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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX9 10declare i32 @llvm.sadd.sat.i32 (i32, i32)11declare i64 @llvm.sadd.sat.i64 (i64, i64)12declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)13 14; fold (sadd_sat x, undef) -> -115define i32 @combine_undef_i32(i32 %a0) {16; CHECK-LABEL: combine_undef_i32:17; CHECK: # %bb.0:18; CHECK-NEXT: movl $-1, %eax19; CHECK-NEXT: retq20 %res = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 undef)21 ret i32 %res22}23 24define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {25; SSE-LABEL: combine_undef_v8i16:26; SSE: # %bb.0:27; SSE-NEXT: pcmpeqd %xmm0, %xmm028; SSE-NEXT: retq29;30; AVX-LABEL: combine_undef_v8i16:31; AVX: # %bb.0:32; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm033; AVX-NEXT: retq34 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)35 ret <8 x i16> %res36}37 38; fold (sadd_sat c1, c2) -> c339define i32 @combine_constfold_i32() {40; CHECK-LABEL: combine_constfold_i32:41; CHECK: # %bb.0:42; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF43; CHECK-NEXT: retq44 %res = call i32 @llvm.sadd.sat.i32(i32 2147483647, i32 100)45 ret i32 %res46}47 48define <8 x i16> @combine_constfold_v8i16() {49; SSE-LABEL: combine_constfold_v8i16:50; SSE: # %bb.0:51; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,0,256,65534,0,65280,32768,0]52; SSE-NEXT: retq53;54; AVX-LABEL: combine_constfold_v8i16:55; AVX: # %bb.0:56; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,0,256,65534,0,65280,32768,0]57; AVX-NEXT: retq58 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>)59 ret <8 x i16> %res60}61 62define <8 x i16> @combine_constfold_undef_v8i16() {63; SSE-LABEL: combine_constfold_undef_v8i16:64; SSE: # %bb.0:65; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,u,65534,0,65280,32768,0]66; SSE-NEXT: retq67;68; AVX-LABEL: combine_constfold_undef_v8i16:69; AVX: # %bb.0:70; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65535,u,65534,0,65280,32768,0]71; AVX-NEXT: retq72 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>)73 ret <8 x i16> %res74}75 76; fold (sadd_sat c, x) -> (sadd_sat x, c)77define i32 @combine_constant_i32(i32 %a0) {78; CHECK-LABEL: combine_constant_i32:79; CHECK: # %bb.0:80; CHECK-NEXT: incl %edi81; CHECK-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF82; CHECK-NEXT: cmovnol %edi, %eax83; CHECK-NEXT: retq84 %res = call i32 @llvm.sadd.sat.i32(i32 1, i32 %a0)85 ret i32 %res86}87 88define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) {89; SSE-LABEL: combine_constant_v8i16:90; SSE: # %bb.0:91; SSE-NEXT: paddsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm092; SSE-NEXT: retq93;94; AVX-LABEL: combine_constant_v8i16:95; AVX: # %bb.0:96; AVX-NEXT: vpaddsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm097; AVX-NEXT: retq98 %res = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)99 ret <8 x i16> %res100}101 102; fold (sadd_sat c, 0) -> x103define i32 @combine_zero_i32(i32 %a0) {104; CHECK-LABEL: combine_zero_i32:105; CHECK: # %bb.0:106; CHECK-NEXT: movl %edi, %eax107; CHECK-NEXT: retq108 %1 = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 0)109 ret i32 %1110}111 112define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) {113; CHECK-LABEL: combine_zero_v8i16:114; CHECK: # %bb.0:115; CHECK-NEXT: retq116 %1 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)117 ret <8 x i16> %1118}119 120; fold (sadd_sat x, y) -> (add x, y) iff no overflow121define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) {122; CHECK-LABEL: combine_no_overflow_i32:123; CHECK: # %bb.0:124; CHECK-NEXT: # kill: def $esi killed $esi def $rsi125; CHECK-NEXT: # kill: def $edi killed $edi def $rdi126; CHECK-NEXT: sarl $16, %edi127; CHECK-NEXT: shrl $16, %esi128; CHECK-NEXT: leal (%rsi,%rdi), %eax129; CHECK-NEXT: retq130 %1 = ashr i32 %a0, 16131 %2 = lshr i32 %a1, 16132 %3 = call i32 @llvm.sadd.sat.i32(i32 %1, i32 %2)133 ret i32 %3134}135 136define <8 x i16> @combine_no_overflow_v8i16(<8 x i16> %a0, <8 x i16> %a1) {137; SSE-LABEL: combine_no_overflow_v8i16:138; SSE: # %bb.0:139; SSE-NEXT: psraw $10, %xmm0140; SSE-NEXT: psrlw $10, %xmm1141; SSE-NEXT: paddw %xmm1, %xmm0142; SSE-NEXT: retq143;144; AVX-LABEL: combine_no_overflow_v8i16:145; AVX: # %bb.0:146; AVX-NEXT: vpsraw $10, %xmm0, %xmm0147; AVX-NEXT: vpsrlw $10, %xmm1, %xmm1148; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0149; AVX-NEXT: retq150 %1 = ashr <8 x i16> %a0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>151 %2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>152 %3 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %1, <8 x i16> %2)153 ret <8 x i16> %3154}155 156; fold (sadd_sat (shuffle x, u, m), (shuffle y, u, m)) -> (shuffle (sadd_sat x, y), u, m)157define <8 x i16> @combine_shuffle_shuffle_v8i16(<8 x i16> %x0, <8 x i16> %y0) {158; SSE-LABEL: combine_shuffle_shuffle_v8i16:159; SSE: # %bb.0:160; SSE-NEXT: paddsw %xmm1, %xmm0161; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]162; SSE-NEXT: retq163;164; AVX-LABEL: combine_shuffle_shuffle_v8i16:165; AVX: # %bb.0:166; AVX-NEXT: vpaddsw %xmm1, %xmm0, %xmm0167; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]168; AVX-NEXT: retq169 %x1= shufflevector <8 x i16> %x0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>170 %y1 = shufflevector <8 x i16> %y0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>171 %res = tail call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x1, <8 x i16> %y1)172 ret <8 x i16> %res173}174