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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX9 10declare i32 @llvm.uadd.sat.i32 (i32, i32)11declare i64 @llvm.uadd.sat.i64 (i64, i64)12declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)13 14; fold (uadd_sat x, undef) -> -115define i32 @combine_undef_i32(i32 %a0) {16; CHECK-LABEL: combine_undef_i32:17; CHECK: # %bb.0:18; CHECK-NEXT: movl $-1, %eax19; CHECK-NEXT: retq20 %res = call i32 @llvm.uadd.sat.i32(i32 %a0, i32 undef)21 ret i32 %res22}23 24define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {25; SSE-LABEL: combine_undef_v8i16:26; SSE: # %bb.0:27; SSE-NEXT: pcmpeqd %xmm0, %xmm028; SSE-NEXT: retq29;30; AVX-LABEL: combine_undef_v8i16:31; AVX: # %bb.0:32; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm033; AVX-NEXT: retq34 %res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)35 ret <8 x i16> %res36}37 38; fold (uadd_sat c1, c2) -> c339define i32 @combine_constfold_i32() {40; CHECK-LABEL: combine_constfold_i32:41; CHECK: # %bb.0:42; CHECK-NEXT: movl $-1, %eax43; CHECK-NEXT: retq44 %res = call i32 @llvm.uadd.sat.i32(i32 4294967295, i32 100)45 ret i32 %res46}47 48define <8 x i16> @combine_constfold_v8i16() {49; SSE-LABEL: combine_constfold_v8i16:50; SSE: # %bb.0:51; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,65535,256,65535,65535,65535,2,65535]52; SSE-NEXT: retq53;54; AVX-LABEL: combine_constfold_v8i16:55; AVX: # %bb.0:56; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65535,256,65535,65535,65535,2,65535]57; AVX-NEXT: retq58 %res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)59 ret <8 x i16> %res60}61 62define <8 x i16> @combine_constfold_undef_v8i16() {63; SSE-LABEL: combine_constfold_undef_v8i16:64; SSE: # %bb.0:65; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,u,65535,65535,65535,2,65535]66; SSE-NEXT: retq67;68; AVX-LABEL: combine_constfold_undef_v8i16:69; AVX: # %bb.0:70; AVX-NEXT: vmovddup {{.*#+}} xmm0 = [65535,65535,2,65535,65535,65535,2,65535]71; AVX-NEXT: # xmm0 = mem[0,0]72; AVX-NEXT: retq73 %res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)74 ret <8 x i16> %res75}76 77; fold (uadd_sat c, x) -> (add_ssat x, c)78define i32 @combine_constant_i32(i32 %a0) {79; CHECK-LABEL: combine_constant_i32:80; CHECK: # %bb.0:81; CHECK-NEXT: incl %edi82; CHECK-NEXT: movl $-1, %eax83; CHECK-NEXT: cmovnel %edi, %eax84; CHECK-NEXT: retq85 %1 = call i32 @llvm.uadd.sat.i32(i32 1, i32 %a0)86 ret i32 %187}88 89define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) {90; SSE-LABEL: combine_constant_v8i16:91; SSE: # %bb.0:92; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm093; SSE-NEXT: retq94;95; AVX-LABEL: combine_constant_v8i16:96; AVX: # %bb.0:97; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm098; AVX-NEXT: retq99 %1 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)100 ret <8 x i16> %1101}102 103; fold (uadd_sat c, 0) -> x104define i32 @combine_zero_i32(i32 %a0) {105; CHECK-LABEL: combine_zero_i32:106; CHECK: # %bb.0:107; CHECK-NEXT: movl %edi, %eax108; CHECK-NEXT: retq109 %1 = call i32 @llvm.uadd.sat.i32(i32 %a0, i32 0)110 ret i32 %1111}112 113define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) {114; CHECK-LABEL: combine_zero_v8i16:115; CHECK: # %bb.0:116; CHECK-NEXT: retq117 %1 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)118 ret <8 x i16> %1119}120 121; fold (uadd_sat x, y) -> (add x, y) iff no overflow122define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) {123; CHECK-LABEL: combine_no_overflow_i32:124; CHECK: # %bb.0:125; CHECK-NEXT: # kill: def $esi killed $esi def $rsi126; CHECK-NEXT: # kill: def $edi killed $edi def $rdi127; CHECK-NEXT: shrl $16, %edi128; CHECK-NEXT: shrl $16, %esi129; CHECK-NEXT: leal (%rsi,%rdi), %eax130; CHECK-NEXT: retq131 %1 = lshr i32 %a0, 16132 %2 = lshr i32 %a1, 16133 %3 = call i32 @llvm.uadd.sat.i32(i32 %1, i32 %2)134 ret i32 %3135}136 137define <8 x i16> @combine_no_overflow_v8i16(<8 x i16> %a0, <8 x i16> %a1) {138; SSE-LABEL: combine_no_overflow_v8i16:139; SSE: # %bb.0:140; SSE-NEXT: psrlw $10, %xmm0141; SSE-NEXT: psrlw $10, %xmm1142; SSE-NEXT: paddw %xmm1, %xmm0143; SSE-NEXT: retq144;145; AVX-LABEL: combine_no_overflow_v8i16:146; AVX: # %bb.0:147; AVX-NEXT: vpsrlw $10, %xmm0, %xmm0148; AVX-NEXT: vpsrlw $10, %xmm1, %xmm1149; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0150; AVX-NEXT: retq151 %1 = lshr <8 x i16> %a0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>152 %2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>153 %3 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %1, <8 x i16> %2)154 ret <8 x i16> %3155}156 157; fold (uadd_sat (shuffle x, u, m), (shuffle y, u, m)) -> (shuffle (uadd_sat x, y), u, m)158define <8 x i16> @combine_shuffle_shuffle_v8i16(<8 x i16> %x0, <8 x i16> %y0) {159; SSE-LABEL: combine_shuffle_shuffle_v8i16:160; SSE: # %bb.0:161; SSE-NEXT: paddusw %xmm1, %xmm0162; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]163; SSE-NEXT: retq164;165; AVX-LABEL: combine_shuffle_shuffle_v8i16:166; AVX: # %bb.0:167; AVX-NEXT: vpaddusw %xmm1, %xmm0, %xmm0168; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]169; AVX-NEXT: retq170 %x1= shufflevector <8 x i16> %x0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>171 %y1 = shufflevector <8 x i16> %y0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>172 %res = tail call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x1, <8 x i16> %y1)173 ret <8 x i16> %res174}175