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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX14; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX25 6; fold (add x, 0) -> x7define <4 x i32> @combine_vec_add_to_zero(<4 x i32> %a) {8; CHECK-LABEL: combine_vec_add_to_zero:9; CHECK: # %bb.0:10; CHECK-NEXT: retq11 %1 = add <4 x i32> %a, zeroinitializer12 ret <4 x i32> %113}14 15; fold ((c1-A)+c2) -> (c1+c2)-A16define <4 x i32> @combine_vec_add_constant_sub(<4 x i32> %a) {17; SSE-LABEL: combine_vec_add_constant_sub:18; SSE: # %bb.0:19; SSE-NEXT: pmovsxbd {{.*#+}} xmm1 = [0,2,4,6]20; SSE-NEXT: psubd %xmm0, %xmm121; SSE-NEXT: movdqa %xmm1, %xmm022; SSE-NEXT: retq23;24; AVX-LABEL: combine_vec_add_constant_sub:25; AVX: # %bb.0:26; AVX-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,2,4,6]27; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm028; AVX-NEXT: retq29 %1 = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %a30 %2 = add <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %131 ret <4 x i32> %232}33 34; fold ((0-A) + B) -> B-A35define <4 x i32> @combine_vec_add_neg0(<4 x i32> %a, <4 x i32> %b) {36; SSE-LABEL: combine_vec_add_neg0:37; SSE: # %bb.0:38; SSE-NEXT: psubd %xmm0, %xmm139; SSE-NEXT: movdqa %xmm1, %xmm040; SSE-NEXT: retq41;42; AVX-LABEL: combine_vec_add_neg0:43; AVX: # %bb.0:44; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm045; AVX-NEXT: retq46 %1 = sub <4 x i32> zeroinitializer, %a47 %2 = add <4 x i32> %1, %b48 ret <4 x i32> %249}50 51; fold (A + (0-B)) -> A-B52define <4 x i32> @combine_vec_add_neg1(<4 x i32> %a, <4 x i32> %b) {53; SSE-LABEL: combine_vec_add_neg1:54; SSE: # %bb.0:55; SSE-NEXT: psubd %xmm1, %xmm056; SSE-NEXT: retq57;58; AVX-LABEL: combine_vec_add_neg1:59; AVX: # %bb.0:60; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm061; AVX-NEXT: retq62 %1 = sub <4 x i32> zeroinitializer, %b63 %2 = add <4 x i32> %a, %164 ret <4 x i32> %265}66 67; fold (A+(B-A)) -> B68define <4 x i32> @combine_vec_add_sub0(<4 x i32> %a, <4 x i32> %b) {69; SSE-LABEL: combine_vec_add_sub0:70; SSE: # %bb.0:71; SSE-NEXT: movaps %xmm1, %xmm072; SSE-NEXT: retq73;74; AVX-LABEL: combine_vec_add_sub0:75; AVX: # %bb.0:76; AVX-NEXT: vmovaps %xmm1, %xmm077; AVX-NEXT: retq78 %1 = sub <4 x i32> %b, %a79 %2 = add <4 x i32> %a, %180 ret <4 x i32> %281}82 83; fold ((B-A)+A) -> B84define <4 x i32> @combine_vec_add_sub1(<4 x i32> %a, <4 x i32> %b) {85; SSE-LABEL: combine_vec_add_sub1:86; SSE: # %bb.0:87; SSE-NEXT: movaps %xmm1, %xmm088; SSE-NEXT: retq89;90; AVX-LABEL: combine_vec_add_sub1:91; AVX: # %bb.0:92; AVX-NEXT: vmovaps %xmm1, %xmm093; AVX-NEXT: retq94 %1 = sub <4 x i32> %b, %a95 %2 = add <4 x i32> %1, %a96 ret <4 x i32> %297}98 99; fold ((A-B)+(C-A)) -> (C-B)100define <4 x i32> @combine_vec_add_sub_sub0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {101; SSE-LABEL: combine_vec_add_sub_sub0:102; SSE: # %bb.0:103; SSE-NEXT: movdqa %xmm2, %xmm0104; SSE-NEXT: psubd %xmm1, %xmm0105; SSE-NEXT: retq106;107; AVX-LABEL: combine_vec_add_sub_sub0:108; AVX: # %bb.0:109; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm0110; AVX-NEXT: retq111 %1 = sub <4 x i32> %a, %b112 %2 = sub <4 x i32> %c, %a113 %3 = add <4 x i32> %1, %2114 ret <4 x i32> %3115}116 117; fold ((A-B)+(B-C)) -> (A-C)118define <4 x i32> @combine_vec_add_sub_sub1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {119; SSE-LABEL: combine_vec_add_sub_sub1:120; SSE: # %bb.0:121; SSE-NEXT: psubd %xmm2, %xmm0122; SSE-NEXT: retq123;124; AVX-LABEL: combine_vec_add_sub_sub1:125; AVX: # %bb.0:126; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0127; AVX-NEXT: retq128 %1 = sub <4 x i32> %a, %b129 %2 = sub <4 x i32> %b, %c130 %3 = add <4 x i32> %1, %2131 ret <4 x i32> %3132}133 134; fold (A+(B-(A+C))) to (B-C)135define <4 x i32> @combine_vec_add_sub_add0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {136; SSE-LABEL: combine_vec_add_sub_add0:137; SSE: # %bb.0:138; SSE-NEXT: movdqa %xmm1, %xmm0139; SSE-NEXT: psubd %xmm2, %xmm0140; SSE-NEXT: retq141;142; AVX-LABEL: combine_vec_add_sub_add0:143; AVX: # %bb.0:144; AVX-NEXT: vpsubd %xmm2, %xmm1, %xmm0145; AVX-NEXT: retq146 %1 = add <4 x i32> %a, %c147 %2 = sub <4 x i32> %b, %1148 %3 = add <4 x i32> %a, %2149 ret <4 x i32> %3150}151 152; fold (A+(B-(C+A))) to (B-C)153define <4 x i32> @combine_vec_add_sub_add1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {154; SSE-LABEL: combine_vec_add_sub_add1:155; SSE: # %bb.0:156; SSE-NEXT: movdqa %xmm1, %xmm0157; SSE-NEXT: psubd %xmm2, %xmm0158; SSE-NEXT: retq159;160; AVX-LABEL: combine_vec_add_sub_add1:161; AVX: # %bb.0:162; AVX-NEXT: vpsubd %xmm2, %xmm1, %xmm0163; AVX-NEXT: retq164 %1 = add <4 x i32> %c, %a165 %2 = sub <4 x i32> %b, %1166 %3 = add <4 x i32> %a, %2167 ret <4 x i32> %3168}169 170; fold (A+((B-A)+C)) to (B+C)171define <4 x i32> @combine_vec_add_sub_add2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {172; SSE-LABEL: combine_vec_add_sub_add2:173; SSE: # %bb.0:174; SSE-NEXT: movdqa %xmm1, %xmm0175; SSE-NEXT: paddd %xmm2, %xmm0176; SSE-NEXT: retq177;178; AVX-LABEL: combine_vec_add_sub_add2:179; AVX: # %bb.0:180; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm0181; AVX-NEXT: retq182 %1 = sub <4 x i32> %b, %a183 %2 = add <4 x i32> %1, %c184 %3 = add <4 x i32> %a, %2185 ret <4 x i32> %3186}187 188; fold (A+((B-A)-C)) to (B-C)189define <4 x i32> @combine_vec_add_sub_add3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {190; SSE-LABEL: combine_vec_add_sub_add3:191; SSE: # %bb.0:192; SSE-NEXT: movdqa %xmm1, %xmm0193; SSE-NEXT: psubd %xmm2, %xmm0194; SSE-NEXT: retq195;196; AVX-LABEL: combine_vec_add_sub_add3:197; AVX: # %bb.0:198; AVX-NEXT: vpsubd %xmm2, %xmm1, %xmm0199; AVX-NEXT: retq200 %1 = sub <4 x i32> %b, %a201 %2 = sub <4 x i32> %1, %c202 %3 = add <4 x i32> %a, %2203 ret <4 x i32> %3204}205 206; fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant207define <4 x i32> @combine_vec_add_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %d) {208; SSE-LABEL: combine_vec_add_sub_sub:209; SSE: # %bb.0:210; SSE-NEXT: paddd %xmm2, %xmm1211; SSE-NEXT: psubd %xmm1, %xmm0212; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0213; SSE-NEXT: retq214;215; AVX-LABEL: combine_vec_add_sub_sub:216; AVX: # %bb.0:217; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1218; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0219; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0220; AVX-NEXT: retq221 %1 = sub <4 x i32> %a, %b222 %2 = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %d223 %3 = add <4 x i32> %1, %2224 ret <4 x i32> %3225}226 227; Check for oneuse limit on fold228define void @PR52039(ptr %pa, ptr %pb) {229; SSE-LABEL: PR52039:230; SSE: # %bb.0:231; SSE-NEXT: movdqu (%rdi), %xmm0232; SSE-NEXT: movdqu 16(%rdi), %xmm1233; SSE-NEXT: pmovsxbd {{.*#+}} xmm2 = [10,10,10,10]234; SSE-NEXT: movdqa %xmm2, %xmm3235; SSE-NEXT: psubd %xmm1, %xmm3236; SSE-NEXT: psubd %xmm0, %xmm2237; SSE-NEXT: movdqa %xmm2, %xmm0238; SSE-NEXT: paddd %xmm0, %xmm0239; SSE-NEXT: paddd %xmm2, %xmm0240; SSE-NEXT: movdqa %xmm3, %xmm1241; SSE-NEXT: paddd %xmm1, %xmm1242; SSE-NEXT: paddd %xmm3, %xmm1243; SSE-NEXT: movdqu %xmm3, 16(%rsi)244; SSE-NEXT: movdqu %xmm2, (%rsi)245; SSE-NEXT: movdqu %xmm1, 16(%rdi)246; SSE-NEXT: movdqu %xmm0, (%rdi)247; SSE-NEXT: retq248;249; AVX1-LABEL: PR52039:250; AVX1: # %bb.0:251; AVX1-NEXT: vbroadcastss {{.*#+}} xmm0 = [10,10,10,10]252; AVX1-NEXT: vpsubd 16(%rdi), %xmm0, %xmm1253; AVX1-NEXT: vpsubd (%rdi), %xmm0, %xmm0254; AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm2255; AVX1-NEXT: vpaddd %xmm0, %xmm2, %xmm2256; AVX1-NEXT: vpaddd %xmm1, %xmm1, %xmm3257; AVX1-NEXT: vpaddd %xmm1, %xmm3, %xmm3258; AVX1-NEXT: vmovdqu %xmm1, 16(%rsi)259; AVX1-NEXT: vmovdqu %xmm0, (%rsi)260; AVX1-NEXT: vmovdqu %xmm3, 16(%rdi)261; AVX1-NEXT: vmovdqu %xmm2, (%rdi)262; AVX1-NEXT: retq263;264; AVX2-LABEL: PR52039:265; AVX2: # %bb.0:266; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm0 = [10,10,10,10,10,10,10,10]267; AVX2-NEXT: vpsubd (%rdi), %ymm0, %ymm0268; AVX2-NEXT: vpaddd %ymm0, %ymm0, %ymm1269; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm1270; AVX2-NEXT: vmovdqu %ymm0, (%rsi)271; AVX2-NEXT: vmovdqu %ymm1, (%rdi)272; AVX2-NEXT: vzeroupper273; AVX2-NEXT: retq274 %load = load <8 x i32>, ptr %pa, align 4275 %sub = sub nsw <8 x i32> <i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>, %load276 %mul = mul nsw <8 x i32> %sub, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>277 store <8 x i32> %sub, ptr %pb, align 4278 store <8 x i32> %mul, ptr %pa, align 4279 ret void280}281 282; fold (a+b) -> (a|b) iff a and b share no bits.283define <4 x i32> @combine_vec_add_uniquebits(<4 x i32> %a, <4 x i32> %b) {284; SSE-LABEL: combine_vec_add_uniquebits:285; SSE: # %bb.0:286; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0287; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1288; SSE-NEXT: orps %xmm1, %xmm0289; SSE-NEXT: retq290;291; AVX1-LABEL: combine_vec_add_uniquebits:292; AVX1: # %bb.0:293; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0294; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1295; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0296; AVX1-NEXT: retq297;298; AVX2-LABEL: combine_vec_add_uniquebits:299; AVX2: # %bb.0:300; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [61680,61680,61680,61680]301; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0302; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [3855,3855,3855,3855]303; AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1304; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0305; AVX2-NEXT: retq306 %1 = and <4 x i32> %a, <i32 61680, i32 61680, i32 61680, i32 61680>307 %2 = and <4 x i32> %b, <i32 3855, i32 3855, i32 3855, i32 3855>308 %3 = add <4 x i32> %1, %2309 ret <4 x i32> %3310}311 312; fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))313define <4 x i32> @combine_vec_add_shl_neg0(<4 x i32> %x, <4 x i32> %y) {314; SSE-LABEL: combine_vec_add_shl_neg0:315; SSE: # %bb.0:316; SSE-NEXT: pslld $5, %xmm1317; SSE-NEXT: psubd %xmm1, %xmm0318; SSE-NEXT: retq319;320; AVX-LABEL: combine_vec_add_shl_neg0:321; AVX: # %bb.0:322; AVX-NEXT: vpslld $5, %xmm1, %xmm1323; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0324; AVX-NEXT: retq325 %1 = sub <4 x i32> zeroinitializer, %y326 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>327 %3 = add <4 x i32> %x, %2328 ret <4 x i32> %3329}330 331; fold (add shl(0 - y, n), x) -> sub(x, shl(y, n))332define <4 x i32> @combine_vec_add_shl_neg1(<4 x i32> %x, <4 x i32> %y) {333; SSE-LABEL: combine_vec_add_shl_neg1:334; SSE: # %bb.0:335; SSE-NEXT: pslld $5, %xmm1336; SSE-NEXT: psubd %xmm1, %xmm0337; SSE-NEXT: retq338;339; AVX-LABEL: combine_vec_add_shl_neg1:340; AVX: # %bb.0:341; AVX-NEXT: vpslld $5, %xmm1, %xmm1342; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0343; AVX-NEXT: retq344 %1 = sub <4 x i32> zeroinitializer, %y345 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>346 %3 = add <4 x i32> %2, %x347 ret <4 x i32> %3348}349 350; (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))351; and similar xforms where the inner op is either ~0 or 0.352define <4 x i32> @combine_vec_add_and_compare(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {353; SSE-LABEL: combine_vec_add_and_compare:354; SSE: # %bb.0:355; SSE-NEXT: pcmpeqd %xmm2, %xmm1356; SSE-NEXT: psubd %xmm1, %xmm0357; SSE-NEXT: retq358;359; AVX-LABEL: combine_vec_add_and_compare:360; AVX: # %bb.0:361; AVX-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1362; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0363; AVX-NEXT: retq364 %1 = icmp eq <4 x i32> %a1, %a2365 %2 = sext <4 x i1> %1 to <4 x i32>366 %3 = and <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>367 %4 = add <4 x i32> %a0, %3368 ret <4 x i32> %4369}370 371; add (sext i1), X -> sub X, (zext i1)372define <4 x i32> @combine_vec_add_sext(<4 x i1> %a0, <4 x i32> %a1) {373; SSE-LABEL: combine_vec_add_sext:374; SSE: # %bb.0:375; SSE-NEXT: pslld $31, %xmm0376; SSE-NEXT: psrad $31, %xmm0377; SSE-NEXT: paddd %xmm1, %xmm0378; SSE-NEXT: retq379;380; AVX-LABEL: combine_vec_add_sext:381; AVX: # %bb.0:382; AVX-NEXT: vpslld $31, %xmm0, %xmm0383; AVX-NEXT: vpsrad $31, %xmm0, %xmm0384; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0385; AVX-NEXT: retq386 %1 = sext <4 x i1> %a0 to <4 x i32>387 %2 = add <4 x i32> %1, %a1388 ret <4 x i32> %2389}390 391; add (sext i1), X -> sub X, (zext i1)392define <4 x i32> @combine_vec_add_sextinreg(<4 x i32> %a0, <4 x i32> %a1) {393; SSE-LABEL: combine_vec_add_sextinreg:394; SSE: # %bb.0:395; SSE-NEXT: pslld $31, %xmm0396; SSE-NEXT: psrad $31, %xmm0397; SSE-NEXT: paddd %xmm1, %xmm0398; SSE-NEXT: retq399;400; AVX-LABEL: combine_vec_add_sextinreg:401; AVX: # %bb.0:402; AVX-NEXT: vpslld $31, %xmm0, %xmm0403; AVX-NEXT: vpsrad $31, %xmm0, %xmm0404; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0405; AVX-NEXT: retq406 %1 = shl <4 x i32> %a0, <i32 31, i32 31, i32 31, i32 31>407 %2 = ashr <4 x i32> %1, <i32 31, i32 31, i32 31, i32 31>408 %3 = add <4 x i32> %2, %a1409 ret <4 x i32> %3410}411 412; (add (add (xor a, -1), b), 1) -> (sub b, a)413define i32 @combine_add_add_not(i32 %a, i32 %b) {414; CHECK-LABEL: combine_add_add_not:415; CHECK: # %bb.0:416; CHECK-NEXT: movl %esi, %eax417; CHECK-NEXT: subl %edi, %eax418; CHECK-NEXT: retq419 %nota = xor i32 %a, -1420 %add = add i32 %nota, %b421 %r = add i32 %add, 1422 ret i32 %r423}424 425define <4 x i32> @combine_vec_add_add_not(<4 x i32> %a, <4 x i32> %b) {426; SSE-LABEL: combine_vec_add_add_not:427; SSE: # %bb.0:428; SSE-NEXT: psubd %xmm0, %xmm1429; SSE-NEXT: movdqa %xmm1, %xmm0430; SSE-NEXT: retq431;432; AVX-LABEL: combine_vec_add_add_not:433; AVX: # %bb.0:434; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0435; AVX-NEXT: retq436 %nota = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>437 %add = add <4 x i32> %nota, %b438 %r = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>439 ret <4 x i32> %r440}441 442define i32 @combine_add_adc_constant(i32 %x, i32 %y, i32 %z) {443; CHECK-LABEL: combine_add_adc_constant:444; CHECK: # %bb.0:445; CHECK-NEXT: movl %edi, %eax446; CHECK-NEXT: btl $7, %edx447; CHECK-NEXT: adcl $32, %eax448; CHECK-NEXT: retq449 %and = lshr i32 %z, 7450 %bit = and i32 %and, 1451 %add = add i32 %x, 32452 %r = add i32 %add, %bit453 ret i32 %r454}455 456declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)457 458define i1 @sadd_add(i32 %a, i32 %b, ptr %p) {459; CHECK-LABEL: sadd_add:460; CHECK: # %bb.0:461; CHECK-NEXT: # kill: def $edi killed $edi def $rdi462; CHECK-NEXT: notl %edi463; CHECK-NEXT: addl %esi, %edi464; CHECK-NEXT: seto %al465; CHECK-NEXT: leal 1(%rdi), %ecx466; CHECK-NEXT: movl %ecx, (%rdx)467; CHECK-NEXT: retq468 %nota = xor i32 %a, -1469 %a0 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %nota, i32 %b)470 %e0 = extractvalue {i32, i1} %a0, 0471 %e1 = extractvalue {i32, i1} %a0, 1472 %res = add i32 %e0, 1473 store i32 %res, ptr %p474 ret i1 %e1475}476 477declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)478 479define i1 @uadd_add(i8 %a, i8 %b, ptr %p) {480; CHECK-LABEL: uadd_add:481; CHECK: # %bb.0:482; CHECK-NEXT: notb %dil483; CHECK-NEXT: addb %sil, %dil484; CHECK-NEXT: setb %al485; CHECK-NEXT: incb %dil486; CHECK-NEXT: movb %dil, (%rdx)487; CHECK-NEXT: retq488 %nota = xor i8 %a, -1489 %a0 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %nota, i8 %b)490 %e0 = extractvalue {i8, i1} %a0, 0491 %e1 = extractvalue {i8, i1} %a0, 1492 %res = add i8 %e0, 1493 store i8 %res, ptr %p494 ret i1 %e1495}496 497; This would crash because we tried to transform an add-with-overflow498; based on the wrong result value.499 500define i1 @PR51238(i1 %b, i8 %x, i8 %y, i8 %z) {501; CHECK-LABEL: PR51238:502; CHECK: # %bb.0:503; CHECK-NEXT: notb %cl504; CHECK-NEXT: addb %dl, %cl505; CHECK-NEXT: setae %al506; CHECK-NEXT: retq507 %ny = xor i8 %y, -1508 %nz = xor i8 %z, -1509 %minxz = select i1 %b, i8 %x, i8 %nz510 %cmpyz = icmp ult i8 %ny, %nz511 %r = add i1 %cmpyz, true512 ret i1 %r513}514 515define <2 x i64> @add_vec_x_notx(<2 x i64> %v0) nounwind {516; SSE-LABEL: add_vec_x_notx:517; SSE: # %bb.0:518; SSE-NEXT: pcmpeqd %xmm0, %xmm0519; SSE-NEXT: retq520;521; AVX-LABEL: add_vec_x_notx:522; AVX: # %bb.0:523; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0524; AVX-NEXT: retq525 %x = xor <2 x i64> %v0, <i64 -1, i64 -1>526 %y = add <2 x i64> %v0, %x527 ret <2 x i64> %y528}529 530define <2 x i64> @add_vec_notx_x(<2 x i64> %v0) nounwind {531; SSE-LABEL: add_vec_notx_x:532; SSE: # %bb.0:533; SSE-NEXT: pcmpeqd %xmm0, %xmm0534; SSE-NEXT: retq535;536; AVX-LABEL: add_vec_notx_x:537; AVX: # %bb.0:538; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0539; AVX-NEXT: retq540 %x = xor <2 x i64> %v0, <i64 -1, i64 -1>541 %y = add <2 x i64> %x, %v0542 ret <2 x i64> %y543}544 545define i64 @add_x_notx(i64 %v0) nounwind {546; CHECK-LABEL: add_x_notx:547; CHECK: # %bb.0:548; CHECK-NEXT: movq $-1, %rax549; CHECK-NEXT: retq550 %x = xor i64 %v0, -1551 %y = add i64 %v0, %x552 ret i64 %y553}554 555define i64 @add_notx_x(i64 %v0) nounwind {556; CHECK-LABEL: add_notx_x:557; CHECK: # %bb.0:558; CHECK-NEXT: movq $-1, %rax559; CHECK-NEXT: retq560 %x = xor i64 %v0, -1561 %y = add i64 %x, %v0562 ret i64 %y563}564