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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX4 5declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone6declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone7 8declare {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone9declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone10 11; fold (sadd x, 0) -> x12define i32 @combine_sadd_zero(i32 %a0, i32 %a1) {13; CHECK-LABEL: combine_sadd_zero:14; CHECK: # %bb.0:15; CHECK-NEXT: movl %edi, %eax16; CHECK-NEXT: retq17 %1 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a0, i32 zeroinitializer)18 %2 = extractvalue {i32, i1} %1, 019 %3 = extractvalue {i32, i1} %1, 120 %4 = select i1 %3, i32 %a1, i32 %221 ret i32 %422}23 24define <4 x i32> @combine_vec_sadd_zero(<4 x i32> %a0, <4 x i32> %a1) {25; CHECK-LABEL: combine_vec_sadd_zero:26; CHECK: # %bb.0:27; CHECK-NEXT: retq28 %1 = call {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)29 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 030 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 131 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %232 ret <4 x i32> %433}34 35; fold (uadd x, 0) -> x36define i32 @combine_uadd_zero(i32 %a0, i32 %a1) {37; CHECK-LABEL: combine_uadd_zero:38; CHECK: # %bb.0:39; CHECK-NEXT: movl %edi, %eax40; CHECK-NEXT: retq41 %1 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a0, i32 zeroinitializer)42 %2 = extractvalue {i32, i1} %1, 043 %3 = extractvalue {i32, i1} %1, 144 %4 = select i1 %3, i32 %a1, i32 %245 ret i32 %446}47 48define <4 x i32> @combine_vec_uadd_zero(<4 x i32> %a0, <4 x i32> %a1) {49; CHECK-LABEL: combine_vec_uadd_zero:50; CHECK: # %bb.0:51; CHECK-NEXT: retq52 %1 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)53 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 054 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 155 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %256 ret <4 x i32> %457}58 59; fold (uadd (xor a, -1), 1) -> (usub 0, a) and flip carry60define i32 @combine_uadd_not(i32 %a0, i32 %a1) {61; CHECK-LABEL: combine_uadd_not:62; CHECK: # %bb.0:63; CHECK-NEXT: movl %edi, %eax64; CHECK-NEXT: negl %eax65; CHECK-NEXT: cmovael %esi, %eax66; CHECK-NEXT: retq67 %1 = xor i32 %a0, -168 %2 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 1)69 %3 = extractvalue {i32, i1} %2, 070 %4 = extractvalue {i32, i1} %2, 171 %5 = select i1 %4, i32 %a1, i32 %372 ret i32 %573}74 75define <4 x i32> @combine_vec_uadd_not(<4 x i32> %a0, <4 x i32> %a1) {76; SSE-LABEL: combine_vec_uadd_not:77; SSE: # %bb.0:78; SSE-NEXT: pxor %xmm2, %xmm279; SSE-NEXT: psubd %xmm0, %xmm280; SSE-NEXT: pmovsxbd {{.*#+}} xmm0 = [1,1,1,1]81; SSE-NEXT: pmaxud %xmm2, %xmm082; SSE-NEXT: pcmpeqd %xmm2, %xmm083; SSE-NEXT: blendvps %xmm0, %xmm2, %xmm184; SSE-NEXT: movaps %xmm1, %xmm085; SSE-NEXT: retq86;87; AVX-LABEL: combine_vec_uadd_not:88; AVX: # %bb.0:89; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm290; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm091; AVX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]92; AVX-NEXT: vpmaxud %xmm2, %xmm0, %xmm293; AVX-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm294; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm095; AVX-NEXT: retq96 %1 = xor <4 x i32> %a0, <i32 -1, i32 -1, i32 -1, i32 -1>97 %2 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)98 %3 = extractvalue {<4 x i32>, <4 x i1>} %2, 099 %4 = extractvalue {<4 x i32>, <4 x i1>} %2, 1100 %5 = select <4 x i1> %4, <4 x i32> %a1, <4 x i32> %3101 ret <4 x i32> %5102}103 104; if uaddo never overflows, replace with add105define i32 @combine_uadd_no_overflow(i32 %a0, i32 %a1, i32 %a2) {106; CHECK-LABEL: combine_uadd_no_overflow:107; CHECK: # %bb.0:108; CHECK-NEXT: # kill: def $edx killed $edx def $rdx109; CHECK-NEXT: # kill: def $esi killed $esi def $rsi110; CHECK-NEXT: shrl $16, %esi111; CHECK-NEXT: shrl $16, %edx112; CHECK-NEXT: leal (%rdx,%rsi), %eax113; CHECK-NEXT: retq114 %1 = lshr i32 %a1, 16115 %2 = lshr i32 %a2, 16116 %3 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 %2)117 %4 = extractvalue {i32, i1} %3, 0118 %5 = extractvalue {i32, i1} %3, 1119 %6 = select i1 %5, i32 %a2, i32 %4120 ret i32 %4121}122 123define <4 x i32> @combine_vec_uadd_no_overflow(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {124; SSE-LABEL: combine_vec_uadd_no_overflow:125; SSE: # %bb.0:126; SSE-NEXT: movdqa %xmm2, %xmm0127; SSE-NEXT: psrld $16, %xmm1128; SSE-NEXT: psrld $16, %xmm0129; SSE-NEXT: paddd %xmm1, %xmm0130; SSE-NEXT: retq131;132; AVX-LABEL: combine_vec_uadd_no_overflow:133; AVX: # %bb.0:134; AVX-NEXT: vpsrld $16, %xmm1, %xmm0135; AVX-NEXT: vpsrld $16, %xmm2, %xmm1136; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0137; AVX-NEXT: retq138 %1 = lshr <4 x i32> %a1, <i32 16, i32 16, i32 16, i32 16>139 %2 = lshr <4 x i32> %a2, <i32 16, i32 16, i32 16, i32 16>140 %3 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> %2)141 %4 = extractvalue {<4 x i32>, <4 x i1>} %3, 0142 %5 = extractvalue {<4 x i32>, <4 x i1>} %3, 1143 %6 = select <4 x i1> %5, <4 x i32> %a2, <4 x i32> %4144 ret <4 x i32> %4145}146