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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefixes=CHECK,AVX,AVX14; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx2 < %s | FileCheck %s --check-prefixes=CHECK,AVX,AVX25; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw < %s | FileCheck %s --check-prefixes=CHECK,AVX,AVX5126 7define i32 @and_self(i32 %x) {8; CHECK-LABEL: and_self:9; CHECK: # %bb.0:10; CHECK-NEXT: movl %edi, %eax11; CHECK-NEXT: retq12 %and = and i32 %x, %x13 ret i32 %and14}15 16define <4 x i32> @and_self_vec(<4 x i32> %x) {17; CHECK-LABEL: and_self_vec:18; CHECK: # %bb.0:19; CHECK-NEXT: retq20 %and = and <4 x i32> %x, %x21 ret <4 x i32> %and22}23 24;25; Verify that the DAGCombiner is able to fold a vector AND into a blend26; if one of the operands to the AND is a vector of all constants, and each27; constant element is either zero or all-ones.28;29 30define <4 x i32> @test1(<4 x i32> %A) {31; SSE-LABEL: test1:32; SSE: # %bb.0:33; SSE-NEXT: xorps %xmm1, %xmm134; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]35; SSE-NEXT: retq36;37; AVX-LABEL: test1:38; AVX: # %bb.0:39; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm140; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]41; AVX-NEXT: retq42 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0>43 ret <4 x i32> %144}45 46define <4 x i32> @test2(<4 x i32> %A) {47; SSE-LABEL: test2:48; SSE: # %bb.0:49; SSE-NEXT: xorps %xmm1, %xmm150; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]51; SSE-NEXT: retq52;53; AVX-LABEL: test2:54; AVX: # %bb.0:55; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm156; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]57; AVX-NEXT: retq58 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0>59 ret <4 x i32> %160}61 62define <4 x i32> @test3(<4 x i32> %A) {63; SSE-LABEL: test3:64; SSE: # %bb.0:65; SSE-NEXT: xorps %xmm1, %xmm166; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3]67; SSE-NEXT: retq68;69; AVX-LABEL: test3:70; AVX: # %bb.0:71; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm172; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3]73; AVX-NEXT: retq74 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0>75 ret <4 x i32> %176}77 78define <4 x i32> @test4(<4 x i32> %A) {79; SSE-LABEL: test4:80; SSE: # %bb.0:81; SSE-NEXT: xorps %xmm1, %xmm182; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]83; SSE-NEXT: retq84;85; AVX-LABEL: test4:86; AVX: # %bb.0:87; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm188; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]89; AVX-NEXT: retq90 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1>91 ret <4 x i32> %192}93 94define <4 x i32> @test5(<4 x i32> %A) {95; SSE-LABEL: test5:96; SSE: # %bb.0:97; SSE-NEXT: xorps %xmm1, %xmm198; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]99; SSE-NEXT: retq100;101; AVX-LABEL: test5:102; AVX: # %bb.0:103; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1104; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]105; AVX-NEXT: retq106 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>107 ret <4 x i32> %1108}109 110define <4 x i32> @test6(<4 x i32> %A) {111; SSE-LABEL: test6:112; SSE: # %bb.0:113; SSE-NEXT: xorps %xmm1, %xmm1114; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]115; SSE-NEXT: retq116;117; AVX-LABEL: test6:118; AVX: # %bb.0:119; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1120; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]121; AVX-NEXT: retq122 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>123 ret <4 x i32> %1124}125 126define <4 x i32> @test7(<4 x i32> %A) {127; SSE-LABEL: test7:128; SSE: # %bb.0:129; SSE-NEXT: xorps %xmm1, %xmm1130; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]131; SSE-NEXT: retq132;133; AVX-LABEL: test7:134; AVX: # %bb.0:135; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1136; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]137; AVX-NEXT: retq138 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1>139 ret <4 x i32> %1140}141 142define <4 x i32> @test8(<4 x i32> %A) {143; SSE-LABEL: test8:144; SSE: # %bb.0:145; SSE-NEXT: xorps %xmm1, %xmm1146; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]147; SSE-NEXT: retq148;149; AVX-LABEL: test8:150; AVX: # %bb.0:151; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1152; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]153; AVX-NEXT: retq154 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1>155 ret <4 x i32> %1156}157 158define <4 x i32> @test9(<4 x i32> %A) {159; SSE-LABEL: test9:160; SSE: # %bb.0:161; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero162; SSE-NEXT: retq163;164; AVX-LABEL: test9:165; AVX: # %bb.0:166; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero167; AVX-NEXT: retq168 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0>169 ret <4 x i32> %1170}171 172define <4 x i32> @test10(<4 x i32> %A) {173; SSE-LABEL: test10:174; SSE: # %bb.0:175; SSE-NEXT: xorps %xmm1, %xmm1176; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]177; SSE-NEXT: retq178;179; AVX-LABEL: test10:180; AVX: # %bb.0:181; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1182; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]183; AVX-NEXT: retq184 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0>185 ret <4 x i32> %1186}187 188define <4 x i32> @test11(<4 x i32> %A) {189; SSE-LABEL: test11:190; SSE: # %bb.0:191; SSE-NEXT: xorps %xmm1, %xmm1192; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]193; SSE-NEXT: retq194;195; AVX-LABEL: test11:196; AVX: # %bb.0:197; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1198; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]199; AVX-NEXT: retq200 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1>201 ret <4 x i32> %1202}203 204define <4 x i32> @test12(<4 x i32> %A) {205; SSE-LABEL: test12:206; SSE: # %bb.0:207; SSE-NEXT: xorps %xmm1, %xmm1208; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]209; SSE-NEXT: retq210;211; AVX-LABEL: test12:212; AVX: # %bb.0:213; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1214; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]215; AVX-NEXT: retq216 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0>217 ret <4 x i32> %1218}219 220define <4 x i32> @test13(<4 x i32> %A) {221; SSE-LABEL: test13:222; SSE: # %bb.0:223; SSE-NEXT: xorps %xmm1, %xmm1224; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]225; SSE-NEXT: retq226;227; AVX-LABEL: test13:228; AVX: # %bb.0:229; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1230; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]231; AVX-NEXT: retq232 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1>233 ret <4 x i32> %1234}235 236define <4 x i32> @test14(<4 x i32> %A) {237; SSE-LABEL: test14:238; SSE: # %bb.0:239; SSE-NEXT: xorps %xmm1, %xmm1240; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]241; SSE-NEXT: retq242;243; AVX-LABEL: test14:244; AVX: # %bb.0:245; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1246; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]247; AVX-NEXT: retq248 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>249 ret <4 x i32> %1250}251 252; X & undef must fold to 0. So lane 0 must choose from the zero vector.253 254define <4 x i32> @undef_lane(<4 x i32> %x) {255; SSE-LABEL: undef_lane:256; SSE: # %bb.0:257; SSE-NEXT: xorps %xmm1, %xmm1258; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]259; SSE-NEXT: retq260;261; AVX-LABEL: undef_lane:262; AVX: # %bb.0:263; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1264; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]265; AVX-NEXT: retq266 %r = and <4 x i32> %x, <i32 undef, i32 4294967295, i32 0, i32 4294967295>267 ret <4 x i32> %r268}269 270define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {271; SSE-LABEL: test15:272; SSE: # %bb.0:273; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]274; SSE-NEXT: retq275;276; AVX-LABEL: test15:277; AVX: # %bb.0:278; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]279; AVX-NEXT: retq280 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1>281 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0>282 %3 = or <4 x i32> %1, %2283 ret <4 x i32> %3284}285 286define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {287; SSE-LABEL: test16:288; SSE: # %bb.0:289; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]290; SSE-NEXT: retq291;292; AVX-LABEL: test16:293; AVX: # %bb.0:294; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]295; AVX-NEXT: retq296 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0>297 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1>298 %3 = or <4 x i32> %1, %2299 ret <4 x i32> %3300}301 302define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {303; SSE-LABEL: test17:304; SSE: # %bb.0:305; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]306; SSE-NEXT: retq307;308; AVX-LABEL: test17:309; AVX: # %bb.0:310; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]311; AVX-NEXT: retq312 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1>313 %2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0>314 %3 = or <4 x i32> %1, %2315 ret <4 x i32> %3316}317 318;319; fold (and (or x, C), D) -> D if (C & D) == D320;321 322define <2 x i64> @and_or_v2i64(<2 x i64> %a0) {323; SSE-LABEL: and_or_v2i64:324; SSE: # %bb.0:325; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,8]326; SSE-NEXT: retq327;328; AVX-LABEL: and_or_v2i64:329; AVX: # %bb.0:330; AVX-NEXT: vmovddup {{.*#+}} xmm0 = [8,8]331; AVX-NEXT: # xmm0 = mem[0,0]332; AVX-NEXT: retq333 %1 = or <2 x i64> %a0, <i64 255, i64 255>334 %2 = and <2 x i64> %1, <i64 8, i64 8>335 ret <2 x i64> %2336}337 338define <4 x i32> @and_or_v4i32(<4 x i32> %a0) {339; SSE-LABEL: and_or_v4i32:340; SSE: # %bb.0:341; SSE-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3]342; SSE-NEXT: retq343;344; AVX-LABEL: and_or_v4i32:345; AVX: # %bb.0:346; AVX-NEXT: vbroadcastss {{.*#+}} xmm0 = [3,3,3,3]347; AVX-NEXT: retq348 %1 = or <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>349 %2 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>350 ret <4 x i32> %2351}352 353define <8 x i16> @and_or_v8i16(<8 x i16> %a0) {354; SSE-LABEL: and_or_v8i16:355; SSE: # %bb.0:356; SSE-NEXT: movaps {{.*#+}} xmm0 = [15,7,3,1,14,10,2,32767]357; SSE-NEXT: retq358;359; AVX-LABEL: and_or_v8i16:360; AVX: # %bb.0:361; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [15,7,3,1,14,10,2,32767]362; AVX-NEXT: retq363 %1 = or <8 x i16> %a0, <i16 255, i16 127, i16 63, i16 31, i16 15, i16 31, i16 63, i16 -1>364 %2 = and <8 x i16> %1, <i16 15, i16 7, i16 3, i16 1, i16 14, i16 10, i16 2, i16 32767>365 ret <8 x i16> %2366}367 368;369; Check we merge and(ext(and(x,c1)),c2) before an and gets folded to a shuffle clear mask370;371 372define <8 x i32> @clear_sext_and(<8 x i16> %x) {373; SSE-LABEL: clear_sext_and:374; SSE: # %bb.0:375; SSE-NEXT: pmovsxwd %xmm0, %xmm2376; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2377; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]378; SSE-NEXT: pmovsxwd %xmm0, %xmm1379; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1380; SSE-NEXT: movdqa %xmm2, %xmm0381; SSE-NEXT: retq382;383; AVX1-LABEL: clear_sext_and:384; AVX1: # %bb.0:385; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1386; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]387; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0388; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0389; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0390; AVX1-NEXT: retq391;392; AVX2-LABEL: clear_sext_and:393; AVX2: # %bb.0:394; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0395; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0396; AVX2-NEXT: retq397;398; AVX512-LABEL: clear_sext_and:399; AVX512: # %bb.0:400; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0401; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0402; AVX512-NEXT: retq403 %1 = and <8 x i16> %x, <i16 -1, i16 3, i16 7, i16 15, i16 31, i16 63, i16 127, i16 -1>404 %2 = sext <8 x i16> %1 to <8 x i32>405 %3 = and <8 x i32> %2, <i32 -1, i32 0, i32 -1, i32 0, i32 0, i32 -1, i32 -1, i32 -1>406 ret <8 x i32> %3407}408 409define <8 x i32> @clear_zext_and(<8 x i16> %x) {410; SSE-LABEL: clear_zext_and:411; SSE: # %bb.0:412; SSE-NEXT: movdqa %xmm0, %xmm1413; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero414; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]415; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1416; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0417; SSE-NEXT: retq418;419; AVX1-LABEL: clear_zext_and:420; AVX1: # %bb.0:421; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7]422; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero423; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0424; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0425; AVX1-NEXT: retq426;427; AVX2-LABEL: clear_zext_and:428; AVX2: # %bb.0:429; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero430; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0431; AVX2-NEXT: retq432;433; AVX512-LABEL: clear_zext_and:434; AVX512: # %bb.0:435; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero436; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0437; AVX512-NEXT: retq438 %1 = and <8 x i16> %x, <i16 -1, i16 3, i16 7, i16 15, i16 31, i16 63, i16 127, i16 -1>439 %2 = zext <8 x i16> %1 to <8 x i32>440 %3 = and <8 x i32> %2, <i32 -1, i32 0, i32 -1, i32 0, i32 0, i32 -1, i32 -1, i32 -1>441 ret <8 x i32> %3442}443 444;445; known bits folding446;447 448define <2 x i64> @and_or_zext_v2i32(<2 x i32> %a0) {449; SSE-LABEL: and_or_zext_v2i32:450; SSE: # %bb.0:451; SSE-NEXT: xorps %xmm0, %xmm0452; SSE-NEXT: retq453;454; AVX-LABEL: and_or_zext_v2i32:455; AVX: # %bb.0:456; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0457; AVX-NEXT: retq458 %1 = zext <2 x i32> %a0 to <2 x i64>459 %2 = or <2 x i64> %1, <i64 1, i64 1>460 %3 = and <2 x i64> %2, <i64 4294967296, i64 4294967296>461 ret <2 x i64> %3462}463 464define <4 x i32> @and_or_zext_v4i16(<4 x i16> %a0) {465; SSE-LABEL: and_or_zext_v4i16:466; SSE: # %bb.0:467; SSE-NEXT: xorps %xmm0, %xmm0468; SSE-NEXT: retq469;470; AVX-LABEL: and_or_zext_v4i16:471; AVX: # %bb.0:472; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0473; AVX-NEXT: retq474 %1 = zext <4 x i16> %a0 to <4 x i32>475 %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>476 %3 = and <4 x i32> %2, <i32 65536, i32 65536, i32 65536, i32 65536>477 ret <4 x i32> %3478}479 480;481; known sign bits folding482;483 484define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) {485; SSE-LABEL: ashr_mask1_v8i16:486; SSE: # %bb.0:487; SSE-NEXT: psrlw $15, %xmm0488; SSE-NEXT: retq489;490; AVX-LABEL: ashr_mask1_v8i16:491; AVX: # %bb.0:492; AVX-NEXT: vpsrlw $15, %xmm0, %xmm0493; AVX-NEXT: retq494 %1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>495 %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>496 ret <8 x i16> %2497}498 499define <4 x i32> @ashr_mask7_v4i32(<4 x i32> %a0) {500; SSE-LABEL: ashr_mask7_v4i32:501; SSE: # %bb.0:502; SSE-NEXT: psrad $31, %xmm0503; SSE-NEXT: psrld $29, %xmm0504; SSE-NEXT: retq505;506; AVX-LABEL: ashr_mask7_v4i32:507; AVX: # %bb.0:508; AVX-NEXT: vpsrad $31, %xmm0, %xmm0509; AVX-NEXT: vpsrld $29, %xmm0, %xmm0510; AVX-NEXT: retq511 %1 = ashr <4 x i32> %a0, <i32 31, i32 31, i32 31, i32 31>512 %2 = and <4 x i32> %1, <i32 7, i32 7, i32 7, i32 7>513 ret <4 x i32> %2514}515 516;517; SimplifyDemandedBits518;519 520; PR34620 - redundant PAND after vector shift of a byte vector (PSRLW)521define <16 x i8> @PR34620(<16 x i8> %a0, <16 x i8> %a1) {522; SSE-LABEL: PR34620:523; SSE: # %bb.0:524; SSE-NEXT: psrlw $1, %xmm0525; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0526; SSE-NEXT: paddb %xmm1, %xmm0527; SSE-NEXT: retq528;529; AVX1-LABEL: PR34620:530; AVX1: # %bb.0:531; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm0532; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0533; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0534; AVX1-NEXT: retq535;536; AVX2-LABEL: PR34620:537; AVX2: # %bb.0:538; AVX2-NEXT: vpsrlw $1, %xmm0, %xmm0539; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0540; AVX2-NEXT: vpaddb %xmm1, %xmm0, %xmm0541; AVX2-NEXT: retq542;543; AVX512-LABEL: PR34620:544; AVX512: # %bb.0:545; AVX512-NEXT: vpsrlw $1, %xmm0, %xmm0546; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0547; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0548; AVX512-NEXT: retq549 %1 = lshr <16 x i8> %a0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>550 %2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>551 %3 = add <16 x i8> %2, %a1552 ret <16 x i8> %3553}554 555;556; Simplify and with a broadcasted negated scalar557;558 559define <8 x i64> @neg_scalar_broadcast_v8i64_arg(i64 %a0, <8 x i64> %a1) {560; SSE-LABEL: neg_scalar_broadcast_v8i64_arg:561; SSE: # %bb.0:562; SSE-NEXT: notq %rdi563; SSE-NEXT: movq %rdi, %xmm4564; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,1,0,1]565; SSE-NEXT: pand %xmm4, %xmm0566; SSE-NEXT: pand %xmm4, %xmm1567; SSE-NEXT: pand %xmm4, %xmm2568; SSE-NEXT: pand %xmm4, %xmm3569; SSE-NEXT: retq570;571; AVX1-LABEL: neg_scalar_broadcast_v8i64_arg:572; AVX1: # %bb.0:573; AVX1-NEXT: notq %rdi574; AVX1-NEXT: vmovq %rdi, %xmm2575; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]576; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2577; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0578; AVX1-NEXT: vandps %ymm1, %ymm2, %ymm1579; AVX1-NEXT: retq580;581; AVX2-LABEL: neg_scalar_broadcast_v8i64_arg:582; AVX2: # %bb.0:583; AVX2-NEXT: notq %rdi584; AVX2-NEXT: vmovq %rdi, %xmm2585; AVX2-NEXT: vpbroadcastq %xmm2, %ymm2586; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0587; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1588; AVX2-NEXT: retq589;590; AVX512-LABEL: neg_scalar_broadcast_v8i64_arg:591; AVX512: # %bb.0:592; AVX512-NEXT: vpbroadcastq %rdi, %zmm1593; AVX512-NEXT: vpandnq %zmm0, %zmm1, %zmm0594; AVX512-NEXT: retq595 %1 = xor i64 %a0, -1596 %2 = insertelement <8 x i64> undef, i64 %1, i64 0597 %3 = shufflevector <8 x i64> %2, <8 x i64> poison, <8 x i32> zeroinitializer598 %4 = and <8 x i64> %3, %a1599 ret <8 x i64> %4600}601 602define <8 x i64> @neg_scalar_broadcast_v8i64(i64 %a0, <2 x i64> %a1) {603; SSE-LABEL: neg_scalar_broadcast_v8i64:604; SSE: # %bb.0:605; SSE-NEXT: movdqa %xmm0, %xmm2606; SSE-NEXT: notq %rdi607; SSE-NEXT: movq %rdi, %xmm0608; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1]609; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]610; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]611; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]612; SSE-NEXT: pand %xmm4, %xmm0613; SSE-NEXT: pand %xmm4, %xmm1614; SSE-NEXT: pand %xmm4, %xmm2615; SSE-NEXT: pand %xmm4, %xmm3616; SSE-NEXT: retq617;618; AVX1-LABEL: neg_scalar_broadcast_v8i64:619; AVX1: # %bb.0:620; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0621; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[0,1,0,1]622; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1623; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0624; AVX1-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1,0,3,3]625; AVX1-NEXT: vmovq %rdi, %xmm2626; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]627; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2628; AVX1-NEXT: vandnpd %ymm0, %ymm2, %ymm0629; AVX1-NEXT: vandnpd %ymm1, %ymm2, %ymm1630; AVX1-NEXT: retq631;632; AVX2-LABEL: neg_scalar_broadcast_v8i64:633; AVX2: # %bb.0:634; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0635; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,1,0,0]636; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,1,1]637; AVX2-NEXT: vmovq %rdi, %xmm2638; AVX2-NEXT: vpbroadcastq %xmm2, %ymm2639; AVX2-NEXT: vpandn %ymm0, %ymm2, %ymm0640; AVX2-NEXT: vpandn %ymm1, %ymm2, %ymm1641; AVX2-NEXT: retq642;643; AVX512-LABEL: neg_scalar_broadcast_v8i64:644; AVX512: # %bb.0:645; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0646; AVX512-NEXT: vpbroadcastq %rdi, %zmm1647; AVX512-NEXT: vpmovsxbq {{.*#+}} zmm2 = [1,0,1,1,0,1,0,0]648; AVX512-NEXT: vpermq %zmm0, %zmm2, %zmm0649; AVX512-NEXT: vpandnq %zmm0, %zmm1, %zmm0650; AVX512-NEXT: retq651 %1 = xor i64 %a0, -1652 %2 = insertelement <8 x i64> undef, i64 %1, i64 0653 %3 = shufflevector <8 x i64> %2, <8 x i64> poison, <8 x i32> zeroinitializer654 %4 = shufflevector <2 x i64> %a1, <2 x i64> poison, <8 x i32> <i32 1, i32 0, i32 1, i32 1, i32 0, i32 1, i32 0, i32 0>655 %5 = and <8 x i64> %4, %3656 ret <8 x i64> %5657}658 659define <4 x i64> @neg_scalar_broadcast_v4i64_arg(i64 %a0, <4 x i64> %a1) {660; SSE-LABEL: neg_scalar_broadcast_v4i64_arg:661; SSE: # %bb.0:662; SSE-NEXT: notq %rdi663; SSE-NEXT: movq %rdi, %xmm2664; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]665; SSE-NEXT: pand %xmm2, %xmm0666; SSE-NEXT: pand %xmm2, %xmm1667; SSE-NEXT: retq668;669; AVX1-LABEL: neg_scalar_broadcast_v4i64_arg:670; AVX1: # %bb.0:671; AVX1-NEXT: vmovq %rdi, %xmm1672; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]673; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1674; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm0675; AVX1-NEXT: retq676;677; AVX2-LABEL: neg_scalar_broadcast_v4i64_arg:678; AVX2: # %bb.0:679; AVX2-NEXT: vmovq %rdi, %xmm1680; AVX2-NEXT: vpbroadcastq %xmm1, %ymm1681; AVX2-NEXT: vpandn %ymm0, %ymm1, %ymm0682; AVX2-NEXT: retq683;684; AVX512-LABEL: neg_scalar_broadcast_v4i64_arg:685; AVX512: # %bb.0:686; AVX512-NEXT: vpbroadcastq %rdi, %ymm1687; AVX512-NEXT: vpandn %ymm0, %ymm1, %ymm0688; AVX512-NEXT: retq689 %1 = xor i64 %a0, -1690 %2 = insertelement <4 x i64> undef, i64 %1, i64 0691 %3 = shufflevector <4 x i64> %2, <4 x i64> poison, <4 x i32> zeroinitializer692 %4 = and <4 x i64> %3, %a1693 ret <4 x i64> %4694}695 696define <4 x i64> @neg_scalar_broadcast_v4i64(i64 %a0, <2 x i64> %a1) {697; SSE-LABEL: neg_scalar_broadcast_v4i64:698; SSE: # %bb.0:699; SSE-NEXT: notq %rdi700; SSE-NEXT: movq %rdi, %xmm1701; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,1,0,1]702; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]703; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]704; SSE-NEXT: pand %xmm2, %xmm0705; SSE-NEXT: pand %xmm2, %xmm1706; SSE-NEXT: retq707;708; AVX1-LABEL: neg_scalar_broadcast_v4i64:709; AVX1: # %bb.0:710; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0711; AVX1-NEXT: vmovq %rdi, %xmm1712; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]713; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1714; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0715; AVX1-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1,0,3,3]716; AVX1-NEXT: vandnpd %ymm0, %ymm1, %ymm0717; AVX1-NEXT: retq718;719; AVX2-LABEL: neg_scalar_broadcast_v4i64:720; AVX2: # %bb.0:721; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0722; AVX2-NEXT: vmovq %rdi, %xmm1723; AVX2-NEXT: vpbroadcastq %xmm1, %ymm1724; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,1,1]725; AVX2-NEXT: vpandn %ymm0, %ymm1, %ymm0726; AVX2-NEXT: retq727;728; AVX512-LABEL: neg_scalar_broadcast_v4i64:729; AVX512: # %bb.0:730; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0731; AVX512-NEXT: vpbroadcastq %rdi, %ymm1732; AVX512-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,1,1]733; AVX512-NEXT: vpandn %ymm0, %ymm1, %ymm0734; AVX512-NEXT: retq735 %1 = xor i64 %a0, -1736 %2 = insertelement <4 x i64> undef, i64 %1, i64 0737 %3 = shufflevector <4 x i64> %2, <4 x i64> poison, <4 x i32> zeroinitializer738 %4 = shufflevector <2 x i64> %a1, <2 x i64> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 1>739 %5 = and <4 x i64> %4, %3740 ret <4 x i64> %5741}742 743define <2 x i64> @neg_scalar_broadcast_v2i64(i64 %a0, <2 x i64> %a1) {744; SSE-LABEL: neg_scalar_broadcast_v2i64:745; SSE: # %bb.0:746; SSE-NEXT: movq %rdi, %xmm1747; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]748; SSE-NEXT: pandn %xmm0, %xmm1749; SSE-NEXT: movdqa %xmm1, %xmm0750; SSE-NEXT: retq751;752; AVX1-LABEL: neg_scalar_broadcast_v2i64:753; AVX1: # %bb.0:754; AVX1-NEXT: vmovq %rdi, %xmm1755; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]756; AVX1-NEXT: vpandn %xmm0, %xmm1, %xmm0757; AVX1-NEXT: retq758;759; AVX2-LABEL: neg_scalar_broadcast_v2i64:760; AVX2: # %bb.0:761; AVX2-NEXT: vmovq %rdi, %xmm1762; AVX2-NEXT: vpbroadcastq %xmm1, %xmm1763; AVX2-NEXT: vpandn %xmm0, %xmm1, %xmm0764; AVX2-NEXT: retq765;766; AVX512-LABEL: neg_scalar_broadcast_v2i64:767; AVX512: # %bb.0:768; AVX512-NEXT: vpbroadcastq %rdi, %xmm1769; AVX512-NEXT: vpandn %xmm0, %xmm1, %xmm0770; AVX512-NEXT: retq771 %1 = xor i64 %a0, -1772 %2 = insertelement <2 x i64> undef, i64 %1, i64 0773 %3 = shufflevector <2 x i64> %2, <2 x i64> poison, <2 x i32> zeroinitializer774 %4 = and <2 x i64> %3, %a1775 ret <2 x i64> %4776}777 778define <2 x i64> @casted_neg_scalar_broadcast_v2i64(<2 x i32> %a0, <2 x i64> %a1) {779; SSE-LABEL: casted_neg_scalar_broadcast_v2i64:780; SSE: # %bb.0:781; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]782; SSE-NEXT: pandn %xmm1, %xmm0783; SSE-NEXT: retq784;785; AVX1-LABEL: casted_neg_scalar_broadcast_v2i64:786; AVX1: # %bb.0:787; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,0,1]788; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0789; AVX1-NEXT: retq790;791; AVX2-LABEL: casted_neg_scalar_broadcast_v2i64:792; AVX2: # %bb.0:793; AVX2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]794; AVX2-NEXT: vandnps %xmm1, %xmm0, %xmm0795; AVX2-NEXT: retq796;797; AVX512-LABEL: casted_neg_scalar_broadcast_v2i64:798; AVX512: # %bb.0:799; AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]800; AVX512-NEXT: vandnps %xmm1, %xmm0, %xmm0801; AVX512-NEXT: retq802 %1 = xor <2 x i32> %a0, <i32 -1, i32 -1>803 %2 = bitcast <2 x i32> %1 to i64804 %3 = insertelement <2 x i64> undef, i64 %2, i64 0805 %4 = shufflevector <2 x i64> %3, <2 x i64> poison, <2 x i32> zeroinitializer806 %5 = and <2 x i64> %4, %a1807 ret <2 x i64> %5808}809 810define <8 x i32> @neg_scalar_broadcast_v8i32(i32 %a0, <8 x i32> %a1) {811; SSE-LABEL: neg_scalar_broadcast_v8i32:812; SSE: # %bb.0:813; SSE-NEXT: notl %edi814; SSE-NEXT: movd %edi, %xmm2815; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]816; SSE-NEXT: pand %xmm2, %xmm0817; SSE-NEXT: pand %xmm2, %xmm1818; SSE-NEXT: retq819;820; AVX1-LABEL: neg_scalar_broadcast_v8i32:821; AVX1: # %bb.0:822; AVX1-NEXT: vmovd %edi, %xmm1823; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]824; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1825; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm0826; AVX1-NEXT: retq827;828; AVX2-LABEL: neg_scalar_broadcast_v8i32:829; AVX2: # %bb.0:830; AVX2-NEXT: vmovd %edi, %xmm1831; AVX2-NEXT: vpbroadcastd %xmm1, %ymm1832; AVX2-NEXT: vpandn %ymm0, %ymm1, %ymm0833; AVX2-NEXT: retq834;835; AVX512-LABEL: neg_scalar_broadcast_v8i32:836; AVX512: # %bb.0:837; AVX512-NEXT: vpbroadcastd %edi, %ymm1838; AVX512-NEXT: vpandn %ymm0, %ymm1, %ymm0839; AVX512-NEXT: retq840 %1 = xor i32 %a0, -1841 %2 = insertelement <8 x i32> undef, i32 %1, i64 0842 %3 = shufflevector <8 x i32> %2, <8 x i32> poison, <8 x i32> zeroinitializer843 %4 = and <8 x i32> %3, %a1844 ret <8 x i32> %4845}846 847define <8 x i16> @neg_scalar_broadcast_v8i16(i16 %a0, <8 x i16> %a1) {848; SSE-LABEL: neg_scalar_broadcast_v8i16:849; SSE: # %bb.0:850; SSE-NEXT: movd %edi, %xmm1851; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]852; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]853; SSE-NEXT: pandn %xmm0, %xmm1854; SSE-NEXT: movdqa %xmm1, %xmm0855; SSE-NEXT: retq856;857; AVX1-LABEL: neg_scalar_broadcast_v8i16:858; AVX1: # %bb.0:859; AVX1-NEXT: vmovd %edi, %xmm1860; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]861; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]862; AVX1-NEXT: vpandn %xmm0, %xmm1, %xmm0863; AVX1-NEXT: retq864;865; AVX2-LABEL: neg_scalar_broadcast_v8i16:866; AVX2: # %bb.0:867; AVX2-NEXT: vmovd %edi, %xmm1868; AVX2-NEXT: vpbroadcastw %xmm1, %xmm1869; AVX2-NEXT: vpandn %xmm0, %xmm1, %xmm0870; AVX2-NEXT: retq871;872; AVX512-LABEL: neg_scalar_broadcast_v8i16:873; AVX512: # %bb.0:874; AVX512-NEXT: vpbroadcastw %edi, %xmm1875; AVX512-NEXT: vpandn %xmm0, %xmm1, %xmm0876; AVX512-NEXT: retq877 %1 = xor i16 %a0, -1878 %2 = insertelement <8 x i16> undef, i16 %1, i64 0879 %3 = shufflevector <8 x i16> %2, <8 x i16> poison, <8 x i32> zeroinitializer880 %4 = and <8 x i16> %3, %a1881 ret <8 x i16> %4882}883 884define <16 x i8> @neg_scalar_broadcast_v16i8(i8 %a0, <16 x i8> %a1) {885; SSE-LABEL: neg_scalar_broadcast_v16i8:886; SSE: # %bb.0:887; SSE-NEXT: movd %edi, %xmm1888; SSE-NEXT: pxor %xmm2, %xmm2889; SSE-NEXT: pshufb %xmm2, %xmm1890; SSE-NEXT: pandn %xmm0, %xmm1891; SSE-NEXT: movdqa %xmm1, %xmm0892; SSE-NEXT: retq893;894; AVX1-LABEL: neg_scalar_broadcast_v16i8:895; AVX1: # %bb.0:896; AVX1-NEXT: vmovd %edi, %xmm1897; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2898; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1899; AVX1-NEXT: vpandn %xmm0, %xmm1, %xmm0900; AVX1-NEXT: retq901;902; AVX2-LABEL: neg_scalar_broadcast_v16i8:903; AVX2: # %bb.0:904; AVX2-NEXT: vmovd %edi, %xmm1905; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1906; AVX2-NEXT: vpandn %xmm0, %xmm1, %xmm0907; AVX2-NEXT: retq908;909; AVX512-LABEL: neg_scalar_broadcast_v16i8:910; AVX512: # %bb.0:911; AVX512-NEXT: vpbroadcastb %edi, %xmm1912; AVX512-NEXT: vpandn %xmm0, %xmm1, %xmm0913; AVX512-NEXT: retq914 %1 = xor i8 %a0, -1915 %2 = insertelement <16 x i8> undef, i8 %1, i64 0916 %3 = shufflevector <16 x i8> %2, <16 x i8> poison, <16 x i32> zeroinitializer917 %4 = and <16 x i8> %3, %a1918 ret <16 x i8> %4919}920 921define <64 x i8> @neg_scalar_broadcast_v64i8(i8 %a0, <64 x i8> %a1) {922; SSE-LABEL: neg_scalar_broadcast_v64i8:923; SSE: # %bb.0:924; SSE-NEXT: notb %dil925; SSE-NEXT: movzbl %dil, %eax926; SSE-NEXT: movd %eax, %xmm4927; SSE-NEXT: pxor %xmm5, %xmm5928; SSE-NEXT: pshufb %xmm5, %xmm4929; SSE-NEXT: pand %xmm4, %xmm0930; SSE-NEXT: pand %xmm4, %xmm1931; SSE-NEXT: pand %xmm4, %xmm2932; SSE-NEXT: pand %xmm4, %xmm3933; SSE-NEXT: retq934;935; AVX1-LABEL: neg_scalar_broadcast_v64i8:936; AVX1: # %bb.0:937; AVX1-NEXT: notb %dil938; AVX1-NEXT: vmovd %edi, %xmm2939; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3940; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2941; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2942; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0943; AVX1-NEXT: vandps %ymm1, %ymm2, %ymm1944; AVX1-NEXT: retq945;946; AVX2-LABEL: neg_scalar_broadcast_v64i8:947; AVX2: # %bb.0:948; AVX2-NEXT: notb %dil949; AVX2-NEXT: vmovd %edi, %xmm2950; AVX2-NEXT: vpbroadcastb %xmm2, %ymm2951; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0952; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1953; AVX2-NEXT: retq954;955; AVX512-LABEL: neg_scalar_broadcast_v64i8:956; AVX512: # %bb.0:957; AVX512-NEXT: vpbroadcastb %edi, %zmm1958; AVX512-NEXT: vpandnq %zmm0, %zmm1, %zmm0959; AVX512-NEXT: retq960 %1 = xor i8 %a0, -1961 %2 = insertelement <64 x i8> undef, i8 %1, i64 0962 %3 = shufflevector <64 x i8> %2, <64 x i8> poison, <64 x i32> zeroinitializer963 %4 = and <64 x i8> %3, %a1964 ret <64 x i8> %4965}966 967define <8 x i64> @neg_scalar_broadcast_v64i8_v8i64(i8 %a0, <8 x i64> %a1) {968; SSE-LABEL: neg_scalar_broadcast_v64i8_v8i64:969; SSE: # %bb.0:970; SSE-NEXT: notb %dil971; SSE-NEXT: movzbl %dil, %eax972; SSE-NEXT: movd %eax, %xmm4973; SSE-NEXT: pxor %xmm5, %xmm5974; SSE-NEXT: pshufb %xmm5, %xmm4975; SSE-NEXT: pand %xmm4, %xmm0976; SSE-NEXT: pand %xmm4, %xmm1977; SSE-NEXT: pand %xmm4, %xmm2978; SSE-NEXT: pand %xmm4, %xmm3979; SSE-NEXT: retq980;981; AVX1-LABEL: neg_scalar_broadcast_v64i8_v8i64:982; AVX1: # %bb.0:983; AVX1-NEXT: notb %dil984; AVX1-NEXT: vmovd %edi, %xmm2985; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3986; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2987; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2988; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0989; AVX1-NEXT: vandps %ymm1, %ymm2, %ymm1990; AVX1-NEXT: retq991;992; AVX2-LABEL: neg_scalar_broadcast_v64i8_v8i64:993; AVX2: # %bb.0:994; AVX2-NEXT: notb %dil995; AVX2-NEXT: vmovd %edi, %xmm2996; AVX2-NEXT: vpbroadcastb %xmm2, %ymm2997; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0998; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1999; AVX2-NEXT: retq1000;1001; AVX512-LABEL: neg_scalar_broadcast_v64i8_v8i64:1002; AVX512: # %bb.0:1003; AVX512-NEXT: vpbroadcastb %edi, %zmm11004; AVX512-NEXT: vpandnq %zmm0, %zmm1, %zmm01005; AVX512-NEXT: retq1006 %1 = xor i8 %a0, -11007 %2 = insertelement <64 x i8> undef, i8 %1, i64 01008 %3 = shufflevector <64 x i8> %2, <64 x i8> poison, <64 x i32> zeroinitializer1009 %4 = bitcast <64 x i8> %3 to <8 x i64>1010 %5 = and <8 x i64> %4, %a11011 ret <8 x i64> %51012}1013 1014define <4 x i64> @neg_scalar_broadcast_v32i8_v4i64(i8 %a0, <4 x i64> %a1) {1015; SSE-LABEL: neg_scalar_broadcast_v32i8_v4i64:1016; SSE: # %bb.0:1017; SSE-NEXT: notb %dil1018; SSE-NEXT: movzbl %dil, %eax1019; SSE-NEXT: movd %eax, %xmm21020; SSE-NEXT: pxor %xmm3, %xmm31021; SSE-NEXT: pshufb %xmm3, %xmm21022; SSE-NEXT: pand %xmm2, %xmm01023; SSE-NEXT: pand %xmm2, %xmm11024; SSE-NEXT: retq1025;1026; AVX1-LABEL: neg_scalar_broadcast_v32i8_v4i64:1027; AVX1: # %bb.0:1028; AVX1-NEXT: vmovd %edi, %xmm11029; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm21030; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm11031; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm11032; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm01033; AVX1-NEXT: retq1034;1035; AVX2-LABEL: neg_scalar_broadcast_v32i8_v4i64:1036; AVX2: # %bb.0:1037; AVX2-NEXT: vmovd %edi, %xmm11038; AVX2-NEXT: vpbroadcastb %xmm1, %ymm11039; AVX2-NEXT: vpandn %ymm0, %ymm1, %ymm01040; AVX2-NEXT: retq1041;1042; AVX512-LABEL: neg_scalar_broadcast_v32i8_v4i64:1043; AVX512: # %bb.0:1044; AVX512-NEXT: vpbroadcastb %edi, %ymm11045; AVX512-NEXT: vpandn %ymm0, %ymm1, %ymm01046; AVX512-NEXT: retq1047 %1 = xor i8 %a0, -11048 %2 = insertelement <32 x i8> undef, i8 %1, i64 01049 %3 = shufflevector <32 x i8> %2, <32 x i8> poison, <32 x i32> zeroinitializer1050 %4 = bitcast <32 x i8> %3 to <4 x i64>1051 %5 = and <4 x i64> %4, %a11052 ret <4 x i64> %51053}1054 1055define <2 x i64> @neg_scalar_broadcast_v16i8_v2i64(i8 %a0, <2 x i64> %a1) {1056; SSE-LABEL: neg_scalar_broadcast_v16i8_v2i64:1057; SSE: # %bb.0:1058; SSE-NEXT: movd %edi, %xmm11059; SSE-NEXT: pxor %xmm2, %xmm21060; SSE-NEXT: pshufb %xmm2, %xmm11061; SSE-NEXT: pandn %xmm0, %xmm11062; SSE-NEXT: movdqa %xmm1, %xmm01063; SSE-NEXT: retq1064;1065; AVX1-LABEL: neg_scalar_broadcast_v16i8_v2i64:1066; AVX1: # %bb.0:1067; AVX1-NEXT: vmovd %edi, %xmm11068; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm21069; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm11070; AVX1-NEXT: vpandn %xmm0, %xmm1, %xmm01071; AVX1-NEXT: retq1072;1073; AVX2-LABEL: neg_scalar_broadcast_v16i8_v2i64:1074; AVX2: # %bb.0:1075; AVX2-NEXT: vmovd %edi, %xmm11076; AVX2-NEXT: vpbroadcastb %xmm1, %xmm11077; AVX2-NEXT: vpandn %xmm0, %xmm1, %xmm01078; AVX2-NEXT: retq1079;1080; AVX512-LABEL: neg_scalar_broadcast_v16i8_v2i64:1081; AVX512: # %bb.0:1082; AVX512-NEXT: vpbroadcastb %edi, %xmm11083; AVX512-NEXT: vpandn %xmm0, %xmm1, %xmm01084; AVX512-NEXT: retq1085 %1 = xor i8 %a0, -11086 %2 = insertelement <16 x i8> undef, i8 %1, i64 01087 %3 = shufflevector <16 x i8> %2, <16 x i8> poison, <16 x i32> zeroinitializer1088 %4 = bitcast <16 x i8> %3 to <2 x i64>1089 %5 = and <2 x i64> %4, %a11090 ret <2 x i64> %51091}1092 1093define <4 x i64> @neg_scalar_broadcast_v8i32_v4i64(i32 %a0, <4 x i64> %a1) {1094; SSE-LABEL: neg_scalar_broadcast_v8i32_v4i64:1095; SSE: # %bb.0:1096; SSE-NEXT: notl %edi1097; SSE-NEXT: movd %edi, %xmm21098; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]1099; SSE-NEXT: pand %xmm2, %xmm01100; SSE-NEXT: pand %xmm2, %xmm11101; SSE-NEXT: retq1102;1103; AVX1-LABEL: neg_scalar_broadcast_v8i32_v4i64:1104; AVX1: # %bb.0:1105; AVX1-NEXT: vmovd %edi, %xmm11106; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]1107; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm11108; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm01109; AVX1-NEXT: retq1110;1111; AVX2-LABEL: neg_scalar_broadcast_v8i32_v4i64:1112; AVX2: # %bb.0:1113; AVX2-NEXT: vmovd %edi, %xmm11114; AVX2-NEXT: vpbroadcastd %xmm1, %ymm11115; AVX2-NEXT: vpandn %ymm0, %ymm1, %ymm01116; AVX2-NEXT: retq1117;1118; AVX512-LABEL: neg_scalar_broadcast_v8i32_v4i64:1119; AVX512: # %bb.0:1120; AVX512-NEXT: vpbroadcastd %edi, %ymm11121; AVX512-NEXT: vpandn %ymm0, %ymm1, %ymm01122; AVX512-NEXT: retq1123 %1 = xor i32 %a0, -11124 %2 = insertelement <8 x i32> undef, i32 %1, i64 01125 %3 = shufflevector <8 x i32> %2, <8 x i32> poison, <8 x i32> zeroinitializer1126 %4 = bitcast <8 x i32> %3 to <4 x i64>1127 %5 = and <4 x i64> %4, %a11128 ret <4 x i64> %51129}1130 1131define <4 x i32> @neg_scalar_broadcast_two_uses(i32 %a0, <4 x i32> %a1, ptr %a2) {1132; SSE-LABEL: neg_scalar_broadcast_two_uses:1133; SSE: # %bb.0:1134; SSE-NEXT: notl %edi1135; SSE-NEXT: movd %edi, %xmm11136; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]1137; SSE-NEXT: movdqa %xmm1, (%rsi)1138; SSE-NEXT: pand %xmm1, %xmm01139; SSE-NEXT: retq1140;1141; AVX1-LABEL: neg_scalar_broadcast_two_uses:1142; AVX1: # %bb.0:1143; AVX1-NEXT: notl %edi1144; AVX1-NEXT: vmovd %edi, %xmm11145; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]1146; AVX1-NEXT: vmovdqa %xmm1, (%rsi)1147; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm01148; AVX1-NEXT: retq1149;1150; AVX2-LABEL: neg_scalar_broadcast_two_uses:1151; AVX2: # %bb.0:1152; AVX2-NEXT: notl %edi1153; AVX2-NEXT: vmovd %edi, %xmm11154; AVX2-NEXT: vpbroadcastd %xmm1, %xmm11155; AVX2-NEXT: vmovdqa %xmm1, (%rsi)1156; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm01157; AVX2-NEXT: retq1158;1159; AVX512-LABEL: neg_scalar_broadcast_two_uses:1160; AVX512: # %bb.0:1161; AVX512-NEXT: notl %edi1162; AVX512-NEXT: vpbroadcastd %edi, %xmm11163; AVX512-NEXT: vmovdqa %xmm1, (%rsi)1164; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm01165; AVX512-NEXT: retq1166 %1 = xor i32 %a0, -11167 %2 = insertelement <4 x i32> undef, i32 %1, i64 01168 %3 = shufflevector <4 x i32> %2, <4 x i32> poison, <4 x i32> zeroinitializer1169 store <4 x i32> %3, ptr %a2, align 161170 %4 = and <4 x i32> %3, %a11171 ret <4 x i32> %41172}1173 1174; PR84660 - check for illegal types1175define <2 x i128> @neg_scalar_broadcast_illegaltype(i128 %arg) {1176; CHECK-LABEL: neg_scalar_broadcast_illegaltype:1177; CHECK: # %bb.0:1178; CHECK-NEXT: movq %rdi, %rax1179; CHECK-NEXT: notl %esi1180; CHECK-NEXT: andl $1, %esi1181; CHECK-NEXT: movq %rsi, 16(%rdi)1182; CHECK-NEXT: movq %rsi, (%rdi)1183; CHECK-NEXT: movq $0, 24(%rdi)1184; CHECK-NEXT: movq $0, 8(%rdi)1185; CHECK-NEXT: retq1186 %i = xor i128 %arg, 11187 %i1 = insertelement <2 x i128> zeroinitializer, i128 %i, i64 01188 %i2 = shufflevector <2 x i128> %i1, <2 x i128> zeroinitializer, <2 x i32> zeroinitializer1189 %i3 = and <2 x i128> <i128 1, i128 1>, %i21190 ret <2 x i128> %i31191}1192 1193define <2 x i64> @andnp_xx(<2 x i64> %v0) nounwind {1194; SSE-LABEL: andnp_xx:1195; SSE: # %bb.0:1196; SSE-NEXT: xorps %xmm0, %xmm01197; SSE-NEXT: retq1198;1199; AVX-LABEL: andnp_xx:1200; AVX: # %bb.0:1201; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm01202; AVX-NEXT: retq1203 %x = xor <2 x i64> %v0, <i64 -1, i64 -1>1204 %y = and <2 x i64> %v0, %x1205 ret <2 x i64> %y1206}1207 1208define <2 x i64> @andnp_xx_2(<2 x i64> %v0) nounwind {1209; SSE-LABEL: andnp_xx_2:1210; SSE: # %bb.0:1211; SSE-NEXT: xorps %xmm0, %xmm01212; SSE-NEXT: retq1213;1214; AVX-LABEL: andnp_xx_2:1215; AVX: # %bb.0:1216; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm01217; AVX-NEXT: retq1218 %x = xor <2 x i64> %v0, <i64 -1, i64 -1>1219 %y = and <2 x i64> %x, %v01220 ret <2 x i64> %y1221}1222 1223define i64 @andn_xx(i64 %v0) nounwind {1224; CHECK-LABEL: andn_xx:1225; CHECK: # %bb.0:1226; CHECK-NEXT: xorl %eax, %eax1227; CHECK-NEXT: retq1228 %x = xor i64 %v0, -11229 %y = and i64 %v0, %x1230 ret i64 %y1231}1232 1233define i64 @andn_xx_2(i64 %v0) nounwind {1234; CHECK-LABEL: andn_xx_2:1235; CHECK: # %bb.0:1236; CHECK-NEXT: xorl %eax, %eax1237; CHECK-NEXT: retq1238 %x = xor i64 %v0, -11239 %y = and i64 %x, %v01240 ret i64 %y1241}1242