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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1OR25; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR26; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX5127 8define <4 x double> @concat_sqrt_v4f64_v2f64(<2 x double> %a0, <2 x double> %a1) {9; SSE-LABEL: concat_sqrt_v4f64_v2f64:10; SSE: # %bb.0:11; SSE-NEXT: sqrtpd %xmm0, %xmm012; SSE-NEXT: sqrtpd %xmm1, %xmm113; SSE-NEXT: retq14;15; AVX-LABEL: concat_sqrt_v4f64_v2f64:16; AVX: # %bb.0:17; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm018; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm019; AVX-NEXT: vsqrtpd %ymm0, %ymm020; AVX-NEXT: retq21 %v0 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0)22 %v1 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a1)23 %res = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>24 ret <4 x double> %res25}26 27define <8 x float> @concat_sqrt_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {28; SSE-LABEL: concat_sqrt_v8f32_v4f32:29; SSE: # %bb.0:30; SSE-NEXT: sqrtps %xmm0, %xmm031; SSE-NEXT: sqrtps %xmm1, %xmm132; SSE-NEXT: retq33;34; AVX-LABEL: concat_sqrt_v8f32_v4f32:35; AVX: # %bb.0:36; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm037; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm038; AVX-NEXT: vsqrtps %ymm0, %ymm039; AVX-NEXT: retq40 %v0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a0)41 %v1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a1)42 %res = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>43 ret <8 x float> %res44}45 46define <8 x double> @concat_sqrt_v8f64_v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3) {47; SSE-LABEL: concat_sqrt_v8f64_v2f64:48; SSE: # %bb.0:49; SSE-NEXT: sqrtpd %xmm0, %xmm050; SSE-NEXT: sqrtpd %xmm1, %xmm151; SSE-NEXT: sqrtpd %xmm2, %xmm252; SSE-NEXT: sqrtpd %xmm3, %xmm353; SSE-NEXT: retq54;55; AVX1OR2-LABEL: concat_sqrt_v8f64_v2f64:56; AVX1OR2: # %bb.0:57; AVX1OR2-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm258; AVX1OR2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm059; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm060; AVX1OR2-NEXT: vsqrtpd %ymm0, %ymm061; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm162; AVX1OR2-NEXT: vsqrtpd %ymm1, %ymm163; AVX1OR2-NEXT: retq64;65; AVX512-LABEL: concat_sqrt_v8f64_v2f64:66; AVX512: # %bb.0:67; AVX512-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm268; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm069; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm270; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm071; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm072; AVX512-NEXT: vsqrtpd %zmm0, %zmm073; AVX512-NEXT: retq74 %v0 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0)75 %v1 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a1)76 %v2 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a2)77 %v3 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a3)78 %r01 = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>79 %r23 = shufflevector <2 x double> %v2, <2 x double> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>80 %res = shufflevector <4 x double> %r01, <4 x double> %r23, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>81 ret <8 x double> %res82}83 84define <16 x float> @concat_sqrt_v16f32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {85; SSE-LABEL: concat_sqrt_v16f32_v4f32:86; SSE: # %bb.0:87; SSE-NEXT: sqrtps %xmm0, %xmm088; SSE-NEXT: sqrtps %xmm1, %xmm189; SSE-NEXT: sqrtps %xmm2, %xmm290; SSE-NEXT: sqrtps %xmm3, %xmm391; SSE-NEXT: retq92;93; AVX1OR2-LABEL: concat_sqrt_v16f32_v4f32:94; AVX1OR2: # %bb.0:95; AVX1OR2-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm296; AVX1OR2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm097; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm098; AVX1OR2-NEXT: vsqrtps %ymm0, %ymm099; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1100; AVX1OR2-NEXT: vsqrtps %ymm1, %ymm1101; AVX1OR2-NEXT: retq102;103; AVX512-LABEL: concat_sqrt_v16f32_v4f32:104; AVX512: # %bb.0:105; AVX512-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm2106; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0107; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2108; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0109; AVX512-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0110; AVX512-NEXT: vsqrtps %zmm0, %zmm0111; AVX512-NEXT: retq112 %v0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a0)113 %v1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a1)114 %v2 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a2)115 %v3 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a3)116 %r01 = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>117 %r23 = shufflevector <4 x float> %v2, <4 x float> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>118 %res = shufflevector <8 x float> %r01, <8 x float> %r23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>119 ret <16 x float> %res120}121 122define <8 x double> @concat_sqrt_v8f64_v4f64(<4 x double> %a0, <4 x double> %a1) {123; SSE-LABEL: concat_sqrt_v8f64_v4f64:124; SSE: # %bb.0:125; SSE-NEXT: sqrtpd %xmm0, %xmm0126; SSE-NEXT: sqrtpd %xmm1, %xmm1127; SSE-NEXT: sqrtpd %xmm2, %xmm2128; SSE-NEXT: sqrtpd %xmm3, %xmm3129; SSE-NEXT: retq130;131; AVX1OR2-LABEL: concat_sqrt_v8f64_v4f64:132; AVX1OR2: # %bb.0:133; AVX1OR2-NEXT: vsqrtpd %ymm0, %ymm0134; AVX1OR2-NEXT: vsqrtpd %ymm1, %ymm1135; AVX1OR2-NEXT: retq136;137; AVX512-LABEL: concat_sqrt_v8f64_v4f64:138; AVX512: # %bb.0:139; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0140; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0141; AVX512-NEXT: vsqrtpd %zmm0, %zmm0142; AVX512-NEXT: retq143 %v0 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a0)144 %v1 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a1)145 %res = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>146 ret <8 x double> %res147}148 149define <16 x float> @concat_sqrt_v16f32_v8f32(<8 x float> %a0, <8 x float> %a1) {150; SSE-LABEL: concat_sqrt_v16f32_v8f32:151; SSE: # %bb.0:152; SSE-NEXT: sqrtps %xmm0, %xmm0153; SSE-NEXT: sqrtps %xmm1, %xmm1154; SSE-NEXT: sqrtps %xmm2, %xmm2155; SSE-NEXT: sqrtps %xmm3, %xmm3156; SSE-NEXT: retq157;158; AVX1OR2-LABEL: concat_sqrt_v16f32_v8f32:159; AVX1OR2: # %bb.0:160; AVX1OR2-NEXT: vsqrtps %ymm0, %ymm0161; AVX1OR2-NEXT: vsqrtps %ymm1, %ymm1162; AVX1OR2-NEXT: retq163;164; AVX512-LABEL: concat_sqrt_v16f32_v8f32:165; AVX512: # %bb.0:166; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0167; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0168; AVX512-NEXT: vsqrtps %zmm0, %zmm0169; AVX512-NEXT: retq170 %v0 = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %a0)171 %v1 = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %a1)172 %res = shufflevector <8 x float> %v0, <8 x float> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>173 ret <16 x float> %res174}175