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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX4 5declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone6declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone7 8declare {<4 x i32>, <4 x i1>} @llvm.smul.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone9declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone10 11; fold (smulo x, 2) -> (saddo x, x)12define i32 @combine_smul_two(i32 %a0, i32 %a1) {13; CHECK-LABEL: combine_smul_two:14; CHECK: # %bb.0:15; CHECK-NEXT: movl %edi, %eax16; CHECK-NEXT: addl %edi, %eax17; CHECK-NEXT: cmovol %esi, %eax18; CHECK-NEXT: retq19 %1 = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %a0, i32 2)20 %2 = extractvalue {i32, i1} %1, 021 %3 = extractvalue {i32, i1} %1, 122 %4 = select i1 %3, i32 %a1, i32 %223 ret i32 %424}25 26define <4 x i32> @combine_vec_smul_two(<4 x i32> %a0, <4 x i32> %a1) {27; SSE-LABEL: combine_vec_smul_two:28; SSE: # %bb.0:29; SSE-NEXT: movdqa %xmm0, %xmm230; SSE-NEXT: paddd %xmm0, %xmm231; SSE-NEXT: movdqa %xmm0, %xmm332; SSE-NEXT: pcmpgtd %xmm2, %xmm333; SSE-NEXT: pxor %xmm3, %xmm034; SSE-NEXT: blendvps %xmm0, %xmm1, %xmm235; SSE-NEXT: movaps %xmm2, %xmm036; SSE-NEXT: retq37;38; AVX-LABEL: combine_vec_smul_two:39; AVX: # %bb.0:40; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm241; AVX-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm342; AVX-NEXT: vpxor %xmm3, %xmm0, %xmm043; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm044; AVX-NEXT: retq45 %1 = call {<4 x i32>, <4 x i1>} @llvm.smul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)46 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 047 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 148 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %249 ret <4 x i32> %450}51 52; fold (umulo x, 2) -> (uaddo x, x)53define i32 @combine_umul_two(i32 %a0, i32 %a1) {54; CHECK-LABEL: combine_umul_two:55; CHECK: # %bb.0:56; CHECK-NEXT: movl %edi, %eax57; CHECK-NEXT: addl %edi, %eax58; CHECK-NEXT: cmovbl %esi, %eax59; CHECK-NEXT: retq60 %1 = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %a0, i32 2)61 %2 = extractvalue {i32, i1} %1, 062 %3 = extractvalue {i32, i1} %1, 163 %4 = select i1 %3, i32 %a1, i32 %264 ret i32 %465}66 67define <4 x i32> @combine_vec_umul_two(<4 x i32> %a0, <4 x i32> %a1) {68; SSE-LABEL: combine_vec_umul_two:69; SSE: # %bb.0:70; SSE-NEXT: movdqa %xmm0, %xmm271; SSE-NEXT: paddd %xmm0, %xmm272; SSE-NEXT: pmaxud %xmm2, %xmm073; SSE-NEXT: pcmpeqd %xmm2, %xmm074; SSE-NEXT: blendvps %xmm0, %xmm2, %xmm175; SSE-NEXT: movaps %xmm1, %xmm076; SSE-NEXT: retq77;78; AVX-LABEL: combine_vec_umul_two:79; AVX: # %bb.0:80; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm281; AVX-NEXT: vpmaxud %xmm0, %xmm2, %xmm082; AVX-NEXT: vpcmpeqd %xmm0, %xmm2, %xmm083; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm084; AVX-NEXT: retq85 %1 = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)86 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 087 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 188 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %289 ret <4 x i32> %490}91 92define { i32, i1 } @combine_smul_nsw(i32 %a, i32 %b) {93; CHECK-LABEL: combine_smul_nsw:94; CHECK: # %bb.0:95; CHECK-NEXT: movl %esi, %eax96; CHECK-NEXT: andl $4095, %edi # imm = 0xFFF97; CHECK-NEXT: andl $524287, %eax # imm = 0x7FFFF98; CHECK-NEXT: imull %edi, %eax99; CHECK-NEXT: xorl %edx, %edx100; CHECK-NEXT: retq101 %aa = and i32 %a, 4095 ; 0xfff102 %bb = and i32 %b, 524287; 0x7ffff103 %x = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %aa, i32 %bb)104 ret { i32, i1 } %x105}106 107define { <4 x i32>, <4 x i1> } @combine_vec_smul_nsw(<4 x i32> %a, <4 x i32> %b) {108; SSE-LABEL: combine_vec_smul_nsw:109; SSE: # %bb.0:110; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0111; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1112; SSE-NEXT: pmulld %xmm1, %xmm0113; SSE-NEXT: pxor %xmm1, %xmm1114; SSE-NEXT: retq115;116; AVX-LABEL: combine_vec_smul_nsw:117; AVX: # %bb.0:118; AVX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4095,4095,4095,4095]119; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0120; AVX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [524287,524287,524287,524287]121; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1122; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0123; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1124; AVX-NEXT: retq125 %aa = and <4 x i32> %a, <i32 4095, i32 4095, i32 4095, i32 4095>126 %bb = and <4 x i32> %b, <i32 524287, i32 524287, i32 524287, i32 524287>127 %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %aa, <4 x i32> %bb)128 ret { <4 x i32>, <4 x i1> } %x129}130