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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1OR25; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR26; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX5127 8define <8 x float> @concat_rcp_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {9; SSE-LABEL: concat_rcp_v8f32_v4f32:10; SSE: # %bb.0:11; SSE-NEXT: rcpps %xmm0, %xmm012; SSE-NEXT: rcpps %xmm1, %xmm113; SSE-NEXT: retq14;15; AVX-LABEL: concat_rcp_v8f32_v4f32:16; AVX: # %bb.0:17; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm018; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm019; AVX-NEXT: vrcpps %ymm0, %ymm020; AVX-NEXT: retq21 %v0 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0)22 %v1 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a1)23 %res = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>24 ret <8 x float> %res25}26 27; Ensure we don't convert rcpps to rcp14ps28define <16 x float> @concat_rcp_v16f32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {29; SSE-LABEL: concat_rcp_v16f32_v4f32:30; SSE: # %bb.0:31; SSE-NEXT: rcpps %xmm0, %xmm032; SSE-NEXT: rcpps %xmm1, %xmm133; SSE-NEXT: rcpps %xmm2, %xmm234; SSE-NEXT: rcpps %xmm3, %xmm335; SSE-NEXT: retq36;37; AVX1OR2-LABEL: concat_rcp_v16f32_v4f32:38; AVX1OR2: # %bb.0:39; AVX1OR2-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm240; AVX1OR2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm041; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm042; AVX1OR2-NEXT: vrcpps %ymm0, %ymm043; AVX1OR2-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm144; AVX1OR2-NEXT: vrcpps %ymm1, %ymm145; AVX1OR2-NEXT: retq46;47; AVX512-LABEL: concat_rcp_v16f32_v4f32:48; AVX512: # %bb.0:49; AVX512-NEXT: # kill: def $xmm2 killed $xmm2 def $ymm250; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm051; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm052; AVX512-NEXT: vrcpps %ymm0, %ymm053; AVX512-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm154; AVX512-NEXT: vrcpps %ymm1, %ymm155; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm056; AVX512-NEXT: retq57 %v0 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0)58 %v1 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a1)59 %v2 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a2)60 %v3 = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a3)61 %r01 = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>62 %r23 = shufflevector <4 x float> %v2, <4 x float> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>63 %res = shufflevector <8 x float> %r01, <8 x float> %r23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>64 ret <16 x float> %res65}66