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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX4 5; fold sextinreg(zext) -> sext6define <4 x i64> @sextinreg_zext_v16i8_4i64(<16 x i8> %a0) {7; SSE-LABEL: sextinreg_zext_v16i8_4i64:8; SSE: # %bb.0:9; SSE-NEXT: pmovsxbq %xmm0, %xmm210; SSE-NEXT: psrld $16, %xmm011; SSE-NEXT: pmovsxbq %xmm0, %xmm112; SSE-NEXT: movdqa %xmm2, %xmm013; SSE-NEXT: retq14;15; AVX-LABEL: sextinreg_zext_v16i8_4i64:16; AVX: # %bb.0:17; AVX-NEXT: vpmovsxbq %xmm0, %ymm018; AVX-NEXT: retq19 %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>20 %2 = zext <4 x i8> %1 to <4 x i64>21 %3 = shl <4 x i64> %2, <i64 56, i64 56, i64 56, i64 56>22 %4 = ashr <4 x i64> %3, <i64 56, i64 56, i64 56, i64 56>23 ret <4 x i64> %424}25 26; fold sextinreg(zext(sext)) -> sext27define <4 x i64> @sextinreg_zext_sext_v16i8_4i64(<16 x i8> %a0) {28; SSE-LABEL: sextinreg_zext_sext_v16i8_4i64:29; SSE: # %bb.0:30; SSE-NEXT: pmovsxbq %xmm0, %xmm231; SSE-NEXT: psrld $16, %xmm032; SSE-NEXT: pmovsxbq %xmm0, %xmm133; SSE-NEXT: movdqa %xmm2, %xmm034; SSE-NEXT: retq35;36; AVX-LABEL: sextinreg_zext_sext_v16i8_4i64:37; AVX: # %bb.0:38; AVX-NEXT: vpmovsxbq %xmm0, %ymm039; AVX-NEXT: retq40 %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>41 %2 = sext <4 x i8> %1 to <4 x i32>42 %3 = zext <4 x i32> %2 to <4 x i64>43 %4 = shl <4 x i64> %3, <i64 32, i64 32, i64 32, i64 32>44 %5 = ashr <4 x i64> %4, <i64 32, i64 32, i64 32, i64 32>45 ret <4 x i64> %546}47