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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2,AVX2-SLOW5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX2,AVX2-FAST-ALL6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX2,AVX2-FAST-PERLANE7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX5128 9; fold (shl 0, x) -> 010define <4 x i32> @combine_vec_shl_zero(<4 x i32> %x) {11; SSE-LABEL: combine_vec_shl_zero:12; SSE: # %bb.0:13; SSE-NEXT: xorps %xmm0, %xmm014; SSE-NEXT: retq15;16; AVX-LABEL: combine_vec_shl_zero:17; AVX: # %bb.0:18; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm019; AVX-NEXT: retq20 %1 = shl <4 x i32> zeroinitializer, %x21 ret <4 x i32> %122}23 24; fold (shl x, c >= size(x)) -> undef25define <4 x i32> @combine_vec_shl_outofrange0(<4 x i32> %x) {26; CHECK-LABEL: combine_vec_shl_outofrange0:27; CHECK: # %bb.0:28; CHECK-NEXT: retq29 %1 = shl <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>30 ret <4 x i32> %131}32 33define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) {34; CHECK-LABEL: combine_vec_shl_outofrange1:35; CHECK: # %bb.0:36; CHECK-NEXT: retq37 %1 = shl <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>38 ret <4 x i32> %139}40 41define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {42; CHECK-LABEL: combine_vec_shl_outofrange2:43; CHECK: # %bb.0:44; CHECK-NEXT: retq45 %1 = and <4 x i32> %a0, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>46 %2 = shl <4 x i32> %1, <i32 33, i32 33, i32 33, i32 33>47 ret <4 x i32> %248}49 50define <4 x i32> @combine_vec_shl_outofrange3(<4 x i32> %a0) {51; CHECK-LABEL: combine_vec_shl_outofrange3:52; CHECK: # %bb.0:53; CHECK-NEXT: retq54 %1 = shl <4 x i32> %a0, <i32 33, i32 34, i32 35, i32 undef>55 ret <4 x i32> %156}57 58; fold (shl x, 0) -> x59define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {60; CHECK-LABEL: combine_vec_shl_by_zero:61; CHECK: # %bb.0:62; CHECK-NEXT: retq63 %1 = shl <4 x i32> %x, zeroinitializer64 ret <4 x i32> %165}66 67; if (shl x, c) is known to be zero, return 068define <4 x i32> @combine_vec_shl_known_zero0(<4 x i32> %x) {69; SSE-LABEL: combine_vec_shl_known_zero0:70; SSE: # %bb.0:71; SSE-NEXT: xorps %xmm0, %xmm072; SSE-NEXT: retq73;74; AVX-LABEL: combine_vec_shl_known_zero0:75; AVX: # %bb.0:76; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm077; AVX-NEXT: retq78 %1 = and <4 x i32> %x, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>79 %2 = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>80 ret <4 x i32> %281}82 83define <4 x i32> @combine_vec_shl_known_zero1(<4 x i32> %x) {84; SSE2-LABEL: combine_vec_shl_known_zero1:85; SSE2: # %bb.0:86; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm087; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65536,32768,16384,8192]88; SSE2-NEXT: pmuludq %xmm0, %xmm189; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]90; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]91; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [32768,u,8192,u]92; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]93; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]94; SSE2-NEXT: movdqa %xmm1, %xmm095; SSE2-NEXT: retq96;97; SSE41-LABEL: combine_vec_shl_known_zero1:98; SSE41: # %bb.0:99; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0100; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [65536,32768,16384,8192]101; SSE41-NEXT: retq102;103; AVX-LABEL: combine_vec_shl_known_zero1:104; AVX: # %bb.0:105; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0106; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0107; AVX-NEXT: retq108 %1 = and <4 x i32> %x, <i32 4294901760, i32 8589803520, i32 17179607040, i32 34359214080>109 %2 = shl <4 x i32> %1, <i32 16, i32 15, i32 14, i32 13>110 ret <4 x i32> %2111}112 113; fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).114define <4 x i32> @combine_vec_shl_trunc_and(<4 x i32> %x, <4 x i64> %y) {115; SSE2-LABEL: combine_vec_shl_trunc_and:116; SSE2: # %bb.0:117; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]118; SSE2-NEXT: pslld $23, %xmm1119; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1120; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1121; SSE2-NEXT: cvttps2dq %xmm1, %xmm1122; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]123; SSE2-NEXT: pmuludq %xmm1, %xmm0124; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]125; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]126; SSE2-NEXT: pmuludq %xmm2, %xmm1127; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]128; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]129; SSE2-NEXT: retq130;131; SSE41-LABEL: combine_vec_shl_trunc_and:132; SSE41: # %bb.0:133; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]134; SSE41-NEXT: pslld $23, %xmm1135; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1136; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1137; SSE41-NEXT: cvttps2dq %xmm1, %xmm1138; SSE41-NEXT: pmulld %xmm1, %xmm0139; SSE41-NEXT: retq140;141; AVX2-SLOW-LABEL: combine_vec_shl_trunc_and:142; AVX2-SLOW: # %bb.0:143; AVX2-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2144; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]145; AVX2-SLOW-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1146; AVX2-SLOW-NEXT: vpsllvd %xmm1, %xmm0, %xmm0147; AVX2-SLOW-NEXT: vzeroupper148; AVX2-SLOW-NEXT: retq149;150; AVX2-FAST-ALL-LABEL: combine_vec_shl_trunc_and:151; AVX2-FAST-ALL: # %bb.0:152; AVX2-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,2,4,6,0,0,0,0]153; AVX2-FAST-ALL-NEXT: vpermd %ymm1, %ymm2, %ymm1154; AVX2-FAST-ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1155; AVX2-FAST-ALL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0156; AVX2-FAST-ALL-NEXT: vzeroupper157; AVX2-FAST-ALL-NEXT: retq158;159; AVX2-FAST-PERLANE-LABEL: combine_vec_shl_trunc_and:160; AVX2-FAST-PERLANE: # %bb.0:161; AVX2-FAST-PERLANE-NEXT: vextractf128 $1, %ymm1, %xmm2162; AVX2-FAST-PERLANE-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]163; AVX2-FAST-PERLANE-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1164; AVX2-FAST-PERLANE-NEXT: vpsllvd %xmm1, %xmm0, %xmm0165; AVX2-FAST-PERLANE-NEXT: vzeroupper166; AVX2-FAST-PERLANE-NEXT: retq167;168; AVX512-LABEL: combine_vec_shl_trunc_and:169; AVX512: # %bb.0:170; AVX512-NEXT: vpmovqd %ymm1, %xmm1171; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1172; AVX512-NEXT: vpsllvd %xmm1, %xmm0, %xmm0173; AVX512-NEXT: vzeroupper174; AVX512-NEXT: retq175 %1 = and <4 x i64> %y, <i64 15, i64 255, i64 4095, i64 65535>176 %2 = trunc <4 x i64> %1 to <4 x i32>177 %3 = shl <4 x i32> %x, %2178 ret <4 x i32> %3179}180 181; fold (shl (shl x, c1), c2) -> (shl x, (add c1, c2))182define <4 x i32> @combine_vec_shl_shl0(<4 x i32> %x) {183; SSE-LABEL: combine_vec_shl_shl0:184; SSE: # %bb.0:185; SSE-NEXT: pslld $6, %xmm0186; SSE-NEXT: retq187;188; AVX-LABEL: combine_vec_shl_shl0:189; AVX: # %bb.0:190; AVX-NEXT: vpslld $6, %xmm0, %xmm0191; AVX-NEXT: retq192 %1 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>193 %2 = shl <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>194 ret <4 x i32> %2195}196 197define <4 x i32> @combine_vec_shl_shl1(<4 x i32> %x) {198; SSE2-LABEL: combine_vec_shl_shl1:199; SSE2: # %bb.0:200; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]201; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16,64,256,1024]202; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]203; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [64,u,1024,u]204; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]205; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]206; SSE2-NEXT: retq207;208; SSE41-LABEL: combine_vec_shl_shl1:209; SSE41: # %bb.0:210; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16,64,256,1024]211; SSE41-NEXT: retq212;213; AVX-LABEL: combine_vec_shl_shl1:214; AVX: # %bb.0:215; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0216; AVX-NEXT: retq217 %1 = shl <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>218 %2 = shl <4 x i32> %1, <i32 4, i32 5, i32 6, i32 7>219 ret <4 x i32> %2220}221 222; fold (shl (shl x, c1), c2) -> 0223define <4 x i32> @combine_vec_shl_shlr_zero0(<4 x i32> %x) {224; SSE-LABEL: combine_vec_shl_shlr_zero0:225; SSE: # %bb.0:226; SSE-NEXT: xorps %xmm0, %xmm0227; SSE-NEXT: retq228;229; AVX-LABEL: combine_vec_shl_shlr_zero0:230; AVX: # %bb.0:231; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0232; AVX-NEXT: retq233 %1 = shl <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>234 %2 = shl <4 x i32> %1, <i32 20, i32 20, i32 20, i32 20>235 ret <4 x i32> %2236}237 238define <4 x i32> @combine_vec_shl_shl_zero1(<4 x i32> %x) {239; SSE-LABEL: combine_vec_shl_shl_zero1:240; SSE: # %bb.0:241; SSE-NEXT: xorps %xmm0, %xmm0242; SSE-NEXT: retq243;244; AVX-LABEL: combine_vec_shl_shl_zero1:245; AVX: # %bb.0:246; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0247; AVX-NEXT: retq248 %1 = shl <4 x i32> %x, <i32 17, i32 18, i32 19, i32 20>249 %2 = shl <4 x i32> %1, <i32 25, i32 26, i32 27, i32 28>250 ret <4 x i32> %2251}252 253; fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2))254define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) {255; SSE2-LABEL: combine_vec_shl_ext_shl0:256; SSE2: # %bb.0:257; SSE2-NEXT: movdqa %xmm0, %xmm1258; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]259; SSE2-NEXT: pslld $20, %xmm0260; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]261; SSE2-NEXT: pslld $20, %xmm1262; SSE2-NEXT: retq263;264; SSE41-LABEL: combine_vec_shl_ext_shl0:265; SSE41: # %bb.0:266; SSE41-NEXT: movdqa %xmm0, %xmm1267; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero268; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]269; SSE41-NEXT: pslld $20, %xmm1270; SSE41-NEXT: pslld $20, %xmm0271; SSE41-NEXT: retq272;273; AVX-LABEL: combine_vec_shl_ext_shl0:274; AVX: # %bb.0:275; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero276; AVX-NEXT: vpslld $20, %ymm0, %ymm0277; AVX-NEXT: retq278 %1 = shl <8 x i16> %x, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>279 %2 = sext <8 x i16> %1 to <8 x i32>280 %3 = shl <8 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>281 ret <8 x i32> %3282}283 284define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) {285; SSE-LABEL: combine_vec_shl_ext_shl1:286; SSE: # %bb.0:287; SSE-NEXT: xorps %xmm0, %xmm0288; SSE-NEXT: xorps %xmm1, %xmm1289; SSE-NEXT: retq290;291; AVX-LABEL: combine_vec_shl_ext_shl1:292; AVX: # %bb.0:293; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0294; AVX-NEXT: retq295 %1 = shl <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>296 %2 = sext <8 x i16> %1 to <8 x i32>297 %3 = shl <8 x i32> %2, <i32 31, i32 31, i32 30, i32 30, i32 29, i32 29, i32 28, i32 28>298 ret <8 x i32> %3299}300 301define <8 x i32> @combine_vec_shl_ext_shl2(<8 x i16> %x) {302; SSE2-LABEL: combine_vec_shl_ext_shl2:303; SSE2: # %bb.0:304; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]305; SSE2-NEXT: psrad $16, %xmm1306; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]307; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [131072,524288,2097152,8388608]308; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3]309; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [524288,u,8388608,u]310; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]311; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]312; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]313; SSE2-NEXT: psrad $16, %xmm0314; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]315; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [33554432,134217728,536870912,2147483648]316; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,2,2,3]317; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [134217728,u,2147483648,u]318; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]319; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]320; SSE2-NEXT: movdqa %xmm2, %xmm0321; SSE2-NEXT: retq322;323; SSE41-LABEL: combine_vec_shl_ext_shl2:324; SSE41: # %bb.0:325; SSE41-NEXT: pmovsxwd %xmm0, %xmm2326; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [131072,524288,2097152,8388608]327; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]328; SSE41-NEXT: pmovsxwd %xmm0, %xmm1329; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [33554432,134217728,536870912,2147483648]330; SSE41-NEXT: movdqa %xmm2, %xmm0331; SSE41-NEXT: retq332;333; AVX-LABEL: combine_vec_shl_ext_shl2:334; AVX: # %bb.0:335; AVX-NEXT: vpmovsxwd %xmm0, %ymm0336; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0337; AVX-NEXT: retq338 %1 = shl <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>339 %2 = sext <8 x i16> %1 to <8 x i32>340 %3 = shl <8 x i32> %2, <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>341 ret <8 x i32> %3342}343 344; fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))345define <8 x i32> @combine_vec_shl_zext_lshr0(<8 x i16> %x) {346; SSE2-LABEL: combine_vec_shl_zext_lshr0:347; SSE2: # %bb.0:348; SSE2-NEXT: movdqa %xmm0, %xmm1349; SSE2-NEXT: pxor %xmm2, %xmm2350; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1351; SSE2-NEXT: movdqa %xmm1, %xmm0352; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]353; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]354; SSE2-NEXT: retq355;356; SSE41-LABEL: combine_vec_shl_zext_lshr0:357; SSE41: # %bb.0:358; SSE41-NEXT: movdqa %xmm0, %xmm1359; SSE41-NEXT: pxor %xmm2, %xmm2360; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1361; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero362; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]363; SSE41-NEXT: retq364;365; AVX2-LABEL: combine_vec_shl_zext_lshr0:366; AVX2: # %bb.0:367; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0368; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero369; AVX2-NEXT: retq370;371; AVX512-LABEL: combine_vec_shl_zext_lshr0:372; AVX512: # %bb.0:373; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0374; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero375; AVX512-NEXT: retq376 %1 = lshr <8 x i16> %x, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>377 %2 = zext <8 x i16> %1 to <8 x i32>378 %3 = shl <8 x i32> %2, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>379 ret <8 x i32> %3380}381 382define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) {383; SSE2-LABEL: combine_vec_shl_zext_lshr1:384; SSE2: # %bb.0:385; SSE2-NEXT: movdqa %xmm0, %xmm1386; SSE2-NEXT: pxor %xmm2, %xmm2387; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1388; SSE2-NEXT: movdqa %xmm1, %xmm0389; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]390; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]391; SSE2-NEXT: retq392;393; SSE41-LABEL: combine_vec_shl_zext_lshr1:394; SSE41: # %bb.0:395; SSE41-NEXT: movdqa %xmm0, %xmm1396; SSE41-NEXT: pxor %xmm2, %xmm2397; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1398; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero399; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]400; SSE41-NEXT: retq401;402; AVX-LABEL: combine_vec_shl_zext_lshr1:403; AVX: # %bb.0:404; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0405; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero406; AVX-NEXT: retq407 %1 = lshr <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 15>408 %2 = zext <8 x i16> %1 to <8 x i32>409 %3 = shl <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 15>410 ret <8 x i32> %3411}412 413; fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2414define <4 x i32> @combine_vec_shl_ge_ashr_exact0(<4 x i32> %x) {415; SSE-LABEL: combine_vec_shl_ge_ashr_exact0:416; SSE: # %bb.0:417; SSE-NEXT: pslld $2, %xmm0418; SSE-NEXT: retq419;420; AVX-LABEL: combine_vec_shl_ge_ashr_exact0:421; AVX: # %bb.0:422; AVX-NEXT: vpslld $2, %xmm0, %xmm0423; AVX-NEXT: retq424 %1 = ashr exact <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>425 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>426 ret <4 x i32> %2427}428 429define <4 x i32> @combine_vec_shl_ge_ashr_exact1(<4 x i32> %x) {430; SSE2-LABEL: combine_vec_shl_ge_ashr_exact1:431; SSE2: # %bb.0:432; SSE2-NEXT: movdqa %xmm0, %xmm1433; SSE2-NEXT: pslld $2, %xmm1434; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]435; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]436; SSE2-NEXT: movaps %xmm1, %xmm0437; SSE2-NEXT: retq438;439; SSE41-LABEL: combine_vec_shl_ge_ashr_exact1:440; SSE41: # %bb.0:441; SSE41-NEXT: movdqa %xmm0, %xmm1442; SSE41-NEXT: pslld $2, %xmm1443; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]444; SSE41-NEXT: retq445;446; AVX-LABEL: combine_vec_shl_ge_ashr_exact1:447; AVX: # %bb.0:448; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0449; AVX-NEXT: retq450 %1 = ashr exact <4 x i32> %x, <i32 3, i32 4, i32 5, i32 8>451 %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>452 ret <4 x i32> %2453}454 455; fold (shl (sr[la] exact SEL(X,Y), C1), C2) -> (shl SEL(X,Y), (C2-C1)) if C1 <= C2456define i32 @combine_shl_ge_sel_ashr_exact0(i32 %x, i32 %y, i32 %z) {457; CHECK-LABEL: combine_shl_ge_sel_ashr_exact0:458; CHECK: # %bb.0:459; CHECK-NEXT: # kill: def $edi killed $edi def $rdi460; CHECK-NEXT: testl %edx, %edx461; CHECK-NEXT: cmovel %esi, %edi462; CHECK-NEXT: leal (,%rdi,4), %eax463; CHECK-NEXT: retq464 %cmp = icmp ne i32 %z, 0465 %ashrx = ashr exact i32 %x, 3466 %ashry = ashr exact i32 %y, 3467 %sel = select i1 %cmp, i32 %ashrx, i32 %ashry468 %shl = shl i32 %sel, 5469 ret i32 %shl470}471 472; fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2473define <4 x i32> @combine_vec_shl_lt_ashr_exact0(<4 x i32> %x) {474; SSE-LABEL: combine_vec_shl_lt_ashr_exact0:475; SSE: # %bb.0:476; SSE-NEXT: psrad $2, %xmm0477; SSE-NEXT: retq478;479; AVX-LABEL: combine_vec_shl_lt_ashr_exact0:480; AVX: # %bb.0:481; AVX-NEXT: vpsrad $2, %xmm0, %xmm0482; AVX-NEXT: retq483 %1 = ashr exact <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>484 %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>485 ret <4 x i32> %2486}487 488define <4 x i32> @combine_vec_shl_lt_ashr_exact1(<4 x i32> %x) {489; SSE2-LABEL: combine_vec_shl_lt_ashr_exact1:490; SSE2: # %bb.0:491; SSE2-NEXT: movdqa %xmm0, %xmm1492; SSE2-NEXT: psrad $2, %xmm1493; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]494; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]495; SSE2-NEXT: movaps %xmm1, %xmm0496; SSE2-NEXT: retq497;498; SSE41-LABEL: combine_vec_shl_lt_ashr_exact1:499; SSE41: # %bb.0:500; SSE41-NEXT: movdqa %xmm0, %xmm1501; SSE41-NEXT: psrad $2, %xmm1502; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]503; SSE41-NEXT: retq504;505; AVX-LABEL: combine_vec_shl_lt_ashr_exact1:506; AVX: # %bb.0:507; AVX-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0508; AVX-NEXT: retq509 %1 = ashr exact <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>510 %2 = shl <4 x i32> %1, <i32 3, i32 4, i32 5, i32 8>511 ret <4 x i32> %2512}513 514; fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) if C2 > C1515define <4 x i32> @combine_vec_shl_gt_lshr0(<4 x i32> %x) {516; SSE-LABEL: combine_vec_shl_gt_lshr0:517; SSE: # %bb.0:518; SSE-NEXT: pslld $2, %xmm0519; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0520; SSE-NEXT: retq521;522; AVX2-LABEL: combine_vec_shl_gt_lshr0:523; AVX2: # %bb.0:524; AVX2-NEXT: vpslld $2, %xmm0, %xmm0525; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967264,4294967264,4294967264,4294967264]526; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0527; AVX2-NEXT: retq528;529; AVX512-LABEL: combine_vec_shl_gt_lshr0:530; AVX512: # %bb.0:531; AVX512-NEXT: vpslld $2, %xmm0, %xmm0532; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0533; AVX512-NEXT: retq534 %1 = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>535 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>536 ret <4 x i32> %2537}538 539define <4 x i32> @combine_vec_shl_gt_lshr1(<4 x i32> %x) {540; SSE-LABEL: combine_vec_shl_gt_lshr1:541; SSE: # %bb.0:542; SSE-NEXT: pslld $2, %xmm0543; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0544; SSE-NEXT: retq545;546; AVX-LABEL: combine_vec_shl_gt_lshr1:547; AVX: # %bb.0:548; AVX-NEXT: vpslld $2, %xmm0, %xmm0549; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0550; AVX-NEXT: retq551 %1 = lshr <4 x i32> %x, <i32 3, i32 4, i32 5, i32 29>552 %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 31>553 ret <4 x i32> %2554}555 556; fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 >= C2557define <4 x i32> @combine_vec_shl_le_lshr0(<4 x i32> %x) {558; SSE-LABEL: combine_vec_shl_le_lshr0:559; SSE: # %bb.0:560; SSE-NEXT: psrld $2, %xmm0561; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0562; SSE-NEXT: retq563;564; AVX2-LABEL: combine_vec_shl_le_lshr0:565; AVX2: # %bb.0:566; AVX2-NEXT: vpsrld $2, %xmm0, %xmm0567; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1073741816,1073741816,1073741816,1073741816]568; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0569; AVX2-NEXT: retq570;571; AVX512-LABEL: combine_vec_shl_le_lshr0:572; AVX512: # %bb.0:573; AVX512-NEXT: vpsrld $2, %xmm0, %xmm0574; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0575; AVX512-NEXT: retq576 %1 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>577 %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>578 ret <4 x i32> %2579}580 581define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) {582; SSE2-LABEL: combine_vec_shl_le_lshr1:583; SSE2: # %bb.0:584; SSE2-NEXT: movdqa %xmm0, %xmm1585; SSE2-NEXT: psrld $2, %xmm1586; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]587; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]588; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1589; SSE2-NEXT: movaps %xmm1, %xmm0590; SSE2-NEXT: retq591;592; SSE41-LABEL: combine_vec_shl_le_lshr1:593; SSE41: # %bb.0:594; SSE41-NEXT: movdqa %xmm0, %xmm1595; SSE41-NEXT: psrld $2, %xmm1596; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]597; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0598; SSE41-NEXT: retq599;600; AVX-LABEL: combine_vec_shl_le_lshr1:601; AVX: # %bb.0:602; AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0603; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0604; AVX-NEXT: retq605 %1 = lshr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>606 %2 = shl <4 x i32> %1, <i32 3, i32 4, i32 5, i32 8>607 ret <4 x i32> %2608}609 610; fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))611define <4 x i32> @combine_vec_shl_ashr0(<4 x i32> %x) {612; SSE-LABEL: combine_vec_shl_ashr0:613; SSE: # %bb.0:614; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0615; SSE-NEXT: retq616;617; AVX2-LABEL: combine_vec_shl_ashr0:618; AVX2: # %bb.0:619; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [4294967264,4294967264,4294967264,4294967264]620; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0621; AVX2-NEXT: retq622;623; AVX512-LABEL: combine_vec_shl_ashr0:624; AVX512: # %bb.0:625; AVX512-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0626; AVX512-NEXT: retq627 %1 = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>628 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>629 ret <4 x i32> %2630}631 632define <4 x i32> @combine_vec_shl_ashr1(<4 x i32> %x) {633; SSE-LABEL: combine_vec_shl_ashr1:634; SSE: # %bb.0:635; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0636; SSE-NEXT: retq637;638; AVX-LABEL: combine_vec_shl_ashr1:639; AVX: # %bb.0:640; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0641; AVX-NEXT: retq642 %1 = ashr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>643 %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>644 ret <4 x i32> %2645}646 647; fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)648define <4 x i32> @combine_vec_shl_add0(<4 x i32> %x) {649; SSE-LABEL: combine_vec_shl_add0:650; SSE: # %bb.0:651; SSE-NEXT: pslld $2, %xmm0652; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0653; SSE-NEXT: retq654;655; AVX2-LABEL: combine_vec_shl_add0:656; AVX2: # %bb.0:657; AVX2-NEXT: vpslld $2, %xmm0, %xmm0658; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [20,20,20,20]659; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0660; AVX2-NEXT: retq661;662; AVX512-LABEL: combine_vec_shl_add0:663; AVX512: # %bb.0:664; AVX512-NEXT: vpslld $2, %xmm0, %xmm0665; AVX512-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0666; AVX512-NEXT: retq667 %1 = add <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>668 %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>669 ret <4 x i32> %2670}671 672define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) {673; SSE2-LABEL: combine_vec_shl_add1:674; SSE2: # %bb.0:675; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]676; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]677; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]678; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [4,u,16,u]679; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]680; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]681; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0682; SSE2-NEXT: retq683;684; SSE41-LABEL: combine_vec_shl_add1:685; SSE41: # %bb.0:686; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]687; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0688; SSE41-NEXT: retq689;690; AVX-LABEL: combine_vec_shl_add1:691; AVX: # %bb.0:692; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0693; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0694; AVX-NEXT: retq695 %1 = add <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>696 %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>697 ret <4 x i32> %2698}699 700; fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)701define <4 x i32> @combine_vec_shl_or0(<4 x i32> %x) {702; SSE-LABEL: combine_vec_shl_or0:703; SSE: # %bb.0:704; SSE-NEXT: pslld $2, %xmm0705; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0706; SSE-NEXT: retq707;708; AVX2-LABEL: combine_vec_shl_or0:709; AVX2: # %bb.0:710; AVX2-NEXT: vpslld $2, %xmm0, %xmm0711; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [20,20,20,20]712; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0713; AVX2-NEXT: retq714;715; AVX512-LABEL: combine_vec_shl_or0:716; AVX512: # %bb.0:717; AVX512-NEXT: vpslld $2, %xmm0, %xmm0718; AVX512-NEXT: vpord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0719; AVX512-NEXT: retq720 %1 = or <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>721 %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>722 ret <4 x i32> %2723}724 725define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) {726; SSE2-LABEL: combine_vec_shl_or1:727; SSE2: # %bb.0:728; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]729; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]730; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]731; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [4,u,16,u]732; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]733; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]734; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0735; SSE2-NEXT: retq736;737; SSE41-LABEL: combine_vec_shl_or1:738; SSE41: # %bb.0:739; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]740; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0741; SSE41-NEXT: retq742;743; AVX-LABEL: combine_vec_shl_or1:744; AVX: # %bb.0:745; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0746; AVX-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0747; AVX-NEXT: retq748 %1 = or <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>749 %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>750 ret <4 x i32> %2751}752 753; fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)754define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) {755; SSE2-LABEL: combine_vec_shl_mul0:756; SSE2: # %bb.0:757; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [20,20,20,20]758; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]759; SSE2-NEXT: pmuludq %xmm1, %xmm0760; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]761; SSE2-NEXT: pmuludq %xmm1, %xmm2762; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]763; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]764; SSE2-NEXT: retq765;766; SSE41-LABEL: combine_vec_shl_mul0:767; SSE41: # %bb.0:768; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [20,20,20,20]769; SSE41-NEXT: retq770;771; AVX2-LABEL: combine_vec_shl_mul0:772; AVX2: # %bb.0:773; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [20,20,20,20]774; AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0775; AVX2-NEXT: retq776;777; AVX512-LABEL: combine_vec_shl_mul0:778; AVX512: # %bb.0:779; AVX512-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0780; AVX512-NEXT: retq781 %1 = mul <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>782 %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>783 ret <4 x i32> %2784}785 786define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) {787; SSE2-LABEL: combine_vec_shl_mul1:788; SSE2: # %bb.0:789; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]790; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [10,24,56,128]791; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]792; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [24,u,128,u]793; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]794; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]795; SSE2-NEXT: retq796;797; SSE41-LABEL: combine_vec_shl_mul1:798; SSE41: # %bb.0:799; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [10,24,56,128]800; SSE41-NEXT: retq801;802; AVX-LABEL: combine_vec_shl_mul1:803; AVX: # %bb.0:804; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [10,24,56,128]805; AVX-NEXT: retq806 %1 = mul <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>807 %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>808 ret <4 x i32> %2809}810 811; fold (add (shl x, c1), c2) -> (or (shl x, c1), c2)812define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) {813; SSE2-LABEL: combine_vec_add_shl_nonsplat:814; SSE2: # %bb.0:815; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]816; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4,8,16,32]817; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]818; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [8,u,32,u]819; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]820; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]821; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0822; SSE2-NEXT: retq823;824; SSE41-LABEL: combine_vec_add_shl_nonsplat:825; SSE41: # %bb.0:826; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4,8,16,32]827; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0828; SSE41-NEXT: retq829;830; AVX2-LABEL: combine_vec_add_shl_nonsplat:831; AVX2: # %bb.0:832; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0833; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3]834; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0835; AVX2-NEXT: retq836;837; AVX512-LABEL: combine_vec_add_shl_nonsplat:838; AVX512: # %bb.0:839; AVX512-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0840; AVX512-NEXT: vpord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0841; AVX512-NEXT: retq842 %1 = shl <4 x i32> %a0, <i32 2, i32 3, i32 4, i32 5>843 %2 = add <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>844 ret <4 x i32> %2845}846 847define <4 x i32> @combine_vec_add_shl_and_nonsplat(<4 x i32> %a0) {848; SSE2-LABEL: combine_vec_add_shl_and_nonsplat:849; SSE2: # %bb.0:850; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0851; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4,8,16,32]852; SSE2-NEXT: pmuludq %xmm0, %xmm1853; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]854; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]855; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [8,u,32,u]856; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]857; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]858; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1859; SSE2-NEXT: movdqa %xmm1, %xmm0860; SSE2-NEXT: retq861;862; SSE41-LABEL: combine_vec_add_shl_and_nonsplat:863; SSE41: # %bb.0:864; SSE41-NEXT: pxor %xmm1, %xmm1865; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]866; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4,8,16,32]867; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0868; SSE41-NEXT: retq869;870; AVX2-LABEL: combine_vec_add_shl_and_nonsplat:871; AVX2: # %bb.0:872; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1873; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]874; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0875; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [15,15,15,15]876; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0877; AVX2-NEXT: retq878;879; AVX512-LABEL: combine_vec_add_shl_and_nonsplat:880; AVX512: # %bb.0:881; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1882; AVX512-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]883; AVX512-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0884; AVX512-NEXT: vpord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0885; AVX512-NEXT: retq886 %1 = and <4 x i32> %a0, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>887 %2 = shl <4 x i32> %1, <i32 2, i32 3, i32 4, i32 5>888 %3 = add <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>889 ret <4 x i32> %3890}891 892define <4 x i32> @combine_vec_add_shuffle_shl(<4 x i32> %a0) {893; SSE2-LABEL: combine_vec_add_shuffle_shl:894; SSE2: # %bb.0:895; SSE2-NEXT: movdqa %xmm0, %xmm1896; SSE2-NEXT: pslld $3, %xmm1897; SSE2-NEXT: pslld $2, %xmm0898; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]899; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,3,0]900; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0901; SSE2-NEXT: retq902;903; SSE41-LABEL: combine_vec_add_shuffle_shl:904; SSE41: # %bb.0:905; SSE41-NEXT: movdqa %xmm0, %xmm1906; SSE41-NEXT: pslld $3, %xmm1907; SSE41-NEXT: pslld $2, %xmm0908; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]909; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]910; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0911; SSE41-NEXT: retq912;913; AVX2-LABEL: combine_vec_add_shuffle_shl:914; AVX2: # %bb.0:915; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]916; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0917; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3]918; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0919; AVX2-NEXT: retq920;921; AVX512-LABEL: combine_vec_add_shuffle_shl:922; AVX512: # %bb.0:923; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]924; AVX512-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0925; AVX512-NEXT: vpord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0926; AVX512-NEXT: retq927 %1 = shl <4 x i32> %a0, <i32 2, i32 3, i32 0, i32 1>928 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>929 %3 = add <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>930 ret <4 x i32> %3931}932 933define <4 x i32> @combine_vec_shl_clamped1(<4 x i32> %sh, <4 x i32> %amt) {934; SSE2-LABEL: combine_vec_shl_clamped1:935; SSE2: # %bb.0:936; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]937; SSE2-NEXT: pxor %xmm1, %xmm2938; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2939; SSE2-NEXT: pslld $23, %xmm1940; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1941; SSE2-NEXT: cvttps2dq %xmm1, %xmm1942; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]943; SSE2-NEXT: pmuludq %xmm1, %xmm0944; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]945; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]946; SSE2-NEXT: pmuludq %xmm3, %xmm1947; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]948; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]949; SSE2-NEXT: pandn %xmm0, %xmm2950; SSE2-NEXT: movdqa %xmm2, %xmm0951; SSE2-NEXT: retq952;953; SSE41-LABEL: combine_vec_shl_clamped1:954; SSE41: # %bb.0:955; SSE41-NEXT: pmovsxbd {{.*#+}} xmm2 = [31,31,31,31]956; SSE41-NEXT: pminud %xmm1, %xmm2957; SSE41-NEXT: pcmpeqd %xmm1, %xmm2958; SSE41-NEXT: pslld $23, %xmm1959; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1960; SSE41-NEXT: cvttps2dq %xmm1, %xmm1961; SSE41-NEXT: pmulld %xmm1, %xmm0962; SSE41-NEXT: pand %xmm2, %xmm0963; SSE41-NEXT: retq964;965; AVX-LABEL: combine_vec_shl_clamped1:966; AVX: # %bb.0:967; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0968; AVX-NEXT: retq969 %cmp.i = icmp ult <4 x i32> %amt, <i32 32, i32 32, i32 32, i32 32>970 %shl = shl <4 x i32> %sh, %amt971 %1 = select <4 x i1> %cmp.i, <4 x i32> %shl, <4 x i32> zeroinitializer972 ret <4 x i32> %1973}974 975define <4 x i32> @combine_vec_shl_clamped2(<4 x i32> %sh, <4 x i32> %amt) {976; SSE2-LABEL: combine_vec_shl_clamped2:977; SSE2: # %bb.0:978; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]979; SSE2-NEXT: pxor %xmm1, %xmm2980; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2981; SSE2-NEXT: pandn %xmm0, %xmm2982; SSE2-NEXT: pslld $23, %xmm1983; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1984; SSE2-NEXT: cvttps2dq %xmm1, %xmm1985; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]986; SSE2-NEXT: pmuludq %xmm1, %xmm2987; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]988; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]989; SSE2-NEXT: pmuludq %xmm3, %xmm1990; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]991; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]992; SSE2-NEXT: retq993;994; SSE41-LABEL: combine_vec_shl_clamped2:995; SSE41: # %bb.0:996; SSE41-NEXT: pmovsxbd {{.*#+}} xmm2 = [31,31,31,31]997; SSE41-NEXT: pminud %xmm1, %xmm2998; SSE41-NEXT: pcmpeqd %xmm1, %xmm2999; SSE41-NEXT: pand %xmm2, %xmm01000; SSE41-NEXT: pslld $23, %xmm11001; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm11002; SSE41-NEXT: cvttps2dq %xmm1, %xmm11003; SSE41-NEXT: pmulld %xmm1, %xmm01004; SSE41-NEXT: retq1005;1006; AVX-LABEL: combine_vec_shl_clamped2:1007; AVX: # %bb.0:1008; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm01009; AVX-NEXT: retq1010 %cmp.i = icmp ult <4 x i32> %amt, <i32 32, i32 32, i32 32, i32 32>1011 %1 = select <4 x i1> %cmp.i, <4 x i32> %sh, <4 x i32> zeroinitializer1012 %shl = shl <4 x i32> %1, %amt1013 ret <4 x i32> %shl1014}1015 1016define <4 x i32> @combine_vec_shl_commuted_clamped(<4 x i32> %sh, <4 x i32> %amt) {1017; SSE2-LABEL: combine_vec_shl_commuted_clamped:1018; SSE2: # %bb.0:1019; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]1020; SSE2-NEXT: pxor %xmm1, %xmm21021; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm21022; SSE2-NEXT: pandn %xmm0, %xmm21023; SSE2-NEXT: pslld $23, %xmm11024; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm11025; SSE2-NEXT: cvttps2dq %xmm1, %xmm11026; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]1027; SSE2-NEXT: pmuludq %xmm1, %xmm21028; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]1029; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]1030; SSE2-NEXT: pmuludq %xmm3, %xmm11031; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]1032; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1033; SSE2-NEXT: retq1034;1035; SSE41-LABEL: combine_vec_shl_commuted_clamped:1036; SSE41: # %bb.0:1037; SSE41-NEXT: pmovsxbd {{.*#+}} xmm2 = [31,31,31,31]1038; SSE41-NEXT: pminud %xmm1, %xmm21039; SSE41-NEXT: pcmpeqd %xmm1, %xmm21040; SSE41-NEXT: pand %xmm2, %xmm01041; SSE41-NEXT: pslld $23, %xmm11042; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm11043; SSE41-NEXT: cvttps2dq %xmm1, %xmm11044; SSE41-NEXT: pmulld %xmm1, %xmm01045; SSE41-NEXT: retq1046;1047; AVX-LABEL: combine_vec_shl_commuted_clamped:1048; AVX: # %bb.0:1049; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm01050; AVX-NEXT: retq1051 %cmp.i = icmp uge <4 x i32> %amt, <i32 32, i32 32, i32 32, i32 32>1052 %1 = select <4 x i1> %cmp.i, <4 x i32> zeroinitializer, <4 x i32> %sh1053 %shl = shl <4 x i32> %1, %amt1054 ret <4 x i32> %shl1055}1056 1057define <4 x i32> @combine_vec_shl_commuted_clamped1(<4 x i32> %sh, <4 x i32> %amt) {1058; SSE2-LABEL: combine_vec_shl_commuted_clamped1:1059; SSE2: # %bb.0:1060; SSE2-NEXT: movdqa %xmm1, %xmm21061; SSE2-NEXT: pslld $23, %xmm21062; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm21063; SSE2-NEXT: cvttps2dq %xmm2, %xmm21064; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]1065; SSE2-NEXT: pmuludq %xmm2, %xmm01066; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]1067; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]1068; SSE2-NEXT: pmuludq %xmm3, %xmm21069; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]1070; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]1071; SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm11072; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm11073; SSE2-NEXT: pandn %xmm0, %xmm11074; SSE2-NEXT: movdqa %xmm1, %xmm01075; SSE2-NEXT: retq1076;1077; SSE41-LABEL: combine_vec_shl_commuted_clamped1:1078; SSE41: # %bb.0:1079; SSE41-NEXT: pmovsxbd {{.*#+}} xmm2 = [31,31,31,31]1080; SSE41-NEXT: pminud %xmm1, %xmm21081; SSE41-NEXT: pcmpeqd %xmm1, %xmm21082; SSE41-NEXT: pslld $23, %xmm11083; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm11084; SSE41-NEXT: cvttps2dq %xmm1, %xmm11085; SSE41-NEXT: pmulld %xmm1, %xmm01086; SSE41-NEXT: pand %xmm2, %xmm01087; SSE41-NEXT: retq1088;1089; AVX-LABEL: combine_vec_shl_commuted_clamped1:1090; AVX: # %bb.0:1091; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm01092; AVX-NEXT: retq1093 %cmp.i = icmp uge <4 x i32> %amt, <i32 32, i32 32, i32 32, i32 32>1094 %shl = shl <4 x i32> %sh, %amt1095 %1 = select <4 x i1> %cmp.i, <4 x i32> zeroinitializer, <4 x i32> %shl1096 ret <4 x i32> %11097}1098