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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX4 5; fold (sub x, 0) -> x6define <4 x i32> @combine_vec_sub_zero(<4 x i32> %a) {7; CHECK-LABEL: combine_vec_sub_zero:8; CHECK: # %bb.0:9; CHECK-NEXT: retq10 %1 = sub <4 x i32> %a, zeroinitializer11 ret <4 x i32> %112}13 14; fold (sub x, x) -> 015define <4 x i32> @combine_vec_sub_self(<4 x i32> %a) {16; SSE-LABEL: combine_vec_sub_self:17; SSE: # %bb.0:18; SSE-NEXT: xorps %xmm0, %xmm019; SSE-NEXT: retq20;21; AVX-LABEL: combine_vec_sub_self:22; AVX: # %bb.0:23; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm024; AVX-NEXT: retq25 %1 = sub <4 x i32> %a, %a26 ret <4 x i32> %127}28 29; fold (sub x, c) -> (add x, -c)30define <4 x i32> @combine_vec_sub_constant(<4 x i32> %x) {31; SSE-LABEL: combine_vec_sub_constant:32; SSE: # %bb.0:33; SSE-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm034; SSE-NEXT: retq35;36; AVX-LABEL: combine_vec_sub_constant:37; AVX: # %bb.0:38; AVX-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm039; AVX-NEXT: retq40 %1 = sub <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>41 ret <4 x i32> %142}43 44; Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)45define <4 x i32> @combine_vec_sub_negone(<4 x i32> %x) {46; SSE-LABEL: combine_vec_sub_negone:47; SSE: # %bb.0:48; SSE-NEXT: pcmpeqd %xmm1, %xmm149; SSE-NEXT: pxor %xmm1, %xmm050; SSE-NEXT: retq51;52; AVX-LABEL: combine_vec_sub_negone:53; AVX: # %bb.0:54; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm155; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm056; AVX-NEXT: retq57 %1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x58 ret <4 x i32> %159}60 61; fold A-(A-B) -> B62define <4 x i32> @combine_vec_sub_sub(<4 x i32> %a, <4 x i32> %b) {63; SSE-LABEL: combine_vec_sub_sub:64; SSE: # %bb.0:65; SSE-NEXT: movaps %xmm1, %xmm066; SSE-NEXT: retq67;68; AVX-LABEL: combine_vec_sub_sub:69; AVX: # %bb.0:70; AVX-NEXT: vmovaps %xmm1, %xmm071; AVX-NEXT: retq72 %1 = sub <4 x i32> %a, %b73 %2 = sub <4 x i32> %a, %174 ret <4 x i32> %275}76 77; fold (A+B)-A -> B78define <4 x i32> @combine_vec_sub_add0(<4 x i32> %a, <4 x i32> %b) {79; SSE-LABEL: combine_vec_sub_add0:80; SSE: # %bb.0:81; SSE-NEXT: movaps %xmm1, %xmm082; SSE-NEXT: retq83;84; AVX-LABEL: combine_vec_sub_add0:85; AVX: # %bb.0:86; AVX-NEXT: vmovaps %xmm1, %xmm087; AVX-NEXT: retq88 %1 = add <4 x i32> %a, %b89 %2 = sub <4 x i32> %1, %a90 ret <4 x i32> %291}92 93; fold (A+B)-B -> A94define <4 x i32> @combine_vec_sub_add1(<4 x i32> %a, <4 x i32> %b) {95; CHECK-LABEL: combine_vec_sub_add1:96; CHECK: # %bb.0:97; CHECK-NEXT: retq98 %1 = add <4 x i32> %a, %b99 %2 = sub <4 x i32> %1, %b100 ret <4 x i32> %2101}102 103; fold C2-(A+C1) -> (C2-C1)-A104define <4 x i32> @combine_vec_sub_constant_add(<4 x i32> %a) {105; SSE-LABEL: combine_vec_sub_constant_add:106; SSE: # %bb.0:107; SSE-NEXT: pmovsxbd {{.*#+}} xmm1 = [3,1,4294967295,4294967293]108; SSE-NEXT: psubd %xmm0, %xmm1109; SSE-NEXT: movdqa %xmm1, %xmm0110; SSE-NEXT: retq111;112; AVX-LABEL: combine_vec_sub_constant_add:113; AVX: # %bb.0:114; AVX-NEXT: vpmovsxbd {{.*#+}} xmm1 = [3,1,4294967295,4294967293]115; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0116; AVX-NEXT: retq117 %1 = add <4 x i32> %a, <i32 0, i32 1, i32 2, i32 3>118 %2 = sub <4 x i32> <i32 3, i32 2, i32 1, i32 0>, %1119 ret <4 x i32> %2120}121 122; fold ((A+(B+C))-B) -> A+C123define <4 x i32> @combine_vec_sub_add_add(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {124; SSE-LABEL: combine_vec_sub_add_add:125; SSE: # %bb.0:126; SSE-NEXT: paddd %xmm2, %xmm0127; SSE-NEXT: retq128;129; AVX-LABEL: combine_vec_sub_add_add:130; AVX: # %bb.0:131; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0132; AVX-NEXT: retq133 %1 = add <4 x i32> %b, %c134 %2 = add <4 x i32> %a, %1135 %3 = sub <4 x i32> %2, %b136 ret <4 x i32> %3137}138 139; fold ((A+(B-C))-B) -> A-C140define <4 x i32> @combine_vec_sub_add_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {141; SSE-LABEL: combine_vec_sub_add_sub:142; SSE: # %bb.0:143; SSE-NEXT: psubd %xmm2, %xmm0144; SSE-NEXT: retq145;146; AVX-LABEL: combine_vec_sub_add_sub:147; AVX: # %bb.0:148; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0149; AVX-NEXT: retq150 %1 = sub <4 x i32> %b, %c151 %2 = add <4 x i32> %a, %1152 %3 = sub <4 x i32> %2, %b153 ret <4 x i32> %3154}155 156; fold ((A-(B-C))-C) -> A-B157define <4 x i32> @combine_vec_sub_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {158; SSE-LABEL: combine_vec_sub_sub_sub:159; SSE: # %bb.0:160; SSE-NEXT: psubd %xmm1, %xmm0161; SSE-NEXT: retq162;163; AVX-LABEL: combine_vec_sub_sub_sub:164; AVX: # %bb.0:165; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0166; AVX-NEXT: retq167 %1 = sub <4 x i32> %b, %c168 %2 = sub <4 x i32> %a, %1169 %3 = sub <4 x i32> %2, %c170 ret <4 x i32> %3171}172 173; fold undef-A -> undef174define <4 x i32> @combine_vec_sub_undef0(<4 x i32> %a) {175; CHECK-LABEL: combine_vec_sub_undef0:176; CHECK: # %bb.0:177; CHECK-NEXT: retq178 %1 = sub <4 x i32> undef, %a179 ret <4 x i32> %1180}181 182; fold A-undef -> undef183define <4 x i32> @combine_vec_sub_undef1(<4 x i32> %a) {184; CHECK-LABEL: combine_vec_sub_undef1:185; CHECK: # %bb.0:186; CHECK-NEXT: retq187 %1 = sub <4 x i32> %a, undef188 ret <4 x i32> %1189}190 191; sub X, (sext Y i1) -> add X, (and Y 1)192define <4 x i32> @combine_vec_add_sext(<4 x i32> %x, <4 x i1> %y) {193; SSE-LABEL: combine_vec_add_sext:194; SSE: # %bb.0:195; SSE-NEXT: pslld $31, %xmm1196; SSE-NEXT: psrad $31, %xmm1197; SSE-NEXT: psubd %xmm1, %xmm0198; SSE-NEXT: retq199;200; AVX-LABEL: combine_vec_add_sext:201; AVX: # %bb.0:202; AVX-NEXT: vpslld $31, %xmm1, %xmm1203; AVX-NEXT: vpsrad $31, %xmm1, %xmm1204; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0205; AVX-NEXT: retq206 %1 = sext <4 x i1> %y to <4 x i32>207 %2 = sub <4 x i32> %x, %1208 ret <4 x i32> %2209}210 211; sub X, (sextinreg Y i1) -> add X, (and Y 1)212define <4 x i32> @combine_vec_sub_sextinreg(<4 x i32> %x, <4 x i32> %y) {213; SSE-LABEL: combine_vec_sub_sextinreg:214; SSE: # %bb.0:215; SSE-NEXT: pslld $31, %xmm1216; SSE-NEXT: psrad $31, %xmm1217; SSE-NEXT: psubd %xmm1, %xmm0218; SSE-NEXT: retq219;220; AVX-LABEL: combine_vec_sub_sextinreg:221; AVX: # %bb.0:222; AVX-NEXT: vpslld $31, %xmm1, %xmm1223; AVX-NEXT: vpsrad $31, %xmm1, %xmm1224; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0225; AVX-NEXT: retq226 %1 = shl <4 x i32> %y, <i32 31, i32 31, i32 31, i32 31>227 %2 = ashr <4 x i32> %1, <i32 31, i32 31, i32 31, i32 31>228 %3 = sub <4 x i32> %x, %2229 ret <4 x i32> %3230}231 232; sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1233define i32 @combine_sub_xor_consts(i32 %x) {234; CHECK-LABEL: combine_sub_xor_consts:235; CHECK: # %bb.0:236; CHECK-NEXT: # kill: def $edi killed $edi def $rdi237; CHECK-NEXT: xorl $-32, %edi238; CHECK-NEXT: leal 33(%rdi), %eax239; CHECK-NEXT: retq240 %xor = xor i32 %x, 31241 %sub = sub i32 32, %xor242 ret i32 %sub243}244 245define <4 x i32> @combine_vec_sub_xor_consts(<4 x i32> %x) {246; SSE-LABEL: combine_vec_sub_xor_consts:247; SSE: # %bb.0:248; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0249; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0250; SSE-NEXT: retq251;252; AVX-LABEL: combine_vec_sub_xor_consts:253; AVX: # %bb.0:254; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0255; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0256; AVX-NEXT: retq257 %xor = xor <4 x i32> %x, <i32 28, i32 29, i32 -1, i32 -31>258 %sub = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %xor259 ret <4 x i32> %sub260}261 262define <4 x i32> @combine_vec_neg_xor_consts(<4 x i32> %x) {263; SSE-LABEL: combine_vec_neg_xor_consts:264; SSE: # %bb.0:265; SSE-NEXT: pcmpeqd %xmm1, %xmm1266; SSE-NEXT: psubd %xmm1, %xmm0267; SSE-NEXT: retq268;269; AVX-LABEL: combine_vec_neg_xor_consts:270; AVX: # %bb.0:271; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1272; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0273; AVX-NEXT: retq274 %xor = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>275 %sub = sub <4 x i32> zeroinitializer, %xor276 ret <4 x i32> %sub277}278 279; With AVX, this could use broadcast (an extra load) and280; load-folded 'add', but currently we favor the virtually281; free pcmpeq instruction.282 283define void @PR52032_oneuse_constant(ptr %p) {284; SSE-LABEL: PR52032_oneuse_constant:285; SSE: # %bb.0:286; SSE-NEXT: movdqu (%rdi), %xmm0287; SSE-NEXT: movdqu 16(%rdi), %xmm1288; SSE-NEXT: pcmpeqd %xmm2, %xmm2289; SSE-NEXT: psubd %xmm2, %xmm1290; SSE-NEXT: psubd %xmm2, %xmm0291; SSE-NEXT: movdqu %xmm0, (%rdi)292; SSE-NEXT: movdqu %xmm1, 16(%rdi)293; SSE-NEXT: retq294;295; AVX-LABEL: PR52032_oneuse_constant:296; AVX: # %bb.0:297; AVX-NEXT: vmovdqu (%rdi), %ymm0298; AVX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1299; AVX-NEXT: vpsubd %ymm1, %ymm0, %ymm0300; AVX-NEXT: vmovdqu %ymm0, (%rdi)301; AVX-NEXT: vzeroupper302; AVX-NEXT: retq303 %i3 = load <8 x i32>, ptr %p, align 4304 %i4 = add nsw <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>305 store <8 x i32> %i4, ptr %p, align 4306 ret void307}308 309; With AVX, we don't transform 'add' to 'sub' because that prevents load folding.310; With SSE, we do it because we can't load fold the other op without overwriting the constant op.311 312define void @PR52032(ptr %p) {313; SSE-LABEL: PR52032:314; SSE: # %bb.0:315; SSE-NEXT: pcmpeqd %xmm0, %xmm0316; SSE-NEXT: movdqu (%rdi), %xmm1317; SSE-NEXT: movdqu 16(%rdi), %xmm2318; SSE-NEXT: movdqu 32(%rdi), %xmm3319; SSE-NEXT: movdqu 48(%rdi), %xmm4320; SSE-NEXT: psubd %xmm0, %xmm2321; SSE-NEXT: psubd %xmm0, %xmm1322; SSE-NEXT: movdqu %xmm1, (%rdi)323; SSE-NEXT: movdqu %xmm2, 16(%rdi)324; SSE-NEXT: psubd %xmm0, %xmm4325; SSE-NEXT: psubd %xmm0, %xmm3326; SSE-NEXT: movdqu %xmm3, 32(%rdi)327; SSE-NEXT: movdqu %xmm4, 48(%rdi)328; SSE-NEXT: retq329;330; AVX-LABEL: PR52032:331; AVX: # %bb.0:332; AVX-NEXT: vpbroadcastd {{.*#+}} ymm0 = [1,1,1,1,1,1,1,1]333; AVX-NEXT: vpaddd (%rdi), %ymm0, %ymm1334; AVX-NEXT: vmovdqu %ymm1, (%rdi)335; AVX-NEXT: vpaddd 32(%rdi), %ymm0, %ymm0336; AVX-NEXT: vmovdqu %ymm0, 32(%rdi)337; AVX-NEXT: vzeroupper338; AVX-NEXT: retq339 %i3 = load <8 x i32>, ptr %p, align 4340 %i4 = add nsw <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>341 store <8 x i32> %i4, ptr %p, align 4342 %p2 = getelementptr inbounds <8 x i32>, ptr %p, i64 1343 %i8 = load <8 x i32>, ptr %p2, align 4344 %i9 = add nsw <8 x i32> %i8, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>345 store <8 x i32> %i9, ptr %p2, align 4346 ret void347}348 349; Same as above, but 128-bit ops:350; With AVX, we don't transform 'add' to 'sub' because that prevents load folding.351; With SSE, we do it because we can't load fold the other op without overwriting the constant op.352 353define void @PR52032_2(ptr %p) {354; SSE-LABEL: PR52032_2:355; SSE: # %bb.0:356; SSE-NEXT: pcmpeqd %xmm0, %xmm0357; SSE-NEXT: movdqu (%rdi), %xmm1358; SSE-NEXT: movdqu 16(%rdi), %xmm2359; SSE-NEXT: psubd %xmm0, %xmm1360; SSE-NEXT: movdqu %xmm1, (%rdi)361; SSE-NEXT: psubd %xmm0, %xmm2362; SSE-NEXT: movdqu %xmm2, 16(%rdi)363; SSE-NEXT: retq364;365; AVX-LABEL: PR52032_2:366; AVX: # %bb.0:367; AVX-NEXT: vpbroadcastd {{.*#+}} xmm0 = [1,1,1,1]368; AVX-NEXT: vpaddd (%rdi), %xmm0, %xmm1369; AVX-NEXT: vmovdqu %xmm1, (%rdi)370; AVX-NEXT: vpaddd 16(%rdi), %xmm0, %xmm0371; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)372; AVX-NEXT: retq373 %i3 = load <4 x i32>, ptr %p, align 4374 %i4 = add nsw <4 x i32> %i3, <i32 1, i32 1, i32 1, i32 1>375 store <4 x i32> %i4, ptr %p, align 4376 %p2 = getelementptr inbounds <4 x i32>, ptr %p, i64 1377 %i8 = load <4 x i32>, ptr %p2, align 4378 %i9 = add nsw <4 x i32> %i8, <i32 1, i32 1, i32 1, i32 1>379 store <4 x i32> %i9, ptr %p2, align 4380 ret void381}382 383; If we are starting with a 'sub', it is always better to do the transform.384 385define void @PR52032_3(ptr %p) {386; SSE-LABEL: PR52032_3:387; SSE: # %bb.0:388; SSE-NEXT: pcmpeqd %xmm0, %xmm0389; SSE-NEXT: movdqu (%rdi), %xmm1390; SSE-NEXT: movdqu 16(%rdi), %xmm2391; SSE-NEXT: paddd %xmm0, %xmm1392; SSE-NEXT: movdqu %xmm1, (%rdi)393; SSE-NEXT: paddd %xmm0, %xmm2394; SSE-NEXT: movdqu %xmm2, 16(%rdi)395; SSE-NEXT: retq396;397; AVX-LABEL: PR52032_3:398; AVX: # %bb.0:399; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0400; AVX-NEXT: vpaddd (%rdi), %xmm0, %xmm1401; AVX-NEXT: vmovdqu %xmm1, (%rdi)402; AVX-NEXT: vpaddd 16(%rdi), %xmm0, %xmm0403; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)404; AVX-NEXT: retq405 %i3 = load <4 x i32>, ptr %p, align 4406 %i4 = sub nsw <4 x i32> %i3, <i32 1, i32 1, i32 1, i32 1>407 store <4 x i32> %i4, ptr %p, align 4408 %p2 = getelementptr inbounds <4 x i32>, ptr %p, i64 1409 %i8 = load <4 x i32>, ptr %p2, align 4410 %i9 = sub nsw <4 x i32> %i8, <i32 1, i32 1, i32 1, i32 1>411 store <4 x i32> %i9, ptr %p2, align 4412 ret void413}414 415; If there's no chance of profitable load folding (because of extra uses), we convert 'add' to 'sub'.416 417define void @PR52032_4(ptr %p, ptr %q) {418; SSE-LABEL: PR52032_4:419; SSE: # %bb.0:420; SSE-NEXT: movdqu (%rdi), %xmm0421; SSE-NEXT: movdqa %xmm0, (%rsi)422; SSE-NEXT: pcmpeqd %xmm1, %xmm1423; SSE-NEXT: psubd %xmm1, %xmm0424; SSE-NEXT: movdqu %xmm0, (%rdi)425; SSE-NEXT: movdqu 16(%rdi), %xmm0426; SSE-NEXT: movdqa %xmm0, 16(%rsi)427; SSE-NEXT: psubd %xmm1, %xmm0428; SSE-NEXT: movdqu %xmm0, 16(%rdi)429; SSE-NEXT: retq430;431; AVX-LABEL: PR52032_4:432; AVX: # %bb.0:433; AVX-NEXT: vmovdqu (%rdi), %xmm0434; AVX-NEXT: vmovdqa %xmm0, (%rsi)435; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1436; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0437; AVX-NEXT: vmovdqu %xmm0, (%rdi)438; AVX-NEXT: vmovdqu 16(%rdi), %xmm0439; AVX-NEXT: vmovdqa %xmm0, 16(%rsi)440; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0441; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)442; AVX-NEXT: retq443 %i3 = load <4 x i32>, ptr %p, align 4444 store <4 x i32> %i3, ptr %q445 %i4 = add nsw <4 x i32> %i3, <i32 1, i32 1, i32 1, i32 1>446 store <4 x i32> %i4, ptr %p, align 4447 %p2 = getelementptr inbounds <4 x i32>, ptr %p, i64 1448 %q2 = getelementptr inbounds <4 x i32>, ptr %q, i64 1449 %i8 = load <4 x i32>, ptr %p2, align 4450 store <4 x i32> %i8, ptr %q2451 %i9 = add nsw <4 x i32> %i8, <i32 1, i32 1, i32 1, i32 1>452 store <4 x i32> %i9, ptr %p2, align 4453 ret void454}455 456; Fold sub(32,xor(bsr(x),31)) -> add(xor(bsr(x),-32),33) -> add(or(bsr(x),-32),33) -> add(bsr(x),1)457define i32 @PR74101(i32 %a0) {458; CHECK-LABEL: PR74101:459; CHECK: # %bb.0:460; CHECK-NEXT: bsrl %edi, %eax461; CHECK-NEXT: incl %eax462; CHECK-NEXT: retq463 %lz = call i32 @llvm.ctlz.i32(i32 %a0, i1 true)464 %add = sub nuw nsw i32 32, %lz465 ret i32 %add466}467