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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX4 5declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone6declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone7declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8) nounwind readnone8declare { i8, i1 } @llvm.usub.with.overflow.i8(i8, i8) nounwind readnone9 10 11declare {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone12declare {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone13declare { <4 x i8>, <4 x i1> } @llvm.ssub.with.overflow.v4i8(<4 x i8>, <4 x i8>) nounwind readnone14declare { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> , <4 x i8>) nounwind readnone15 16; fold (ssub x, 0) -> x17define i32 @combine_ssub_zero(i32 %a0, i32 %a1) {18; CHECK-LABEL: combine_ssub_zero:19; CHECK: # %bb.0:20; CHECK-NEXT: movl %edi, %eax21; CHECK-NEXT: retq22 %1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 zeroinitializer)23 %2 = extractvalue {i32, i1} %1, 024 %3 = extractvalue {i32, i1} %1, 125 %4 = select i1 %3, i32 %a1, i32 %226 ret i32 %427}28 29define <4 x i32> @combine_vec_ssub_zero(<4 x i32> %a0, <4 x i32> %a1) {30; CHECK-LABEL: combine_vec_ssub_zero:31; CHECK: # %bb.0:32; CHECK-NEXT: retq33 %1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)34 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 035 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 136 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %237 ret <4 x i32> %438}39 40; fold (usub x, 0) -> x41define i32 @combine_usub_zero(i32 %a0, i32 %a1) {42; CHECK-LABEL: combine_usub_zero:43; CHECK: # %bb.0:44; CHECK-NEXT: movl %edi, %eax45; CHECK-NEXT: retq46 %1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a0, i32 zeroinitializer)47 %2 = extractvalue {i32, i1} %1, 048 %3 = extractvalue {i32, i1} %1, 149 %4 = select i1 %3, i32 %a1, i32 %250 ret i32 %451}52 53define <4 x i32> @combine_vec_usub_zero(<4 x i32> %a0, <4 x i32> %a1) {54; CHECK-LABEL: combine_vec_usub_zero:55; CHECK: # %bb.0:56; CHECK-NEXT: retq57 %1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)58 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 059 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 160 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %261 ret <4 x i32> %462}63 64; fold (ssub x, x) -> 065define i32 @combine_ssub_self(i32 %a0, i32 %a1) {66; CHECK-LABEL: combine_ssub_self:67; CHECK: # %bb.0:68; CHECK-NEXT: xorl %eax, %eax69; CHECK-NEXT: retq70 %1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 %a0)71 %2 = extractvalue {i32, i1} %1, 072 %3 = extractvalue {i32, i1} %1, 173 %4 = select i1 %3, i32 %a1, i32 %274 ret i32 %475}76 77define <4 x i32> @combine_vec_ssub_self(<4 x i32> %a0, <4 x i32> %a1) {78; SSE-LABEL: combine_vec_ssub_self:79; SSE: # %bb.0:80; SSE-NEXT: xorps %xmm0, %xmm081; SSE-NEXT: retq82;83; AVX-LABEL: combine_vec_ssub_self:84; AVX: # %bb.0:85; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm086; AVX-NEXT: retq87 %1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a0)88 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 089 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 190 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %291 ret <4 x i32> %492}93 94; fold (usub x, x) -> x95define i32 @combine_usub_self(i32 %a0, i32 %a1) {96; CHECK-LABEL: combine_usub_self:97; CHECK: # %bb.0:98; CHECK-NEXT: xorl %eax, %eax99; CHECK-NEXT: retq100 %1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a0, i32 %a0)101 %2 = extractvalue {i32, i1} %1, 0102 %3 = extractvalue {i32, i1} %1, 1103 %4 = select i1 %3, i32 %a1, i32 %2104 ret i32 %4105}106 107define <4 x i32> @combine_vec_usub_self(<4 x i32> %a0, <4 x i32> %a1) {108; SSE-LABEL: combine_vec_usub_self:109; SSE: # %bb.0:110; SSE-NEXT: xorps %xmm0, %xmm0111; SSE-NEXT: retq112;113; AVX-LABEL: combine_vec_usub_self:114; AVX: # %bb.0:115; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0116; AVX-NEXT: retq117 %1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a0)118 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0119 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1120 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2121 ret <4 x i32> %4122}123 124; fold (usub -1, x) -> (xor x, -1) + no borrow125define i32 @combine_usub_negone(i32 %a0, i32 %a1) {126; CHECK-LABEL: combine_usub_negone:127; CHECK: # %bb.0:128; CHECK-NEXT: movl %edi, %eax129; CHECK-NEXT: notl %eax130; CHECK-NEXT: retq131 %1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -1, i32 %a0)132 %2 = extractvalue {i32, i1} %1, 0133 %3 = extractvalue {i32, i1} %1, 1134 %4 = select i1 %3, i32 %a1, i32 %2135 ret i32 %4136}137 138define <4 x i32> @combine_vec_usub_negone(<4 x i32> %a0, <4 x i32> %a1) {139; SSE-LABEL: combine_vec_usub_negone:140; SSE: # %bb.0:141; SSE-NEXT: pcmpeqd %xmm1, %xmm1142; SSE-NEXT: pxor %xmm1, %xmm0143; SSE-NEXT: retq144;145; AVX-LABEL: combine_vec_usub_negone:146; AVX: # %bb.0:147; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1148; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0149; AVX-NEXT: retq150 %1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a0)151 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0152 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1153 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2154 ret <4 x i32> %4155}156 157define { i32, i1 } @combine_usub_nuw(i32 %a, i32 %b) {158; CHECK-LABEL: combine_usub_nuw:159; CHECK: # %bb.0:160; CHECK-NEXT: movl %edi, %eax161; CHECK-NEXT: orl $-2147483648, %eax # imm = 0x80000000162; CHECK-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF163; CHECK-NEXT: subl %esi, %eax164; CHECK-NEXT: xorl %edx, %edx165; CHECK-NEXT: retq166 %aa = or i32 %a, 2147483648167 %bb = and i32 %b, 2147483647168 %x = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %aa, i32 %bb)169 ret { i32, i1 } %x170}171 172define { i8, i1 } @usub_always_overflow(i8 %x) nounwind {173; CHECK-LABEL: usub_always_overflow:174; CHECK: # %bb.0:175; CHECK-NEXT: orb $64, %dil176; CHECK-NEXT: movb $63, %al177; CHECK-NEXT: subb %dil, %al178; CHECK-NEXT: setb %dl179; CHECK-NEXT: retq180 %y = or i8 %x, 64181 %a = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 63, i8 %y)182 ret { i8, i1 } %a183}184 185define { i8, i1 } @ssub_always_overflow(i8 %x) nounwind {186; CHECK-LABEL: ssub_always_overflow:187; CHECK: # %bb.0:188; CHECK-NEXT: cmpb $30, %dil189; CHECK-NEXT: movl $29, %ecx190; CHECK-NEXT: cmovgel %edi, %ecx191; CHECK-NEXT: movb $-100, %al192; CHECK-NEXT: subb %cl, %al193; CHECK-NEXT: seto %dl194; CHECK-NEXT: retq195 %c = icmp sgt i8 %x, 29196 %y = select i1 %c, i8 %x, i8 29197 %a = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 -100, i8 %y)198 ret { i8, i1 } %a199}200 201define { <4 x i8>, <4 x i1> } @always_usub_const_vector() nounwind {202; SSE-LABEL: always_usub_const_vector:203; SSE: # %bb.0:204; SSE-NEXT: pcmpeqd %xmm0, %xmm0205; SSE-NEXT: pcmpeqd %xmm1, %xmm1206; SSE-NEXT: retq207;208; AVX-LABEL: always_usub_const_vector:209; AVX: # %bb.0:210; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0211; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1212; AVX-NEXT: retq213 %x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> <i8 0, i8 0, i8 0, i8 0>, <4 x i8> <i8 1, i8 1, i8 1, i8 1>)214 ret { <4 x i8>, <4 x i1> } %x215}216 217define { <4 x i8>, <4 x i1> } @never_usub_const_vector() nounwind {218; SSE-LABEL: never_usub_const_vector:219; SSE: # %bb.0:220; SSE-NEXT: movss {{.*#+}} xmm0 = [127,255,0,254,0,0,0,0,0,0,0,0,0,0,0,0]221; SSE-NEXT: xorps %xmm1, %xmm1222; SSE-NEXT: retq223;224; AVX-LABEL: never_usub_const_vector:225; AVX: # %bb.0:226; AVX-NEXT: vmovss {{.*#+}} xmm0 = [127,255,0,254,0,0,0,0,0,0,0,0,0,0,0,0]227; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1228; AVX-NEXT: retq229 %x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> <i8 255, i8 255, i8 255, i8 255>, <4 x i8> <i8 128, i8 0, i8 255, i8 1>)230 ret { <4 x i8>, <4 x i1> } %x231}232