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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2;RUN: llc -mtriple=x86_64-apple-darwin -mcpu=skx < %s | FileCheck %s3 4define i32 @combineTESTM_AND_1(<8 x i64> %a, <8 x i64> %b) {5; CHECK-LABEL: combineTESTM_AND_1:6; CHECK: ## %bb.0:7; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k08; CHECK-NEXT: kmovb %k0, %eax9; CHECK-NEXT: vzeroupper10; CHECK-NEXT: retq11 %and.i = and <8 x i64> %b, %a12 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 -1)13 %conv = zext i8 %test.i to i3214 ret i32 %conv15}16 17define i32 @combineTESTM_AND_2(<8 x i64> %a, <8 x i64> %b , i8 %mask) {18; CHECK-LABEL: combineTESTM_AND_2:19; CHECK: ## %bb.0:20; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k021; CHECK-NEXT: kmovd %k0, %eax22; CHECK-NEXT: andb %dil, %al23; CHECK-NEXT: movzbl %al, %eax24; CHECK-NEXT: vzeroupper25; CHECK-NEXT: retq26 %and.i = and <8 x i64> %b, %a27 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 %mask)28 %conv = zext i8 %test.i to i3229 ret i32 %conv30}31 32define i32 @combineTESTM_AND_mask_3(<8 x i64> %a, ptr %bptr , i8 %mask) {33; CHECK-LABEL: combineTESTM_AND_mask_3:34; CHECK: ## %bb.0:35; CHECK-NEXT: vptestmq (%rdi), %zmm0, %k036; CHECK-NEXT: kmovd %k0, %eax37; CHECK-NEXT: andb %sil, %al38; CHECK-NEXT: movzbl %al, %eax39; CHECK-NEXT: vzeroupper40; CHECK-NEXT: retq41 %b = load <8 x i64>, ptr %bptr42 %and.i = and <8 x i64> %a, %b43 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 %mask)44 %conv = zext i8 %test.i to i3245 ret i32 %conv46}47 48define i32 @combineTESTM_AND_mask_4(<8 x i64> %a, ptr %bptr , i8 %mask) {49; CHECK-LABEL: combineTESTM_AND_mask_4:50; CHECK: ## %bb.0:51; CHECK-NEXT: vptestmq (%rdi), %zmm0, %k052; CHECK-NEXT: kmovd %k0, %eax53; CHECK-NEXT: andb %sil, %al54; CHECK-NEXT: movzbl %al, %eax55; CHECK-NEXT: vzeroupper56; CHECK-NEXT: retq57 %b = load <8 x i64>, ptr %bptr58 %and.i = and <8 x i64> %b, %a59 %test.i = tail call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %and.i, <8 x i64> %and.i, i8 %mask)60 %conv = zext i8 %test.i to i3261 ret i32 %conv62}63 64declare i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64>, <8 x i64>, i8)65