815 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX15; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX26; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CHECK,XOP7 8; fold (udiv x, 1) -> x9define i32 @combine_udiv_by_one(i32 %x) {10; CHECK-LABEL: combine_udiv_by_one:11; CHECK: # %bb.0:12; CHECK-NEXT: movl %edi, %eax13; CHECK-NEXT: retq14 %1 = udiv i32 %x, 115 ret i32 %116}17 18define <4 x i32> @combine_vec_udiv_by_one(<4 x i32> %x) {19; CHECK-LABEL: combine_vec_udiv_by_one:20; CHECK: # %bb.0:21; CHECK-NEXT: retq22 %1 = udiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>23 ret <4 x i32> %124}25 26; fold (udiv x, -1) -> select((icmp eq x, -1), 1, 0)27define i32 @combine_udiv_by_negone(i32 %x) {28; CHECK-LABEL: combine_udiv_by_negone:29; CHECK: # %bb.0:30; CHECK-NEXT: xorl %eax, %eax31; CHECK-NEXT: cmpl $-1, %edi32; CHECK-NEXT: sete %al33; CHECK-NEXT: retq34 %1 = udiv i32 %x, -135 ret i32 %136}37 38define <4 x i32> @combine_vec_udiv_by_negone(<4 x i32> %x) {39; SSE-LABEL: combine_vec_udiv_by_negone:40; SSE: # %bb.0:41; SSE-NEXT: pcmpeqd %xmm1, %xmm142; SSE-NEXT: pcmpeqd %xmm1, %xmm043; SSE-NEXT: psrld $31, %xmm044; SSE-NEXT: retq45;46; AVX-LABEL: combine_vec_udiv_by_negone:47; AVX: # %bb.0:48; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm149; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm050; AVX-NEXT: vpsrld $31, %xmm0, %xmm051; AVX-NEXT: retq52;53; XOP-LABEL: combine_vec_udiv_by_negone:54; XOP: # %bb.0:55; XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm156; XOP-NEXT: vpcomeqd %xmm1, %xmm0, %xmm057; XOP-NEXT: vpsrld $31, %xmm0, %xmm058; XOP-NEXT: retq59 %1 = udiv <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>60 ret <4 x i32> %161}62 63; fold (udiv x, INT_MIN) -> (srl x, 31)64define i32 @combine_udiv_by_minsigned(i32 %x) {65; CHECK-LABEL: combine_udiv_by_minsigned:66; CHECK: # %bb.0:67; CHECK-NEXT: movl %edi, %eax68; CHECK-NEXT: shrl $31, %eax69; CHECK-NEXT: retq70 %1 = udiv i32 %x, -214748364871 ret i32 %172}73 74define <4 x i32> @combine_vec_udiv_by_minsigned(<4 x i32> %x) {75; SSE-LABEL: combine_vec_udiv_by_minsigned:76; SSE: # %bb.0:77; SSE-NEXT: psrld $31, %xmm078; SSE-NEXT: retq79;80; AVX-LABEL: combine_vec_udiv_by_minsigned:81; AVX: # %bb.0:82; AVX-NEXT: vpsrld $31, %xmm0, %xmm083; AVX-NEXT: retq84;85; XOP-LABEL: combine_vec_udiv_by_minsigned:86; XOP: # %bb.0:87; XOP-NEXT: vpsrld $31, %xmm0, %xmm088; XOP-NEXT: retq89 %1 = udiv <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>90 ret <4 x i32> %191}92 93; fold (udiv 0, x) -> 094define i32 @combine_udiv_zero(i32 %x) {95; CHECK-LABEL: combine_udiv_zero:96; CHECK: # %bb.0:97; CHECK-NEXT: xorl %eax, %eax98; CHECK-NEXT: retq99 %1 = udiv i32 0, %x100 ret i32 %1101}102 103define <4 x i32> @combine_vec_udiv_zero(<4 x i32> %x) {104; SSE-LABEL: combine_vec_udiv_zero:105; SSE: # %bb.0:106; SSE-NEXT: xorps %xmm0, %xmm0107; SSE-NEXT: retq108;109; AVX-LABEL: combine_vec_udiv_zero:110; AVX: # %bb.0:111; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0112; AVX-NEXT: retq113;114; XOP-LABEL: combine_vec_udiv_zero:115; XOP: # %bb.0:116; XOP-NEXT: vxorps %xmm0, %xmm0, %xmm0117; XOP-NEXT: retq118 %1 = udiv <4 x i32> zeroinitializer, %x119 ret <4 x i32> %1120}121 122; fold (udiv x, x) -> 1123define i32 @combine_udiv_dupe(i32 %x) {124; CHECK-LABEL: combine_udiv_dupe:125; CHECK: # %bb.0:126; CHECK-NEXT: movl $1, %eax127; CHECK-NEXT: retq128 %1 = udiv i32 %x, %x129 ret i32 %1130}131 132define <4 x i32> @combine_vec_udiv_dupe(<4 x i32> %x) {133; SSE-LABEL: combine_vec_udiv_dupe:134; SSE: # %bb.0:135; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,1,1,1]136; SSE-NEXT: retq137;138; AVX-LABEL: combine_vec_udiv_dupe:139; AVX: # %bb.0:140; AVX-NEXT: vbroadcastss {{.*#+}} xmm0 = [1,1,1,1]141; AVX-NEXT: retq142;143; XOP-LABEL: combine_vec_udiv_dupe:144; XOP: # %bb.0:145; XOP-NEXT: vbroadcastss {{.*#+}} xmm0 = [1,1,1,1]146; XOP-NEXT: retq147 %1 = udiv <4 x i32> %x, %x148 ret <4 x i32> %1149}150 151; fold (udiv x, (1 << c)) -> x >>u c152define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {153; SSE-LABEL: combine_vec_udiv_by_pow2a:154; SSE: # %bb.0:155; SSE-NEXT: psrld $2, %xmm0156; SSE-NEXT: retq157;158; AVX-LABEL: combine_vec_udiv_by_pow2a:159; AVX: # %bb.0:160; AVX-NEXT: vpsrld $2, %xmm0, %xmm0161; AVX-NEXT: retq162;163; XOP-LABEL: combine_vec_udiv_by_pow2a:164; XOP: # %bb.0:165; XOP-NEXT: vpsrld $2, %xmm0, %xmm0166; XOP-NEXT: retq167 %1 = udiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>168 ret <4 x i32> %1169}170 171define <4 x i32> @combine_vec_udiv_by_pow2b(<4 x i32> %x) {172; SSE2-LABEL: combine_vec_udiv_by_pow2b:173; SSE2: # %bb.0:174; SSE2-NEXT: movdqa %xmm0, %xmm1175; SSE2-NEXT: psrld $4, %xmm1176; SSE2-NEXT: movdqa %xmm0, %xmm2177; SSE2-NEXT: psrld $3, %xmm2178; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1]179; SSE2-NEXT: movdqa %xmm0, %xmm1180; SSE2-NEXT: psrld $2, %xmm1181; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]182; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3]183; SSE2-NEXT: retq184;185; SSE41-LABEL: combine_vec_udiv_by_pow2b:186; SSE41: # %bb.0:187; SSE41-NEXT: movdqa %xmm0, %xmm1188; SSE41-NEXT: psrld $4, %xmm1189; SSE41-NEXT: movdqa %xmm0, %xmm2190; SSE41-NEXT: psrld $2, %xmm2191; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]192; SSE41-NEXT: movdqa %xmm0, %xmm1193; SSE41-NEXT: psrld $3, %xmm1194; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]195; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]196; SSE41-NEXT: retq197;198; AVX1-LABEL: combine_vec_udiv_by_pow2b:199; AVX1: # %bb.0:200; AVX1-NEXT: vpsrld $4, %xmm0, %xmm1201; AVX1-NEXT: vpsrld $2, %xmm0, %xmm2202; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]203; AVX1-NEXT: vpsrld $3, %xmm0, %xmm2204; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]205; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]206; AVX1-NEXT: retq207;208; AVX2-LABEL: combine_vec_udiv_by_pow2b:209; AVX2: # %bb.0:210; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0211; AVX2-NEXT: retq212;213; XOP-LABEL: combine_vec_udiv_by_pow2b:214; XOP: # %bb.0:215; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0216; XOP-NEXT: retq217 %1 = udiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>218 ret <4 x i32> %1219}220 221define <4 x i32> @combine_vec_udiv_by_pow2c(<4 x i32> %x, <4 x i32> %y) {222; SSE2-LABEL: combine_vec_udiv_by_pow2c:223; SSE2: # %bb.0:224; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]225; SSE2-NEXT: movdqa %xmm0, %xmm3226; SSE2-NEXT: psrld %xmm2, %xmm3227; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]228; SSE2-NEXT: movdqa %xmm0, %xmm2229; SSE2-NEXT: psrld %xmm4, %xmm2230; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]231; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]232; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]233; SSE2-NEXT: movdqa %xmm0, %xmm4234; SSE2-NEXT: psrld %xmm3, %xmm4235; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]236; SSE2-NEXT: psrld %xmm1, %xmm0237; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]238; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]239; SSE2-NEXT: movaps %xmm2, %xmm0240; SSE2-NEXT: retq241;242; SSE41-LABEL: combine_vec_udiv_by_pow2c:243; SSE41: # %bb.0:244; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]245; SSE41-NEXT: movdqa %xmm0, %xmm3246; SSE41-NEXT: psrld %xmm2, %xmm3247; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]248; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]249; SSE41-NEXT: movdqa %xmm0, %xmm5250; SSE41-NEXT: psrld %xmm4, %xmm5251; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]252; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]253; SSE41-NEXT: movdqa %xmm0, %xmm3254; SSE41-NEXT: psrld %xmm1, %xmm3255; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]256; SSE41-NEXT: psrld %xmm1, %xmm0257; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]258; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]259; SSE41-NEXT: retq260;261; AVX1-LABEL: combine_vec_udiv_by_pow2c:262; AVX1: # %bb.0:263; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero264; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2265; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3266; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3267; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]268; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3269; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]270; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3271; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero272; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0273; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]274; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]275; AVX1-NEXT: retq276;277; AVX2-LABEL: combine_vec_udiv_by_pow2c:278; AVX2: # %bb.0:279; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0280; AVX2-NEXT: retq281;282; XOP-LABEL: combine_vec_udiv_by_pow2c:283; XOP: # %bb.0:284; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2285; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1286; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm0287; XOP-NEXT: retq288 %1 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y289 %2 = udiv <4 x i32> %x, %1290 ret <4 x i32> %2291}292 293; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2294define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {295; SSE2-LABEL: combine_vec_udiv_by_shl_pow2a:296; SSE2: # %bb.0:297; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1298; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]299; SSE2-NEXT: movdqa %xmm0, %xmm3300; SSE2-NEXT: psrld %xmm2, %xmm3301; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]302; SSE2-NEXT: movdqa %xmm0, %xmm2303; SSE2-NEXT: psrld %xmm4, %xmm2304; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]305; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]306; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]307; SSE2-NEXT: movdqa %xmm0, %xmm4308; SSE2-NEXT: psrld %xmm3, %xmm4309; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]310; SSE2-NEXT: psrld %xmm1, %xmm0311; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]312; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]313; SSE2-NEXT: movaps %xmm2, %xmm0314; SSE2-NEXT: retq315;316; SSE41-LABEL: combine_vec_udiv_by_shl_pow2a:317; SSE41: # %bb.0:318; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1319; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]320; SSE41-NEXT: movdqa %xmm0, %xmm3321; SSE41-NEXT: psrld %xmm2, %xmm3322; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]323; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]324; SSE41-NEXT: movdqa %xmm0, %xmm5325; SSE41-NEXT: psrld %xmm4, %xmm5326; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]327; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]328; SSE41-NEXT: movdqa %xmm0, %xmm3329; SSE41-NEXT: psrld %xmm1, %xmm3330; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]331; SSE41-NEXT: psrld %xmm1, %xmm0332; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]333; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]334; SSE41-NEXT: retq335;336; AVX1-LABEL: combine_vec_udiv_by_shl_pow2a:337; AVX1: # %bb.0:338; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1339; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero340; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2341; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3342; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3343; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]344; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3345; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]346; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3347; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero348; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0349; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]350; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]351; AVX1-NEXT: retq352;353; AVX2-LABEL: combine_vec_udiv_by_shl_pow2a:354; AVX2: # %bb.0:355; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2,2,2,2]356; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1357; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0358; AVX2-NEXT: retq359;360; XOP-LABEL: combine_vec_udiv_by_shl_pow2a:361; XOP: # %bb.0:362; XOP-NEXT: vbroadcastss {{.*#+}} xmm2 = [4294967294,4294967294,4294967294,4294967294]363; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1364; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm0365; XOP-NEXT: retq366 %1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y367 %2 = udiv <4 x i32> %x, %1368 ret <4 x i32> %2369}370 371define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {372; SSE2-LABEL: combine_vec_udiv_by_shl_pow2b:373; SSE2: # %bb.0:374; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1375; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]376; SSE2-NEXT: movdqa %xmm0, %xmm3377; SSE2-NEXT: psrld %xmm2, %xmm3378; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]379; SSE2-NEXT: movdqa %xmm0, %xmm2380; SSE2-NEXT: psrld %xmm4, %xmm2381; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]382; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]383; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]384; SSE2-NEXT: movdqa %xmm0, %xmm4385; SSE2-NEXT: psrld %xmm3, %xmm4386; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]387; SSE2-NEXT: psrld %xmm1, %xmm0388; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]389; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]390; SSE2-NEXT: movaps %xmm2, %xmm0391; SSE2-NEXT: retq392;393; SSE41-LABEL: combine_vec_udiv_by_shl_pow2b:394; SSE41: # %bb.0:395; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1396; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]397; SSE41-NEXT: movdqa %xmm0, %xmm3398; SSE41-NEXT: psrld %xmm2, %xmm3399; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]400; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]401; SSE41-NEXT: movdqa %xmm0, %xmm5402; SSE41-NEXT: psrld %xmm4, %xmm5403; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]404; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]405; SSE41-NEXT: movdqa %xmm0, %xmm3406; SSE41-NEXT: psrld %xmm1, %xmm3407; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]408; SSE41-NEXT: psrld %xmm1, %xmm0409; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]410; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]411; SSE41-NEXT: retq412;413; AVX1-LABEL: combine_vec_udiv_by_shl_pow2b:414; AVX1: # %bb.0:415; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2416; AVX1-NEXT: vpsrldq {{.*#+}} xmm3 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero417; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3418; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm4419; AVX1-NEXT: vpsrld %xmm4, %xmm0, %xmm4420; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5,6,7]421; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero422; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm1423; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4424; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm2[2],xmm4[2],xmm2[3],xmm4[3]425; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm0426; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]427; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5],xmm3[6,7]428; AVX1-NEXT: retq429;430; AVX2-LABEL: combine_vec_udiv_by_shl_pow2b:431; AVX2: # %bb.0:432; AVX2-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1433; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0434; AVX2-NEXT: retq435;436; XOP-LABEL: combine_vec_udiv_by_shl_pow2b:437; XOP: # %bb.0:438; XOP-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,4294967294,4294967293,4294967292]439; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1440; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm0441; XOP-NEXT: retq442 %1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y443 %2 = udiv <4 x i32> %x, %1444 ret <4 x i32> %2445}446 447; fold (udiv x, c1)448define i32 @combine_udiv_uniform(i32 %x) {449; CHECK-LABEL: combine_udiv_uniform:450; CHECK: # %bb.0:451; CHECK-NEXT: movl %edi, %ecx452; CHECK-NEXT: movl $2987803337, %eax # imm = 0xB21642C9453; CHECK-NEXT: imulq %rcx, %rax454; CHECK-NEXT: shrq $36, %rax455; CHECK-NEXT: # kill: def $eax killed $eax killed $rax456; CHECK-NEXT: retq457 %1 = udiv i32 %x, 23458 ret i32 %1459}460 461define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {462; SSE-LABEL: combine_vec_udiv_uniform:463; SSE: # %bb.0:464; SSE-NEXT: movdqa {{.*#+}} xmm1 = [25645,25645,25645,25645,25645,25645,25645,25645]465; SSE-NEXT: pmulhuw %xmm0, %xmm1466; SSE-NEXT: psubw %xmm1, %xmm0467; SSE-NEXT: psrlw $1, %xmm0468; SSE-NEXT: paddw %xmm1, %xmm0469; SSE-NEXT: psrlw $4, %xmm0470; SSE-NEXT: retq471;472; AVX-LABEL: combine_vec_udiv_uniform:473; AVX: # %bb.0:474; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [25645,25645,25645,25645,25645,25645,25645,25645]475; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0476; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0477; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0478; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0479; AVX-NEXT: retq480;481; XOP-LABEL: combine_vec_udiv_uniform:482; XOP: # %bb.0:483; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [25645,25645,25645,25645,25645,25645,25645,25645]484; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0485; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0486; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0487; XOP-NEXT: vpsrlw $4, %xmm0, %xmm0488; XOP-NEXT: retq489 %1 = udiv <8 x i16> %x, <i16 23, i16 23, i16 23, i16 23, i16 23, i16 23, i16 23, i16 23>490 ret <8 x i16> %1491}492 493define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {494; SSE2-LABEL: combine_vec_udiv_nonuniform:495; SSE2: # %bb.0:496; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,65535,65535,65535,65535]497; SSE2-NEXT: movdqa %xmm0, %xmm2498; SSE2-NEXT: pand %xmm1, %xmm2499; SSE2-NEXT: movdqa %xmm0, %xmm3500; SSE2-NEXT: psrlw $3, %xmm3501; SSE2-NEXT: pandn %xmm3, %xmm1502; SSE2-NEXT: por %xmm2, %xmm1503; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]504; SSE2-NEXT: psubw %xmm1, %xmm0505; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [32768,0,0,0]506; SSE2-NEXT: paddw %xmm1, %xmm0507; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,0,65535,65535,0]508; SSE2-NEXT: pandn %xmm0, %xmm1509; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [0,16,0,8,8,0,0,0,0,0,2,0,2,0,0,0]510; SSE2-NEXT: por %xmm1, %xmm0511; SSE2-NEXT: retq512;513; SSE41-LABEL: combine_vec_udiv_nonuniform:514; SSE41: # %bb.0:515; SSE41-NEXT: movdqa %xmm0, %xmm1516; SSE41-NEXT: psrlw $3, %xmm1517; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]518; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]519; SSE41-NEXT: psubw %xmm1, %xmm0520; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [32768,0,0,0]521; SSE41-NEXT: paddw %xmm1, %xmm0522; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4096,2048,8,u,u,2,2,u]523; SSE41-NEXT: pmulhuw %xmm0, %xmm1524; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]525; SSE41-NEXT: retq526;527; AVX-LABEL: combine_vec_udiv_nonuniform:528; AVX: # %bb.0:529; AVX-NEXT: vpsrlw $3, %xmm0, %xmm1530; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]531; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]532; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0533; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [32768,0,0,0]534; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0535; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [4096,2048,8,u,u,2,2,u]536; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]537; AVX-NEXT: retq538;539; XOP-LABEL: combine_vec_udiv_nonuniform:540; XOP: # %bb.0:541; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1542; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]543; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0544; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [32768,0,0,0]545; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0546; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0547; XOP-NEXT: retq548 %1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768>549 ret <8 x i16> %1550}551 552define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {553; SSE2-LABEL: combine_vec_udiv_nonuniform2:554; SSE2: # %bb.0:555; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]556; SSE2-NEXT: movdqa %xmm0, %xmm2557; SSE2-NEXT: pand %xmm1, %xmm2558; SSE2-NEXT: psrlw $1, %xmm0559; SSE2-NEXT: pandn %xmm0, %xmm1560; SSE2-NEXT: por %xmm2, %xmm1561; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [16393,59919,58255,32787,55189,8197,52429,32789]562; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [8,2048,2048,2,2048,8,2048,2]563; SSE2-NEXT: movdqa %xmm1, %xmm0564; SSE2-NEXT: retq565;566; SSE41-LABEL: combine_vec_udiv_nonuniform2:567; SSE41: # %bb.0:568; SSE41-NEXT: movdqa %xmm0, %xmm1569; SSE41-NEXT: psrlw $1, %xmm1570; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]571; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16393,59919,58255,32787,55189,8197,52429,32789]572; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [8,2048,2048,2,2048,8,2048,2]573; SSE41-NEXT: retq574;575; AVX-LABEL: combine_vec_udiv_nonuniform2:576; AVX: # %bb.0:577; AVX-NEXT: vpsrlw $1, %xmm0, %xmm1578; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]579; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [16393,59919,58255,32787,55189,8197,52429,32789]580; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [8,2048,2048,2,2048,8,2048,2]581; AVX-NEXT: retq582;583; XOP-LABEL: combine_vec_udiv_nonuniform2:584; XOP: # %bb.0:585; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0586; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [16393,59919,58255,32787,55189,8197,52429,32789]587; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0588; XOP-NEXT: retq589 %1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>590 ret <8 x i16> %1591}592 593define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {594; SSE-LABEL: combine_vec_udiv_nonuniform3:595; SSE: # %bb.0:596; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9363,25645,18351,12137,2115,23705,1041,517]597; SSE-NEXT: pmulhuw %xmm0, %xmm1598; SSE-NEXT: psubw %xmm1, %xmm0599; SSE-NEXT: psrlw $1, %xmm0600; SSE-NEXT: paddw %xmm1, %xmm0601; SSE-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16384,4096,4096,4096,4096,2048,2048,1024]602; SSE-NEXT: retq603;604; AVX-LABEL: combine_vec_udiv_nonuniform3:605; AVX: # %bb.0:606; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [9363,25645,18351,12137,2115,23705,1041,517]607; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0608; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0609; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0610; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [16384,4096,4096,4096,4096,2048,2048,1024]611; AVX-NEXT: retq612;613; XOP-LABEL: combine_vec_udiv_nonuniform3:614; XOP: # %bb.0:615; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [9363,25645,18351,12137,2115,23705,1041,517]616; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0617; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0618; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0619; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0620; XOP-NEXT: retq621 %1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127>622 ret <8 x i16> %1623}624 625define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {626; SSE2-LABEL: combine_vec_udiv_nonuniform4:627; SSE2: # %bb.0:628; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]629; SSE2-NEXT: movdqa %xmm0, %xmm2630; SSE2-NEXT: pand %xmm1, %xmm2631; SSE2-NEXT: pxor %xmm3, %xmm3632; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]633; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [171,0,0,0]634; SSE2-NEXT: psrlw $15, %xmm0635; SSE2-NEXT: pandn %xmm0, %xmm1636; SSE2-NEXT: por %xmm2, %xmm1637; SSE2-NEXT: movdqa %xmm1, %xmm0638; SSE2-NEXT: retq639;640; SSE41-LABEL: combine_vec_udiv_nonuniform4:641; SSE41: # %bb.0:642; SSE41-NEXT: movdqa %xmm0, %xmm1643; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero644; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [171,0,0,0]645; SSE41-NEXT: psrlw $8, %xmm2646; SSE41-NEXT: packuswb %xmm2, %xmm2647; SSE41-NEXT: psrlw $7, %xmm2648; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2649; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]650; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2651; SSE41-NEXT: movdqa %xmm2, %xmm0652; SSE41-NEXT: retq653;654; AVX-LABEL: combine_vec_udiv_nonuniform4:655; AVX: # %bb.0:656; AVX-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero657; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [171,0,0,0]658; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1659; AVX-NEXT: vpackuswb %xmm1, %xmm1, %xmm1660; AVX-NEXT: vpsrlw $7, %xmm1, %xmm1661; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1662; AVX-NEXT: vpmovsxwq {{.*#+}} xmm2 = [18446744073709551360,18446744073709551615]663; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0664; AVX-NEXT: retq665;666; XOP-LABEL: combine_vec_udiv_nonuniform4:667; XOP: # %bb.0:668; XOP-NEXT: movl $249, %eax669; XOP-NEXT: vmovd %eax, %xmm1670; XOP-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero671; XOP-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [171,0,0,0]672; XOP-NEXT: vpsrlw $8, %xmm2, %xmm2673; XOP-NEXT: vpshlb %xmm1, %xmm2, %xmm1674; XOP-NEXT: vpmovsxwq {{.*#+}} xmm2 = [18446744073709551360,18446744073709551615]675; XOP-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0676; XOP-NEXT: retq677 %div = udiv <16 x i8> %x, <i8 -64, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>678 ret <16 x i8> %div679}680 681define <8 x i16> @pr38477(<8 x i16> %a0) {682; SSE2-LABEL: pr38477:683; SSE2: # %bb.0:684; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]685; SSE2-NEXT: movdqa %xmm1, %xmm2686; SSE2-NEXT: pandn %xmm0, %xmm2687; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [u,4957,57457,4103,16385,35545,2048,2115]688; SSE2-NEXT: pmulhuw %xmm0, %xmm3689; SSE2-NEXT: psubw %xmm3, %xmm0690; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [u,32768,0,0,0,0,0,32768]691; SSE2-NEXT: paddw %xmm3, %xmm0692; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [u,u,0,4,0,4,16,0,4,0,0,4,0,0,0,16]693; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3694; SSE2-NEXT: por %xmm3, %xmm0695; SSE2-NEXT: pand %xmm1, %xmm0696; SSE2-NEXT: por %xmm2, %xmm0697; SSE2-NEXT: retq698;699; SSE41-LABEL: pr38477:700; SSE41: # %bb.0:701; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [u,4957,57457,4103,16385,35545,2048,2115]702; SSE41-NEXT: pmulhuw %xmm0, %xmm1703; SSE41-NEXT: movdqa %xmm0, %xmm2704; SSE41-NEXT: psubw %xmm1, %xmm2705; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [u,32768,0,0,0,0,0,32768]706; SSE41-NEXT: paddw %xmm1, %xmm2707; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [u,1024,1024,16,4,1024,u,4096]708; SSE41-NEXT: pmulhuw %xmm2, %xmm1709; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6],xmm1[7]710; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]711; SSE41-NEXT: retq712;713; AVX-LABEL: pr38477:714; AVX: # %bb.0:715; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,4957,57457,4103,16385,35545,2048,2115]716; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm2717; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,32768,0,0,0,0,0,32768]718; AVX-NEXT: vpaddw %xmm1, %xmm2, %xmm1719; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [u,1024,1024,16,4,1024,u,4096]720; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5],xmm1[6],xmm2[7]721; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]722; AVX-NEXT: retq723;724; XOP-LABEL: pr38477:725; XOP: # %bb.0:726; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,4957,57457,4103,16385,35545,2048,2115]727; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm2728; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,32768,0,0,0,0,0,32768]729; XOP-NEXT: vpaddw %xmm1, %xmm2, %xmm1730; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1731; XOP-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]732; XOP-NEXT: retq733 %1 = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31>734 ret <8 x i16> %1735}736 737define i1 @bool_udiv(i1 %x, i1 %y) {738; CHECK-LABEL: bool_udiv:739; CHECK: # %bb.0:740; CHECK-NEXT: movl %edi, %eax741; CHECK-NEXT: # kill: def $al killed $al killed $eax742; CHECK-NEXT: retq743 %r = udiv i1 %x, %y744 ret i1 %r745}746 747define <4 x i1> @boolvec_udiv(<4 x i1> %x, <4 x i1> %y) {748; CHECK-LABEL: boolvec_udiv:749; CHECK: # %bb.0:750; CHECK-NEXT: retq751 %r = udiv <4 x i1> %x, %y752 ret <4 x i1> %r753}754 755define <4 x i32> @vector_div_leading_zeros(<4 x i32> %x) {756; SSE2-LABEL: vector_div_leading_zeros:757; SSE2: # %bb.0:758; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0759; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [613566757,613566757,613566757,613566757]760; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]761; SSE2-NEXT: pmuludq %xmm1, %xmm0762; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]763; SSE2-NEXT: pmuludq %xmm1, %xmm2764; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]765; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]766; SSE2-NEXT: retq767;768; SSE41-LABEL: vector_div_leading_zeros:769; SSE41: # %bb.0:770; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0771; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]772; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]773; SSE41-NEXT: pmuludq %xmm2, %xmm1774; SSE41-NEXT: pmuludq %xmm2, %xmm0775; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]776; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]777; SSE41-NEXT: retq778;779; AVX1-LABEL: vector_div_leading_zeros:780; AVX1: # %bb.0:781; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0782; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]783; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]784; AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1785; AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm0786; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]787; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]788; AVX1-NEXT: retq789;790; AVX2-LABEL: vector_div_leading_zeros:791; AVX2: # %bb.0:792; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0793; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]794; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]795; AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1796; AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm0797; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]798; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]799; AVX2-NEXT: retq800;801; XOP-LABEL: vector_div_leading_zeros:802; XOP: # %bb.0:803; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0804; XOP-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]805; XOP-NEXT: vbroadcastss {{.*#+}} xmm2 = [613566757,613566757,613566757,613566757]806; XOP-NEXT: vpmuludq %xmm2, %xmm1, %xmm1807; XOP-NEXT: vpmuludq %xmm2, %xmm0, %xmm0808; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]809; XOP-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]810; XOP-NEXT: retq811 %a = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>812 %b = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>813 ret <4 x i32> %b814}815