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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX14; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX25 6; fold (urem x, 1) -> 07define i32 @combine_urem_by_one(i32 %x) {8; CHECK-LABEL: combine_urem_by_one:9; CHECK: # %bb.0:10; CHECK-NEXT: xorl %eax, %eax11; CHECK-NEXT: retq12 %1 = urem i32 %x, 113 ret i32 %114}15 16define <4 x i32> @combine_vec_urem_by_one(<4 x i32> %x) {17; SSE-LABEL: combine_vec_urem_by_one:18; SSE: # %bb.0:19; SSE-NEXT: xorps %xmm0, %xmm020; SSE-NEXT: retq21;22; AVX-LABEL: combine_vec_urem_by_one:23; AVX: # %bb.0:24; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm025; AVX-NEXT: retq26 %1 = urem <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>27 ret <4 x i32> %128}29 30; fold (urem x, -1) -> select((icmp eq x, -1), 0, x)31define i32 @combine_urem_by_negone(i32 %x) {32; CHECK-LABEL: combine_urem_by_negone:33; CHECK: # %bb.0:34; CHECK-NEXT: xorl %eax, %eax35; CHECK-NEXT: cmpl $-1, %edi36; CHECK-NEXT: cmovnel %edi, %eax37; CHECK-NEXT: retq38 %1 = urem i32 %x, -139 ret i32 %140}41 42define <4 x i32> @combine_vec_urem_by_negone(<4 x i32> %x) {43; SSE-LABEL: combine_vec_urem_by_negone:44; SSE: # %bb.0:45; SSE-NEXT: pcmpeqd %xmm1, %xmm146; SSE-NEXT: pcmpeqd %xmm0, %xmm147; SSE-NEXT: pandn %xmm0, %xmm148; SSE-NEXT: movdqa %xmm1, %xmm049; SSE-NEXT: retq50;51; AVX-LABEL: combine_vec_urem_by_negone:52; AVX: # %bb.0:53; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm154; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm155; AVX-NEXT: vpandn %xmm0, %xmm1, %xmm056; AVX-NEXT: retq57 %1 = urem <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>58 ret <4 x i32> %159}60 61; Use PSLLI intrinsic to postpone the undef creation until after urem-by-constant expansion62 63define <4 x i32> @combine_vec_urem_undef_by_negone(<4 x i32> %in) {64; SSE-LABEL: combine_vec_urem_undef_by_negone:65; SSE: # %bb.0:66; SSE-NEXT: pcmpeqd %xmm0, %xmm067; SSE-NEXT: pcmpeqd %xmm0, %xmm068; SSE-NEXT: pandn %xmm0, %xmm069; SSE-NEXT: retq70;71; AVX-LABEL: combine_vec_urem_undef_by_negone:72; AVX: # %bb.0:73; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm074; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm075; AVX-NEXT: vpandn %xmm0, %xmm0, %xmm076; AVX-NEXT: retq77 %x = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 0)78 %y = urem <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>79 ret <4 x i32> %y80}81 82; fold (urem x, INT_MIN) -> (and x, ~INT_MIN)83define i32 @combine_urem_by_minsigned(i32 %x) {84; CHECK-LABEL: combine_urem_by_minsigned:85; CHECK: # %bb.0:86; CHECK-NEXT: movl %edi, %eax87; CHECK-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF88; CHECK-NEXT: retq89 %1 = urem i32 %x, -214748364890 ret i32 %191}92 93define <4 x i32> @combine_vec_urem_by_minsigned(<4 x i32> %x) {94; SSE-LABEL: combine_vec_urem_by_minsigned:95; SSE: # %bb.0:96; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm097; SSE-NEXT: retq98;99; AVX1-LABEL: combine_vec_urem_by_minsigned:100; AVX1: # %bb.0:101; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0102; AVX1-NEXT: retq103;104; AVX2-LABEL: combine_vec_urem_by_minsigned:105; AVX2: # %bb.0:106; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647]107; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0108; AVX2-NEXT: retq109 %1 = urem <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>110 ret <4 x i32> %1111}112 113; fold (urem 0, x) -> 0114define i32 @combine_urem_zero(i32 %x) {115; CHECK-LABEL: combine_urem_zero:116; CHECK: # %bb.0:117; CHECK-NEXT: xorl %eax, %eax118; CHECK-NEXT: retq119 %1 = urem i32 0, %x120 ret i32 %1121}122 123define <4 x i32> @combine_vec_urem_zero(<4 x i32> %x) {124; SSE-LABEL: combine_vec_urem_zero:125; SSE: # %bb.0:126; SSE-NEXT: xorps %xmm0, %xmm0127; SSE-NEXT: retq128;129; AVX-LABEL: combine_vec_urem_zero:130; AVX: # %bb.0:131; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0132; AVX-NEXT: retq133 %1 = urem <4 x i32> zeroinitializer, %x134 ret <4 x i32> %1135}136 137; fold (urem x, x) -> 0138define i32 @combine_urem_dupe(i32 %x) {139; CHECK-LABEL: combine_urem_dupe:140; CHECK: # %bb.0:141; CHECK-NEXT: xorl %eax, %eax142; CHECK-NEXT: retq143 %1 = urem i32 %x, %x144 ret i32 %1145}146 147define <4 x i32> @combine_vec_urem_dupe(<4 x i32> %x) {148; SSE-LABEL: combine_vec_urem_dupe:149; SSE: # %bb.0:150; SSE-NEXT: xorps %xmm0, %xmm0151; SSE-NEXT: retq152;153; AVX-LABEL: combine_vec_urem_dupe:154; AVX: # %bb.0:155; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0156; AVX-NEXT: retq157 %1 = urem <4 x i32> %x, %x158 ret <4 x i32> %1159}160 161; fold (urem x, pow2) -> (and x, (pow2-1))162define <4 x i32> @combine_vec_urem_by_pow2a(<4 x i32> %x) {163; SSE-LABEL: combine_vec_urem_by_pow2a:164; SSE: # %bb.0:165; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0166; SSE-NEXT: retq167;168; AVX1-LABEL: combine_vec_urem_by_pow2a:169; AVX1: # %bb.0:170; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0171; AVX1-NEXT: retq172;173; AVX2-LABEL: combine_vec_urem_by_pow2a:174; AVX2: # %bb.0:175; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [3,3,3,3]176; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0177; AVX2-NEXT: retq178 %1 = urem <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>179 ret <4 x i32> %1180}181 182define <4 x i32> @combine_vec_urem_by_pow2b(<4 x i32> %x) {183; SSE-LABEL: combine_vec_urem_by_pow2b:184; SSE: # %bb.0:185; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0186; SSE-NEXT: retq187;188; AVX-LABEL: combine_vec_urem_by_pow2b:189; AVX: # %bb.0:190; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0191; AVX-NEXT: retq192 %1 = urem <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>193 ret <4 x i32> %1194}195 196define <4 x i32> @combine_vec_urem_by_pow2c(<4 x i32> %x, <4 x i32> %y) {197; SSE-LABEL: combine_vec_urem_by_pow2c:198; SSE: # %bb.0:199; SSE-NEXT: pslld $23, %xmm1200; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1201; SSE-NEXT: cvttps2dq %xmm1, %xmm1202; SSE-NEXT: pcmpeqd %xmm2, %xmm2203; SSE-NEXT: paddd %xmm1, %xmm2204; SSE-NEXT: pand %xmm2, %xmm0205; SSE-NEXT: retq206;207; AVX1-LABEL: combine_vec_urem_by_pow2c:208; AVX1: # %bb.0:209; AVX1-NEXT: vpslld $23, %xmm1, %xmm1210; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1211; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1212; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2213; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1214; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0215; AVX1-NEXT: retq216;217; AVX2-LABEL: combine_vec_urem_by_pow2c:218; AVX2: # %bb.0:219; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]220; AVX2-NEXT: vpsllvd %xmm1, %xmm2, %xmm1221; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2222; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1223; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0224; AVX2-NEXT: retq225 %1 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y226 %2 = urem <4 x i32> %x, %1227 ret <4 x i32> %2228}229 230define <4 x i32> @combine_vec_urem_by_pow2d(<4 x i32> %x, <4 x i32> %y) {231; SSE-LABEL: combine_vec_urem_by_pow2d:232; SSE: # %bb.0:233; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]234; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]235; SSE-NEXT: movdqa %xmm3, %xmm4236; SSE-NEXT: psrld %xmm2, %xmm4237; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]238; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm2[2,3,3,3,4,5,6,7]239; SSE-NEXT: movdqa %xmm3, %xmm6240; SSE-NEXT: psrld %xmm5, %xmm6241; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm4[0,1,2,3],xmm6[4,5,6,7]242; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]243; SSE-NEXT: movdqa %xmm3, %xmm4244; SSE-NEXT: psrld %xmm1, %xmm4245; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]246; SSE-NEXT: psrld %xmm1, %xmm3247; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5,6,7]248; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm6[2,3],xmm3[4,5],xmm6[6,7]249; SSE-NEXT: pcmpeqd %xmm1, %xmm1250; SSE-NEXT: paddd %xmm3, %xmm1251; SSE-NEXT: pand %xmm1, %xmm0252; SSE-NEXT: retq253;254; AVX1-LABEL: combine_vec_urem_by_pow2d:255; AVX1: # %bb.0:256; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero257; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]258; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2259; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm4260; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4261; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]262; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4263; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]264; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4265; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero266; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1267; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]268; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]269; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2270; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1271; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0272; AVX1-NEXT: retq273;274; AVX2-LABEL: combine_vec_urem_by_pow2d:275; AVX2: # %bb.0:276; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]277; AVX2-NEXT: vpsrlvd %xmm1, %xmm2, %xmm1278; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2279; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1280; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0281; AVX2-NEXT: retq282 %1 = lshr <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %y283 %2 = urem <4 x i32> %x, %1284 ret <4 x i32> %2285}286 287; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))288define <4 x i32> @combine_vec_urem_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {289; SSE-LABEL: combine_vec_urem_by_shl_pow2a:290; SSE: # %bb.0:291; SSE-NEXT: pslld $23, %xmm1292; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1293; SSE-NEXT: cvttps2dq %xmm1, %xmm1294; SSE-NEXT: pslld $2, %xmm1295; SSE-NEXT: pcmpeqd %xmm2, %xmm2296; SSE-NEXT: paddd %xmm1, %xmm2297; SSE-NEXT: pand %xmm2, %xmm0298; SSE-NEXT: retq299;300; AVX1-LABEL: combine_vec_urem_by_shl_pow2a:301; AVX1: # %bb.0:302; AVX1-NEXT: vpslld $23, %xmm1, %xmm1303; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1304; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1305; AVX1-NEXT: vpslld $2, %xmm1, %xmm1306; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2307; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1308; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0309; AVX1-NEXT: retq310;311; AVX2-LABEL: combine_vec_urem_by_shl_pow2a:312; AVX2: # %bb.0:313; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4,4,4,4]314; AVX2-NEXT: vpsllvd %xmm1, %xmm2, %xmm1315; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2316; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1317; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0318; AVX2-NEXT: retq319 %1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y320 %2 = urem <4 x i32> %x, %1321 ret <4 x i32> %2322}323 324define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {325; SSE-LABEL: combine_vec_urem_by_shl_pow2b:326; SSE: # %bb.0:327; SSE-NEXT: pslld $23, %xmm1328; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1329; SSE-NEXT: cvttps2dq %xmm1, %xmm1330; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1,4,8,16]331; SSE-NEXT: pcmpeqd %xmm2, %xmm2332; SSE-NEXT: paddd %xmm1, %xmm2333; SSE-NEXT: pand %xmm2, %xmm0334; SSE-NEXT: retq335;336; AVX1-LABEL: combine_vec_urem_by_shl_pow2b:337; AVX1: # %bb.0:338; AVX1-NEXT: vpslld $23, %xmm1, %xmm1339; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1340; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1341; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,4,8,16]342; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2343; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1344; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0345; AVX1-NEXT: retq346;347; AVX2-LABEL: combine_vec_urem_by_shl_pow2b:348; AVX2: # %bb.0:349; AVX2-NEXT: vpmovsxbd {{.*#+}} xmm2 = [1,4,8,16]350; AVX2-NEXT: vpsllvd %xmm1, %xmm2, %xmm1351; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2352; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1353; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0354; AVX2-NEXT: retq355 %1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y356 %2 = urem <4 x i32> %x, %1357 ret <4 x i32> %2358}359 360; fold (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1))361define <4 x i32> @combine_vec_urem_by_lshr_pow2a(<4 x i32> %x, <4 x i32> %y) {362; SSE-LABEL: combine_vec_urem_by_lshr_pow2a:363; SSE: # %bb.0:364; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]365; SSE-NEXT: pmovsxbd {{.*#+}} xmm3 = [4,4,4,4]366; SSE-NEXT: movdqa %xmm3, %xmm4367; SSE-NEXT: psrld %xmm2, %xmm4368; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]369; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm2[2,3,3,3,4,5,6,7]370; SSE-NEXT: movdqa %xmm3, %xmm6371; SSE-NEXT: psrld %xmm5, %xmm6372; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm4[0,1,2,3],xmm6[4,5,6,7]373; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]374; SSE-NEXT: movdqa %xmm3, %xmm4375; SSE-NEXT: psrld %xmm1, %xmm4376; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]377; SSE-NEXT: psrld %xmm1, %xmm3378; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5,6,7]379; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm6[2,3],xmm3[4,5],xmm6[6,7]380; SSE-NEXT: pcmpeqd %xmm1, %xmm1381; SSE-NEXT: paddd %xmm3, %xmm1382; SSE-NEXT: pand %xmm1, %xmm0383; SSE-NEXT: retq384;385; AVX1-LABEL: combine_vec_urem_by_lshr_pow2a:386; AVX1: # %bb.0:387; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero388; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [4,4,4,4]389; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2390; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm4391; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4392; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]393; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4394; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]395; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4396; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero397; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1398; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]399; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]400; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2401; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1402; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0403; AVX1-NEXT: retq404;405; AVX2-LABEL: combine_vec_urem_by_lshr_pow2a:406; AVX2: # %bb.0:407; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4,4,4,4]408; AVX2-NEXT: vpsrlvd %xmm1, %xmm2, %xmm1409; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2410; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1411; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0412; AVX2-NEXT: retq413 %1 = lshr <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y414 %2 = urem <4 x i32> %x, %1415 ret <4 x i32> %2416}417 418define <4 x i32> @combine_vec_urem_by_lshr_pow2b(<4 x i32> %x, <4 x i32> %y) {419; SSE-LABEL: combine_vec_urem_by_lshr_pow2b:420; SSE: # %bb.0:421; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]422; SSE-NEXT: pmovsxbd {{.*#+}} xmm3 = [1,4,8,16]423; SSE-NEXT: movdqa %xmm3, %xmm4424; SSE-NEXT: psrld %xmm2, %xmm4425; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]426; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm2[2,3,3,3,4,5,6,7]427; SSE-NEXT: movdqa %xmm3, %xmm6428; SSE-NEXT: psrld %xmm5, %xmm6429; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm4[0,1,2,3],xmm6[4,5,6,7]430; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]431; SSE-NEXT: movdqa %xmm3, %xmm4432; SSE-NEXT: psrld %xmm1, %xmm4433; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]434; SSE-NEXT: psrld %xmm1, %xmm3435; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5,6,7]436; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm6[2,3],xmm3[4,5],xmm6[6,7]437; SSE-NEXT: pcmpeqd %xmm1, %xmm1438; SSE-NEXT: paddd %xmm3, %xmm1439; SSE-NEXT: pand %xmm1, %xmm0440; SSE-NEXT: retq441;442; AVX1-LABEL: combine_vec_urem_by_lshr_pow2b:443; AVX1: # %bb.0:444; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero445; AVX1-NEXT: vpmovsxbd {{.*#+}} xmm3 = [1,4,8,16]446; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2447; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm4448; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4449; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]450; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4451; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]452; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4453; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero454; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1455; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]456; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]457; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2458; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1459; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0460; AVX1-NEXT: retq461;462; AVX2-LABEL: combine_vec_urem_by_lshr_pow2b:463; AVX2: # %bb.0:464; AVX2-NEXT: vpmovsxbd {{.*#+}} xmm2 = [1,4,8,16]465; AVX2-NEXT: vpsrlvd %xmm1, %xmm2, %xmm1466; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2467; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1468; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0469; AVX2-NEXT: retq470 %1 = lshr <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y471 %2 = urem <4 x i32> %x, %1472 ret <4 x i32> %2473}474 475; FIXME: PR55271 - urem(undef, 3) != undef476; Use PSLLI intrinsic to postpone the undef creation until after urem-by-constant expansion477define <4 x i32> @combine_vec_urem_undef_by_3(<4 x i32> %in) {478; CHECK-LABEL: combine_vec_urem_undef_by_3:479; CHECK: # %bb.0:480; CHECK-NEXT: retq481 %x = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 0)482 %y = urem <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>483 ret <4 x i32> %y484}485declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)486 487define i1 @bool_urem(i1 %x, i1 %y) {488; CHECK-LABEL: bool_urem:489; CHECK: # %bb.0:490; CHECK-NEXT: xorl %eax, %eax491; CHECK-NEXT: retq492 %r = urem i1 %x, %y493 ret i1 %r494}495 496define <4 x i1> @boolvec_urem(<4 x i1> %x, <4 x i1> %y) {497; SSE-LABEL: boolvec_urem:498; SSE: # %bb.0:499; SSE-NEXT: xorps %xmm0, %xmm0500; SSE-NEXT: retq501;502; AVX-LABEL: boolvec_urem:503; AVX: # %bb.0:504; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0505; AVX-NEXT: retq506 %r = urem <4 x i1> %x, %y507 ret <4 x i1> %r508}509