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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+sse2,+pclmul | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+avx2,+pclmul | FileCheck %s --check-prefix=AVX4; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+avx512vl,+vpclmulqdq | FileCheck %s --check-prefix=AVX5 6declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone7 8define <2 x i64> @commute_lq_lq(ptr %a0, <2 x i64> %a1) #0 {9; SSE-LABEL: commute_lq_lq:10; SSE: # %bb.0:11; SSE-NEXT: pclmulqdq $0, (%rdi), %xmm012; SSE-NEXT: retq13;14; AVX-LABEL: commute_lq_lq:15; AVX: # %bb.0:16; AVX-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm017; AVX-NEXT: retq18 %1 = load <2 x i64>, ptr %a019 %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 0)20 ret <2 x i64> %221}22 23define <2 x i64> @commute_lq_hq(ptr %a0, <2 x i64> %a1) #0 {24; SSE-LABEL: commute_lq_hq:25; SSE: # %bb.0:26; SSE-NEXT: pclmulqdq $1, (%rdi), %xmm027; SSE-NEXT: retq28;29; AVX-LABEL: commute_lq_hq:30; AVX: # %bb.0:31; AVX-NEXT: vpclmulqdq $1, (%rdi), %xmm0, %xmm032; AVX-NEXT: retq33 %1 = load <2 x i64>, ptr %a034 %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 16)35 ret <2 x i64> %236}37 38define <2 x i64> @commute_hq_lq(ptr %a0, <2 x i64> %a1) #0 {39; SSE-LABEL: commute_hq_lq:40; SSE: # %bb.0:41; SSE-NEXT: pclmulqdq $16, (%rdi), %xmm042; SSE-NEXT: retq43;44; AVX-LABEL: commute_hq_lq:45; AVX: # %bb.0:46; AVX-NEXT: vpclmulqdq $16, (%rdi), %xmm0, %xmm047; AVX-NEXT: retq48 %1 = load <2 x i64>, ptr %a049 %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 1)50 ret <2 x i64> %251}52 53define <2 x i64> @commute_hq_hq(ptr %a0, <2 x i64> %a1) #0 {54; SSE-LABEL: commute_hq_hq:55; SSE: # %bb.0:56; SSE-NEXT: pclmulqdq $17, (%rdi), %xmm057; SSE-NEXT: retq58;59; AVX-LABEL: commute_hq_hq:60; AVX: # %bb.0:61; AVX-NEXT: vpclmulqdq $17, (%rdi), %xmm0, %xmm062; AVX-NEXT: retq63 %1 = load <2 x i64>, ptr %a064 %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 17)65 ret <2 x i64> %266}67