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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+vpclmulqdq | FileCheck %s3; FIXME: actual vpclmulqdq operation should be eliminated4 5declare <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64>, <4 x i64>, i8) nounwind readnone6 7define <4 x i64> @commute_v1(<4 x i64> %a0, <4 x i64> %a1) {8; CHECK-LABEL: commute_v1:9; CHECK: # %bb.0:10; CHECK-NEXT: vpclmulqdq $0, %ymm1, %ymm0, %ymm011; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm012; CHECK-NEXT: retq13 %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 0)14 %2 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a1, <4 x i64> %a0, i8 0)15 %3 = xor <4 x i64> %1, %216 ret <4 x i64> %317}18 19define <4 x i64> @commute_v2(<4 x i64> %a0, <4 x i64> %a1) {20; CHECK-LABEL: commute_v2:21; CHECK: # %bb.0:22; CHECK-NEXT: vpclmulqdq $16, %ymm1, %ymm0, %ymm023; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm024; CHECK-NEXT: retq25 %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 16)26 %2 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a1, <4 x i64> %a0, i8 1)27 %3 = xor <4 x i64> %2, %128 ret <4 x i64> %329}30 31define <4 x i64> @commute_v3(<4 x i64> %a0, <4 x i64> %a1) {32; CHECK-LABEL: commute_v3:33; CHECK: # %bb.0:34; CHECK-NEXT: vpclmulqdq $17, %ymm1, %ymm0, %ymm035; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm036; CHECK-NEXT: retq37 %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 17)38 %2 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a1, <4 x i64> %a0, i8 17)39 %3 = xor <4 x i64> %2, %140 ret <4 x i64> %341}42 43