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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O0 -relocation-model=pic -frame-pointer=all < %s | FileCheck %s3target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"4target triple = "x86_64-apple-darwin10"5 6; This file contains functions that may crash llc -O07 8; The DIV8 instruction produces results in AH and AL, but we don't want to use9; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for10; aliased registers (AX and AL) - RegAllocFast does not like that.11; PR731212define i32 @div8() nounwind {13; CHECK-LABEL: div8:14; CHECK: ## %bb.0: ## %entry15; CHECK-NEXT: pushq %rbp16; CHECK-NEXT: movq %rsp, %rbp17; CHECK-NEXT: ## implicit-def: $rax18; CHECK-NEXT: movb %al, %cl19; CHECK-NEXT: xorl %eax, %eax20; CHECK-NEXT: ## kill: def $al killed $al killed $eax21; CHECK-NEXT: movzbw %al, %ax22; CHECK-NEXT: divb %cl23; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill24; CHECK-NEXT: xorl %eax, %eax25; CHECK-NEXT: ## kill: def $al killed $al killed $eax26; CHECK-NEXT: movzbw %al, %ax27; CHECK-NEXT: divb %cl28; CHECK-NEXT: shrw $8, %ax29; CHECK-NEXT: ## kill: def $al killed $al killed $ax30; CHECK-NEXT: cmpb %cl, %al31; CHECK-NEXT: jae LBB0_232; CHECK-NEXT: ## %bb.1: ## %"39"33; CHECK-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload34; CHECK-NEXT: movzbl %al, %eax35; CHECK-NEXT: ## implicit-def: $ecx36; CHECK-NEXT: imull %ecx, %eax37; CHECK-NEXT: ## implicit-def: $ecx38; CHECK-NEXT: addl %ecx, %eax39; CHECK-NEXT: ## implicit-def: $ecx40; CHECK-NEXT: cmpl %ecx, %eax41; CHECK-NEXT: je LBB0_342; CHECK-NEXT: LBB0_2: ## %"40"43; CHECK-NEXT: ud244; CHECK-NEXT: LBB0_3: ## %"41"45; CHECK-NEXT: ud246entry:47 %0 = trunc i64 undef to i8 ; <i8> [#uses=3]48 %1 = udiv i8 0, %0 ; <i8> [#uses=1]49 %2 = urem i8 0, %0 ; <i8> [#uses=1]50 %3 = icmp uge i8 %2, %0 ; <i1> [#uses=1]51 br i1 %3, label %"40", label %"39"52 53"39": ; preds = %"36"54 %4 = zext i8 %1 to i32 ; <i32> [#uses=1]55 %5 = mul nsw i32 %4, undef ; <i32> [#uses=1]56 %6 = add nsw i32 %5, undef ; <i32> [#uses=1]57 %7 = icmp ne i32 %6, undef ; <i1> [#uses=1]58 br i1 %7, label %"40", label %"41"59 60"40": ; preds = %"39", %"36"61 unreachable62 63"41": ; preds = %"39"64 unreachable65}66 67; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64.68; CQO defines implicitly AX and DIV64 uses it implicitly too.69; When an instruction gets between those two, RegAllocFast was reusing70; AX for the vreg defined in between and the compiler crashed.71;72; An instruction gets between CQO and DIV64 because the load is folded73; into the division but it requires a sign extension.74; PR2170075define i64 @addressModeWith32bitIndex(i32 %V) {76; CHECK-LABEL: addressModeWith32bitIndex:77; CHECK: ## %bb.0:78; CHECK-NEXT: pushq %rbp79; CHECK-NEXT: .cfi_def_cfa_offset 1680; CHECK-NEXT: .cfi_offset %rbp, -1681; CHECK-NEXT: movq %rsp, %rbp82; CHECK-NEXT: .cfi_def_cfa_register %rbp83; CHECK-NEXT: xorl %eax, %eax84; CHECK-NEXT: movl %eax, %ecx85; CHECK-NEXT: movq %rcx, %rax86; CHECK-NEXT: cqto87; CHECK-NEXT: movslq %edi, %rsi88; CHECK-NEXT: idivq (%rcx,%rsi,8)89; CHECK-NEXT: popq %rbp90; CHECK-NEXT: retq91 %gep = getelementptr i64, ptr null, i32 %V92 %load = load i64, ptr %gep93 %sdiv = sdiv i64 0, %load94 ret i64 %sdiv95}96