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1; REQUIRES: asserts2; RUN: llc -mtriple=i686-- -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness3; RUN: llc -mtriple=x86_64-- -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness4 5; PR64976 7; Chain and flag folding issues.8define i32 @test1() nounwind ssp {9entry:10 %tmp5.i = load volatile i32, ptr undef ; <i32> [#uses=1]11 %conv.i = zext i32 %tmp5.i to i64 ; <i64> [#uses=1]12 %tmp12.i = load volatile i32, ptr undef ; <i32> [#uses=1]13 %conv13.i = zext i32 %tmp12.i to i64 ; <i64> [#uses=1]14 %shl.i = shl i64 %conv13.i, 32 ; <i64> [#uses=1]15 %or.i = or i64 %shl.i, %conv.i ; <i64> [#uses=1]16 %add16.i = add i64 %or.i, 256 ; <i64> [#uses=1]17 %shr.i = lshr i64 %add16.i, 8 ; <i64> [#uses=1]18 %conv19.i = trunc i64 %shr.i to i32 ; <i32> [#uses=1]19 store volatile i32 %conv19.i, ptr undef20 ret i32 undef21}22 23; PR653324define void @test2(i1 %x, i32 %y) nounwind {25 %land.ext = zext i1 %x to i32 ; <i32> [#uses=1]26 %and = and i32 %y, 1 ; <i32> [#uses=1]27 %xor = xor i32 %and, %land.ext ; <i32> [#uses=1]28 %cmp = icmp eq i32 %xor, 1 ; <i1> [#uses=1]29 br i1 %cmp, label %if.end, label %if.then30 31if.then: ; preds = %land.end32 ret void33 34if.end: ; preds = %land.end35 ret void36}37 38; PR657739%pair = type { i64, double }40 41define void @test3() {42dependentGraph243.exit:43 %subject19 = load %pair, ptr undef ; <%1> [#uses=1]44 %0 = extractvalue %pair %subject19, 1 ; <double> [#uses=2]45 %1 = select i1 undef, double %0, double undef ; <double> [#uses=1]46 %2 = select i1 undef, double %1, double %0 ; <double> [#uses=1]47 %3 = insertvalue %pair undef, double %2, 1 ; <%1> [#uses=1]48 store %pair %3, ptr undef49 ret void50}51 52; PR660553define i64 @test4(ptr %P) nounwind ssp {54entry:55 %tmp1 = load i8, ptr %P ; <i8> [#uses=3]56 %tobool = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1]57 %tmp58 = sext i1 %tobool to i8 ; <i8> [#uses=1]58 %mul.i = and i8 %tmp58, %tmp1 ; <i8> [#uses=1]59 %conv6 = zext i8 %mul.i to i32 ; <i32> [#uses=1]60 %cmp = icmp ne i8 %tmp1, 1 ; <i1> [#uses=1]61 %conv11 = zext i1 %cmp to i32 ; <i32> [#uses=1]62 %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1]63 %and = and i32 %conv6, %call12 ; <i32> [#uses=1]64 %tobool13 = icmp eq i32 %and, 0 ; <i1> [#uses=1]65 br i1 %tobool13, label %if.else, label %return66 67if.else: ; preds = %entry68 br label %return69 70return: ; preds = %if.else, %entry71 ret i64 undef72}73 74declare i32 @safe(i32)75 76; PR660777define fastcc void @test5(i32 %FUNC) nounwind {78foo:79 %0 = load i8, ptr undef, align 1 ; <i8> [#uses=3]80 %1 = sext i8 %0 to i32 ; <i32> [#uses=2]81 %2 = zext i8 %0 to i32 ; <i32> [#uses=1]82 %tmp1.i5037 = urem i32 %2, 10 ; <i32> [#uses=1]83 %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15 ; <i1> [#uses=1]84 %3 = zext i1 %tmp.i5038 to i8 ; <i8> [#uses=1]85 %4 = icmp slt i8 %0, %3 ; <i1> [#uses=1]86 %5 = add nsw i32 %1, 256 ; <i32> [#uses=1]87 %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1]88 %6 = shl i32 %storemerge.i.i57, 16 ; <i32> [#uses=1]89 %7 = sdiv i32 %6, -256 ; <i32> [#uses=1]90 %8 = trunc i32 %7 to i8 ; <i8> [#uses=1]91 store i8 %8, ptr undef, align 192 ret void93}94 95 96; Crash commoning identical asms.97; PR680398define void @test6(i1 %C) nounwind optsize ssp {99entry:100 br i1 %C, label %do.body55, label %do.body92101 102do.body55: ; preds = %if.else36103 call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0104 ret void105 106do.body92: ; preds = %if.then66107 call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1108 ret void109}110 111!0 = !{i32 633550}112!1 = !{i32 634261}113 114 115; Crash during XOR optimization.116; <rdar://problem/7869290>117 118define void @test7(i1 %arg) nounwind ssp {119entry:120 br i1 %arg, label %bb14, label %bb67121 122bb14:123 %tmp0 = trunc i16 undef to i1124 %tmp1 = load i8, ptr undef, align 8125 %tmp2 = shl i8 %tmp1, 4126 %tmp3 = lshr i8 %tmp2, 7127 %tmp4 = trunc i8 %tmp3 to i1128 %tmp5 = icmp ne i1 %tmp0, %tmp4129 br i1 %tmp5, label %bb14, label %bb67130 131bb67:132 ret void133}134 135; Crash when trying to copy AH to AL.136; PR7540137define void @copy8bitregs() nounwind {138entry:139 %div.i = sdiv i32 115200, 0140 %shr8.i = lshr i32 %div.i, 8141 %conv4.i = trunc i32 %shr8.i to i8142 call void asm sideeffect "outb $0, ${1:w}", "{ax},N{dx},~{dirflag},~{fpsr},~{flags}"(i8 %conv4.i, i32 1017) nounwind143 unreachable144}145 146; Crash trying to form conditional increment with fp value.147; PR8981148define i32 @test9(double %X) ssp align 2 {149entry:150 %0 = fcmp one double %X, 0.000000e+00151 %cond = select i1 %0, i32 1, i32 2152 ret i32 %cond153}154 155 156; PR8514 - Crash in match address do to "heroics" turning and-of-shift into157; shift of and.158%struct.S0 = type { i8, [2 x i8], i8 }159 160define void @func_59(i32 %p_63, i1 %arg) noreturn nounwind {161entry:162 br label %for.body163 164for.body: ; preds = %for.inc44, %entry165 %p_63.addr.1 = phi i32 [ %p_63, %entry ], [ 0, %for.inc44 ]166 %l_74.0 = phi i32 [ 0, %entry ], [ %add46, %for.inc44 ]167 br i1 %arg, label %for.inc44, label %bb.nph81168 169bb.nph81: ; preds = %for.body170 %tmp98 = add i32 %p_63.addr.1, 0171 br label %for.body22172 173for.body22: ; preds = %for.body22, %bb.nph81174 %l_75.077 = phi i64 [ %ins, %for.body22 ], [ undef, %bb.nph81 ]175 %tmp110 = trunc i64 %l_75.077 to i32176 %tmp111 = and i32 %tmp110, 65535177 %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]], ptr undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0178 store i8 1, ptr %arrayidx32.0, align 4179 %tmp106 = shl i32 %tmp110, 2180 %tmp107 = and i32 %tmp106, 262140181 %scevgep99.sum114 = or i32 %tmp107, 1182 %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]], ptr undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114183 store i8 0, ptr %arrayidx32.1.1, align 1184 %ins = or i64 undef, undef185 br label %for.body22186 187for.inc44: ; preds = %for.body188 %add46 = add i32 %l_74.0, 1189 br label %for.body190}191 192; PR9028193define void @func_60(i64 %A) nounwind {194entry:195 %0 = zext i64 %A to i160196 %1 = shl i160 %0, 64197 %2 = zext i160 %1 to i576198 %3 = zext i96 undef to i576199 %4 = or i576 %3, %2200 store i576 %4, ptr undef, align 8201 ret void202}203 204; <rdar://problem/9187792>205define fastcc void @func_61() nounwind sspreq {206entry:207 %t1 = tail call i64 @llvm.objectsize.i64.p0(ptr undef, i1 false)208 %t2 = icmp eq i64 %t1, -1209 br i1 %t2, label %bb2, label %bb1210 211bb1:212 ret void213 214bb2:215 ret void216}217 218declare i64 @llvm.objectsize.i64.p0(ptr, i1) nounwind readnone219 220; PR10277221; This test has dead code elimination caused by remat during spilling.222; DCE causes a live interval to break into connected components.223; One of the components is spilled.224 225%t2 = type { i8 }226%t9 = type { %t10 }227%t10 = type { %t11 }228%t11 = type { %t12 }229%t12 = type { ptr, ptr, ptr }230%t13 = type { ptr, %t15, %t15 }231%t14 = type opaque232%t15 = type { i8, i32, i32 }233%t16 = type { %t17, ptr }234%t17 = type { %t18 }235%t18 = type { %t19 }236%t19 = type { ptr, ptr, ptr }237%t20 = type { i32, i32 }238%t21 = type { ptr }239 240define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE(i1 %arg) ssp align 2 {241bb:242 %tmp = load ptr, ptr undef, align 4243 %tmp3 = getelementptr inbounds %t9, ptr %tmp, i32 0, i32 0, i32 0, i32 0, i32 1244 br label %bb4245 246bb4: ; preds = %bb37, %bb247 %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ]248 %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ]249 br i1 %arg, label %bb34, label %bb7250 251bb7: ; preds = %bb4252 %tmp8 = load i32, ptr undef, align 4253 %tmp9 = and i96 %tmp6, 4294967040254 %tmp10 = zext i32 %tmp8 to i96255 %tmp11 = shl nuw nsw i96 %tmp10, 32256 %tmp12 = or i96 %tmp9, %tmp11257 %tmp13 = or i96 %tmp12, 1258 %tmp14 = load i32, ptr undef, align 4259 %tmp15 = and i96 %tmp5, 4294967040260 %tmp16 = zext i32 %tmp14 to i96261 %tmp17 = shl nuw nsw i96 %tmp16, 32262 %tmp18 = or i96 %tmp15, %tmp17263 %tmp19 = or i96 %tmp18, 1264 %tmp20 = load i8, ptr undef, align 1265 %tmp21 = and i8 %tmp20, 1266 %tmp22 = icmp ne i8 %tmp21, 0267 %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13268 %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19269 store i96 %tmp24, ptr undef, align 4270 %tmp25 = load ptr, ptr %tmp3, align 4271 %tmp26 = icmp eq ptr %tmp25, undef272 br i1 %tmp26, label %bb28, label %bb27273 274bb27: ; preds = %bb7275 br label %bb29276 277bb28: ; preds = %bb7278 call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(ptr %tmp, ptr byval(%t21) align 4 undef, ptr undef)279 br label %bb29280 281bb29: ; preds = %bb28, %bb27282 store i96 %tmp23, ptr undef, align 4283 %tmp30 = load ptr, ptr %tmp3, align 4284 br i1 false, label %bb33, label %bb31285 286bb31: ; preds = %bb29287 %tmp32 = getelementptr inbounds %t13, ptr %tmp30, i32 1288 store ptr %tmp32, ptr %tmp3, align 4289 br label %bb37290 291bb33: ; preds = %bb29292 unreachable293 294bb34: ; preds = %bb4295 br i1 %arg, label %bb36, label %bb35296 297bb35: ; preds = %bb34298 store ptr null, ptr %tmp3, align 4299 br label %bb37300 301bb36: ; preds = %bb34302 call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(ptr %tmp, ptr byval(%t21) align 4 undef, ptr undef)303 br label %bb37304 305bb37: ; preds = %bb36, %bb35, %bb31306 %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ]307 %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ]308 %tmp40 = add i32 undef, 1309 br label %bb4310}311 312declare ptr @_ZN4llvm9MCContext16CreateTempSymbolEv(ptr)313 314declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(ptr, ptr byval(%t21) align 4, ptr)315 316declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind317 318declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind319 320; PR10463321; Spilling a virtual register with <undef> uses.322define void @autogen_239_1000(i1 %arg) {323BB:324 %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>325 br label %CF326 327CF:328 %B16 = frem <8 x double> zeroinitializer, %Shuff329 %E19 = extractelement <8 x double> %Shuff, i32 5330 br i1 %arg, label %CF, label %CF75331 332CF75:333 br i1 %arg, label %CF75, label %CF76334 335CF76:336 store double %E19, ptr undef337 br i1 %arg, label %CF76, label %CF77338 339CF77:340 %B55 = fmul <8 x double> %B16, undef341 br label %CF77342}343 344; PR10527345define void @pr10527() nounwind uwtable {346entry:347 br label %"4"348 349"3":350 %0 = load <2 x i32>, ptr null, align 8351 %1 = xor <2 x i32> zeroinitializer, %0352 %2 = and <2 x i32> %1, %6353 %3 = or <2 x i32> undef, %2354 %4 = and <2 x i32> %3, undef355 store <2 x i32> %4, ptr undef356 %5 = load <2 x i32>, ptr undef, align 1357 br label %"4"358 359"4":360 %6 = phi <2 x i32> [ %5, %"3" ], [ zeroinitializer, %entry ]361 %7 = icmp ult i32 undef, undef362 br i1 %7, label %"3", label %"5"363 364"5":365 ret void366}367 368; PR11078369;370; A virtual register used by the "foo" inline asm memory operand gets371; constrained to GR32_ABCD during coalescing. This makes the inline asm372; impossible to allocate without splitting the live range and reinflating the373; register class around the inline asm.374;375; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0).376 377@__force_order = external hidden global i32, align 4378define void @pr11078(ptr %pgd) nounwind {379entry:380 %t0 = load i32, ptr %pgd, align 4381 %and2 = and i32 %t0, 1382 %tobool = icmp eq i32 %and2, 0383 br i1 %tobool, label %if.then, label %if.end384 385if.then:386 %t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @__force_order) nounwind387 br label %if.end388 389if.end:390 %t6 = inttoptr i32 %t0 to ptr391 %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i64) %t6, i32 0, i32 0, i64 0) nounwind392 ret void393}394 395; Avoid emitting wrong kill flags from InstrEmitter.396; InstrEmitter::EmitSubregNode() may steal virtual registers from already397; emitted blocks when isCoalescableExtInstr points out the opportunity.398; Make sure kill flags are cleared on the newly global virtual register.399define i64 @ov_read(ptr %vf, ptr nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, ptr %bitstream, i1 %arg) nounwind uwtable ssp {400entry:401 br i1 %arg, label %return, label %while.body.preheader402 403while.body.preheader: ; preds = %entry404 br i1 %arg, label %if.then3, label %if.end7405 406if.then3: ; preds = %while.body.preheader407 %0 = load i32, ptr undef, align 4408 br i1 %arg, label %land.lhs.true.i255, label %if.end7409 410land.lhs.true.i255: ; preds = %if.then3411 br i1 %arg, label %if.then.i256, label %if.end7412 413if.then.i256: ; preds = %land.lhs.true.i255414 %sub.i = sub i32 0, %0415 %conv = sext i32 %sub.i to i64416 br i1 %arg, label %if.end7, label %while.end417 418if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader419 unreachable420 421while.end: ; preds = %if.then.i256422 %cmp18 = icmp sgt i32 %sub.i, 0423 %.conv = select i1 %cmp18, i64 -131, i64 %conv424 ret i64 %.conv425 426return: ; preds = %entry427 ret i64 -131428}429 430; The tail call to a varargs function sets %AL.431; uitofp expands to an FCMOV instruction which splits the basic block.432; Make sure the live range of %AL isn't split.433@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32434define void @pr13188(ptr nocapture %this) uwtable ssp sanitize_address align 2 {435entry:436 %x7 = load i64, ptr %this, align 8437 %sub = add i64 %x7, -1438 %conv = uitofp i64 %sub to float439 %div = fmul float %conv, 5.000000e-01440 %conv2 = fpext float %div to double441 tail call void (...) @_Z6PrintFz(ptr @.str, double %conv2)442 ret void443}444declare void @_Z6PrintFz(...)445 446@a = external global i32, align 4447@fn1.g = private unnamed_addr constant [9 x ptr] [ptr null, ptr @a, ptr null, ptr null, ptr null, ptr null, ptr null, ptr null, ptr null], align 16448@e = external global i32, align 4449 450define void @pr13943() nounwind uwtable ssp {451entry:452 %srcval = load i576, ptr @fn1.g, align 16453 br label %for.cond454 455for.cond: ; preds = %for.inc, %entry456 %g.0 = phi i576 [ %srcval, %entry ], [ %ins, %for.inc ]457 %0 = load i32, ptr @e, align 4458 %1 = lshr i576 %g.0, 64459 %2 = trunc i576 %1 to i64460 %3 = inttoptr i64 %2 to ptr461 %cmp = icmp eq ptr undef, %3462 %conv2 = zext i1 %cmp to i32463 %and = and i32 %conv2, %0464 tail call void (...) @fn3(i32 %and) nounwind465 %tobool = icmp eq i32 undef, 0466 br i1 %tobool, label %for.inc, label %if.then467 468if.then: ; preds = %for.cond469 ret void470 471for.inc: ; preds = %for.cond472 %4 = shl i576 %1, 384473 %mask = and i576 %g.0, -726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307841474 %5 = and i576 %4, 726838724295606890509921801691610055141362320587174446476410459910173841445449629921945328942266354949348255351381262292727973638307840475 %ins = or i576 %5, %mask476 br label %for.cond477}478 479declare void @fn3(...)480 481; Check coalescing of IMPLICIT_DEF instructions:482;483; %1 = IMPLICIT_DEF484; %2 = MOV32r0485;486; When coalescing %1 and %2, the IMPLICIT_DEF instruction should be487; erased along with its value number.488;489define void @rdar12474033(i1 %arg, i32 %arg2, i32 %arg3, i32 %arg4) nounwind ssp {490bb:491 br i1 %arg, label %bb21, label %bb1492 493bb1: ; preds = %bb494 switch i32 %arg2, label %bb10 [495 i32 4, label %bb2496 i32 1, label %bb9497 i32 5, label %bb3498 i32 6, label %bb3499 i32 2, label %bb9500 ]501 502bb2: ; preds = %bb1503 unreachable504 505bb3: ; preds = %bb1, %bb1506 br i1 %arg, label %bb4, label %bb5507 508bb4: ; preds = %bb3509 unreachable510 511bb5: ; preds = %bb3512 %tmp = load <4 x float>, ptr undef, align 1513 %tmp6 = bitcast <4 x float> %tmp to i128514 %tmp7 = load <4 x float>, ptr undef, align 1515 %tmp8 = bitcast <4 x float> %tmp7 to i128516 br label %bb10517 518bb9: ; preds = %bb1, %bb1519 unreachable520 521bb10: ; preds = %bb5, %bb1522 %tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ]523 %tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ]524 switch i32 %arg3, label %bb21 [525 i32 2, label %bb18526 i32 3, label %bb13527 i32 5, label %bb16528 i32 6, label %bb17529 i32 1, label %bb18530 ]531 532bb13: ; preds = %bb10533 br i1 %arg, label %bb15, label %bb14534 535bb14: ; preds = %bb13536 br label %bb21537 538bb15: ; preds = %bb13539 unreachable540 541bb16: ; preds = %bb10542 unreachable543 544bb17: ; preds = %bb10545 unreachable546 547bb18: ; preds = %bb10, %bb10548 %tmp19 = bitcast i128 %tmp11 to <4 x float>549 %tmp20 = bitcast i128 %tmp12 to <4 x float>550 br label %bb21551 552bb21: ; preds = %bb18, %bb14, %bb10, %bb553 %tmp22 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp20, %bb18 ]554 %tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ]555 store <4 x float> %tmp23, ptr undef, align 16556 store <4 x float> %tmp22, ptr undef, align 16557 switch i32 %arg4, label %bb29 [558 i32 5, label %bb27559 i32 1, label %bb24560 i32 2, label %bb25561 i32 14, label %bb28562 i32 4, label %bb26563 ]564 565bb24: ; preds = %bb21566 unreachable567 568bb25: ; preds = %bb21569 br label %bb29570 571bb26: ; preds = %bb21572 br label %bb29573 574bb27: ; preds = %bb21575 unreachable576 577bb28: ; preds = %bb21578 br label %bb29579 580bb29: ; preds = %bb28, %bb26, %bb25, %bb21581 unreachable582}583 584define void @pr14194() nounwind uwtable {585 %tmp = load i64, ptr undef, align 16586 %tmp1 = trunc i64 %tmp to i32587 %tmp2 = lshr i64 %tmp, 32588 %tmp3 = trunc i64 %tmp2 to i32589 %tmp4 = call { i32, i32 } asm sideeffect "", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %tmp3, i32 undef, i32 %tmp3, i32 %tmp1) nounwind590 ret void591}592