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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple=x86_64 -verify-machineinstrs --run-pass=machine-cse -o - %s | FileCheck %s3# RUN: llc -mtriple=x86_64 -passes=machine-cse -o - %s | FileCheck %s4--- |5 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"6 7 define float @max(float noundef %a, float noundef %b) #0 {8 entry:9 %U = fcmp uno float %a, %b10 br i1 %U, label %UL, label %NU11 12 NU: ; preds = %entry13 %GT = fcmp ogt float %a, %b14 br i1 %GT, label %EXIT, label %NGT15 16 NGT: ; preds = %NU17 %LT = fcmp one float %a, %b18 br i1 %LT, label %EXIT, label %EQ19 20 EQ: ; preds = %NGT21 %bc = bitcast float %a to i3222 %cmp = icmp slt i32 %bc, 023 %eq = select i1 %cmp, float %a, float %b24 br label %EXIT25 26 UL: ; preds = %entry27 %AU = fcmp uno float %a, %a28 br i1 %AU, label %EXIT, label %ULB29 30 ULB: ; preds = %UL31 br label %EXIT32 33 EXIT: ; preds = %ULB, %UL, %EQ, %NGT, %NU34 %res = phi float [ %a, %NU ], [ %b, %NGT ], [ %a, %UL ], [ %eq, %EQ ], [ %b, %ULB ]35 ret float %res36 }37 38 attributes #0 = { "target-cpu"="skylake" }39 40...41---42name: max43alignment: 1644exposesReturnsTwice: false45legalized: false46regBankSelected: false47selected: false48failedISel: false49tracksRegLiveness: true50hasWinCFI: false51callsEHReturn: false52callsUnwindInit: false53hasEHContTarget: false54hasEHScopes: false55hasEHFunclets: false56isOutlined: false57debugInstrRef: true58failsVerification: false59tracksDebugUserValues: false60registers:61 - { id: 0, class: fr32, preferred-register: '' }62 - { id: 1, class: fr32, preferred-register: '' }63 - { id: 2, class: fr32, preferred-register: '' }64 - { id: 3, class: fr32, preferred-register: '' }65 - { id: 4, class: gr32, preferred-register: '' }66liveins:67 - { reg: '$xmm0', virtual-reg: '%2' }68 - { reg: '$xmm1', virtual-reg: '%3' }69frameInfo:70 isFrameAddressTaken: false71 isReturnAddressTaken: false72 hasStackMap: false73 hasPatchPoint: false74 stackSize: 075 offsetAdjustment: 076 maxAlignment: 177 adjustsStack: false78 hasCalls: false79 stackProtector: ''80 functionContext: ''81 maxCallFrameSize: 429496729582 cvBytesOfCalleeSavedRegisters: 083 hasOpaqueSPAdjustment: false84 hasVAStart: false85 hasMustTailInVarArgFunc: false86 hasTailCall: false87 localFrameSize: 088 savePoint: []89 restorePoint: []90fixedStack: []91stack: []92callSites: []93debugValueSubstitutions: []94constants: []95machineFunctionInfo: {}96body: |97 ; CHECK-LABEL: name: max98 ; CHECK: bb.0.entry:99 ; CHECK-NEXT: successors: %bb.6(0x00000800), %bb.1(0x7ffff800)100 ; CHECK-NEXT: liveins: $xmm0, $xmm1101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm1103 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm0104 ; CHECK-NEXT: nofpexcept VUCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr105 ; CHECK-NEXT: JCC_1 %bb.6, 10, implicit $eflags106 ; CHECK-NEXT: JMP_1 %bb.1107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: bb.1.NU:109 ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.2(0x40000000)110 ; CHECK-NEXT: liveins: $eflags111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: JCC_1 %bb.8, 7, implicit $eflags113 ; CHECK-NEXT: JMP_1 %bb.2114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: bb.2.NGT:116 ; CHECK-NEXT: successors: %bb.8(0x50000000), %bb.3(0x30000000)117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: nofpexcept VUCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr119 ; CHECK-NEXT: JCC_1 %bb.8, 5, implicit $eflags120 ; CHECK-NEXT: JMP_1 %bb.3121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: bb.3.EQ:123 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: [[VMOVSS2DIrr:%[0-9]+]]:gr32 = VMOVSS2DIrr [[COPY1]]126 ; CHECK-NEXT: TEST32rr [[VMOVSS2DIrr]], [[VMOVSS2DIrr]], implicit-def $eflags127 ; CHECK-NEXT: JCC_1 %bb.5, 8, implicit $eflags128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: bb.4.EQ:130 ; CHECK-NEXT: successors: %bb.5(0x80000000)131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: bb.5.EQ:133 ; CHECK-NEXT: successors: %bb.8(0x80000000)134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY]], %bb.4, [[COPY1]], %bb.3136 ; CHECK-NEXT: JMP_1 %bb.8137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: bb.6.UL:139 ; CHECK-NEXT: successors: %bb.8(0x00000800), %bb.7(0x7ffff800)140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: nofpexcept VUCOMISSrr [[COPY1]], [[COPY1]], implicit-def $eflags, implicit $mxcsr142 ; CHECK-NEXT: JCC_1 %bb.8, 10, implicit $eflags143 ; CHECK-NEXT: JMP_1 %bb.7144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: bb.7.ULB:146 ; CHECK-NEXT: successors: %bb.8(0x80000000)147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: bb.8.EXIT:149 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:fr32 = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2, [[PHI]], %bb.5, [[COPY1]], %bb.6, [[COPY]], %bb.7150 ; CHECK-NEXT: $xmm0 = COPY [[PHI1]]151 ; CHECK-NEXT: RET 0, $xmm0152 bb.0.entry:153 successors: %bb.4(0x00000800), %bb.1(0x7ffff800)154 liveins: $xmm0, $xmm1155 156 %3:fr32 = COPY $xmm1157 %2:fr32 = COPY $xmm0158 nofpexcept VUCOMISSrr %2, %3, implicit-def $eflags, implicit $mxcsr159 JCC_1 %bb.4, 10, implicit $eflags160 JMP_1 %bb.1161 162 bb.1.NU:163 successors: %bb.6(0x40000000), %bb.2(0x40000000)164 165 nofpexcept VUCOMISSrr %2, %3, implicit-def $eflags, implicit $mxcsr166 JCC_1 %bb.6, 7, implicit $eflags167 JMP_1 %bb.2168 169 bb.2.NGT:170 successors: %bb.6(0x50000000), %bb.3(0x30000000)171 172 nofpexcept VUCOMISSrr %2, %3, implicit-def $eflags, implicit $mxcsr173 JCC_1 %bb.6, 5, implicit $eflags174 JMP_1 %bb.3175 176 bb.3.EQ:177 successors: %bb.7(0x40000000), %bb.8(0x40000000)178 179 %4:gr32 = VMOVSS2DIrr %2180 TEST32rr %4, %4, implicit-def $eflags181 JCC_1 %bb.8, 8, implicit $eflags182 183 bb.7.EQ:184 successors: %bb.8(0x80000000)185 186 187 bb.8.EQ:188 successors: %bb.6(0x80000000)189 190 %0:fr32 = PHI %3, %bb.7, %2, %bb.3191 JMP_1 %bb.6192 193 bb.4.UL:194 successors: %bb.6(0x00000800), %bb.5(0x7ffff800)195 196 nofpexcept VUCOMISSrr %2, %2, implicit-def $eflags, implicit $mxcsr197 JCC_1 %bb.6, 10, implicit $eflags198 JMP_1 %bb.5199 200 bb.5.ULB:201 successors: %bb.6(0x80000000)202 203 204 bb.6.EXIT:205 %1:fr32 = PHI %2, %bb.1, %3, %bb.2, %0, %bb.8, %2, %bb.4, %3, %bb.5206 $xmm0 = COPY %1207 RET 0, $xmm0208 209...210