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1; RUN: llc < %s -mtriple=x86_64-pc-win32 -O0 -mattr=+avx | FileCheck %s2 3; Background:4; If fast-isel bails out to normal selection, then the DAG combiner will run,5; even at -O0. In principle this should not happen (those are optimizations,6; and we said -O0) but as a practical matter there are some instruction7; selection patterns that depend on the legalizations and transforms that the8; DAG combiner does.9;10; The 'optnone' attribute implicitly sets -O0 and fast-isel for the function.11; The DAG combiner was disabled for 'optnone' (but not -O0) by r221168, then12; re-enabled in r233153 because of problems with instruction selection patterns13; mentioned above. (Note: because 'optnone' is supposed to match -O0, r22116814; really should have disabled the combiner for both.)15;16; If instruction selection eventually becomes smart enough to run without DAG17; combiner, then the combiner can be turned off for -O0 (not just 'optnone')18; and this test can go away. (To be replaced by a different test that verifies19; the DAG combiner does *not* run at -O0 or for 'optnone' functions.)20;21; In the meantime, this test wants to make sure the combiner stays enabled for22; 'optnone' functions, just as it is for -O0.23 24 25; The test cases @foo[WithOptnone] prove that the same DAG combine happens26; with -O0 and with 'optnone' set. To prove this, we use a varags to cause27; fast-isel to bail out (varags aren't handled in fast isel). Then we have28; a repeated fadd that can be combined into an fmul. We show that this29; happens in both the non-optnone function and the optnone function.30 31define float @foo(float %x, ...) {32entry:33 %add = fadd fast float %x, %x34 %add1 = fadd fast float %add, %x35 ret float %add136}37 38; CHECK-LABEL: @foo39; CHECK-NOT: add40; CHECK: mul41; CHECK-NEXT: ret42 43define float @fooWithOptnone(float %x, ...) #1 {44entry:45 %add = fadd fast float %x, %x46 %add1 = fadd fast float %add, %x47 ret float %add148}49 50; CHECK-LABEL: @fooWithOptnone51; CHECK-NOT: add52; CHECK: mul53; CHECK-NEXT: ret54 55 56; The test case @bar is derived from an instruction selection failure case57; that was solved by r233153. It depends on -mattr=+avx.58; Really all we're trying to prove is that it doesn't crash any more.59 60@id84 = common global <16 x i32> zeroinitializer, align 6461 62define void @bar(...) #1 {63entry:64 %id83 = alloca <16 x i8>, align 1665 %0 = load <16 x i32>, ptr @id84, align 6466 %conv = trunc <16 x i32> %0 to <16 x i8>67 store <16 x i8> %conv, ptr %id83, align 1668 ret void69}70 71attributes #1 = { noinline optnone }72