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1# RUN: llc -O1 -start-after register-coalescer -o - %s -experimental-debug-variable-locations=true | FileCheck %s2 3--- |4 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"5 target triple = "x86_64-pc-linux-gnu"6 7 define i16 @foo(i8 %zzz) !dbg !4 {8 entry:9 ret i16 110 }11 12 ; Function Attrs: nounwind readnone speculatable13 declare void @llvm.dbg.value(metadata, metadata, metadata)14 15 !llvm.dbg.cu = !{!0}16 !llvm.module.flags = !{!3}17 18 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2)19 !1 = !DIFile(filename: "test.c", directory: "")20 !2 = !{}21 !3 = !{i32 1, !"Debug Info Version", i32 3}22 !4 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0)23 !5 = !DISubroutineType(types: !6)24 !6 = !{null}25 !7 = !DILocalVariable(name: "zzz", arg: 1, scope: !4, file: !1, line: 3, type: !8)26 !8 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed)27 !9 = !DILocation(line: 0, scope: !4)28 !10 = !DILocation(line: 4, column: 22, scope: !11)29 !11 = distinct !DILexicalBlock(scope: !4, file: !1, line: 3, column: 19)30 31...32---33name: foo34tracksRegLiveness: true35debugInstrRef: true36debugValueSubstitutions:37 - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 }38body: |39 bb.0:40 %0:gr16_abcd = MOV16ri 1, debug-instr-number 1, debug-location !941 42 bb.1:43 DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !944 %1:gr16 = COPY %0, debug-location !945 %2:gr16 = COPY %046 47 bb.2:48 $ax = COPY %1, debug-location !949 $dx = COPY %250 RET64 killed $ax, killed $dx, debug-location !951...52 53# This test is an instruction-referencing flavour of the54# dbg-value-superreg-copy.mir test. Over there, we ran into difficulties where55# register coalescing would transform DBG_VALUEs of subregisters such as:56#57# DBG_VALUE %0.sub_8bit_hi, $noreg,58#59# Into references to larger registers, potentially with the wrong offset. We60# can't refer to vregs in instruction referencing mode, so this test replicates61# the same scenario in a new test. The defining storing load gets an instruction62# number, and we encode which subregister we want through a substitution. Check63# that it comes out the other end of regalloc through coalescing still in a64# high register.65#66# CHECK-NOT: #DEBUG_VALUE:67# CHECK: #DEBUG_VALUE: foo:zzz <- ${{[abcd]+}}h68# CHECK-NOT: #DEBUG_VALUE:69