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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s3 4; Div/rem by zero is undef.5 6define i32 @srem0(i32 %x) {7; CHECK-LABEL: srem0:8; CHECK: # %bb.0:9; CHECK-NEXT: retq10 %rem = srem i32 %x, 011 ret i32 %rem12}13 14define i32 @urem0(i32 %x) {15; CHECK-LABEL: urem0:16; CHECK: # %bb.0:17; CHECK-NEXT: retq18 %rem = urem i32 %x, 019 ret i32 %rem20}21 22define i32 @sdiv0(i32 %x) {23; CHECK-LABEL: sdiv0:24; CHECK: # %bb.0:25; CHECK-NEXT: retq26 %div = sdiv i32 %x, 027 ret i32 %div28}29 30define i32 @udiv0(i32 %x) {31; CHECK-LABEL: udiv0:32; CHECK: # %bb.0:33; CHECK-NEXT: retq34 %div = udiv i32 %x, 035 ret i32 %div36}37 38; Div/rem by zero vectors is undef.39 40define <4 x i32> @srem_vec0(<4 x i32> %x) {41; CHECK-LABEL: srem_vec0:42; CHECK: # %bb.0:43; CHECK-NEXT: retq44 %rem = srem <4 x i32> %x, zeroinitializer45 ret <4 x i32> %rem46}47 48define <4 x i32> @urem_vec0(<4 x i32> %x) {49; CHECK-LABEL: urem_vec0:50; CHECK: # %bb.0:51; CHECK-NEXT: retq52 %rem = urem <4 x i32> %x, zeroinitializer53 ret <4 x i32> %rem54}55 56define <4 x i32> @sdiv_vec0(<4 x i32> %x) {57; CHECK-LABEL: sdiv_vec0:58; CHECK: # %bb.0:59; CHECK-NEXT: retq60 %div = sdiv <4 x i32> %x, zeroinitializer61 ret <4 x i32> %div62}63 64define <4 x i32> @udiv_vec0(<4 x i32> %x) {65; CHECK-LABEL: udiv_vec0:66; CHECK: # %bb.0:67; CHECK-NEXT: retq68 %div = udiv <4 x i32> %x, zeroinitializer69 ret <4 x i32> %div70}71 72; Make sure we handle undef before we try to fold constants from the select with the 0.73; These used to assert because we can't fold div/rem-by-0 into APInt.74 75define i32 @sel_urem0(i1 %cond) {76; CHECK-LABEL: sel_urem0:77; CHECK: # %bb.0:78; CHECK-NEXT: retq79 %sel = select i1 %cond, i32 23, i32 23480 %rem = urem i32 %sel, 081 ret i32 %rem82}83 84define i32 @sel_srem0(i1 %cond) {85; CHECK-LABEL: sel_srem0:86; CHECK: # %bb.0:87; CHECK-NEXT: retq88 %sel = select i1 %cond, i32 23, i32 23489 %rem = srem i32 %sel, 090 ret i32 %rem91}92 93define i32 @sel_udiv0(i1 %cond) {94; CHECK-LABEL: sel_udiv0:95; CHECK: # %bb.0:96; CHECK-NEXT: retq97 %sel = select i1 %cond, i32 23, i32 23498 %div = udiv i32 %sel, 099 ret i32 %div100}101 102define i32 @sel_sdiv0(i1 %cond) {103; CHECK-LABEL: sel_sdiv0:104; CHECK: # %bb.0:105; CHECK-NEXT: retq106 %sel = select i1 %cond, i32 23, i32 234107 %div = sdiv i32 %sel, 0108 ret i32 %div109}110 111; Make sure we handle undef before we try to fold constants from the select with the vector 0.112; These used to assert because we can't fold div/rem-by-0 into APInt.113 114define <4 x i32> @sel_urem0_vec(i1 %cond) {115; CHECK-LABEL: sel_urem0_vec:116; CHECK: # %bb.0:117; CHECK-NEXT: retq118 %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>119 %rem = urem <4 x i32> %sel, zeroinitializer120 ret <4 x i32> %rem121}122 123define <4 x i32> @sel_srem0_vec(i1 %cond) {124; CHECK-LABEL: sel_srem0_vec:125; CHECK: # %bb.0:126; CHECK-NEXT: retq127 %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>128 %rem = srem <4 x i32> %sel, zeroinitializer129 ret <4 x i32> %rem130}131 132define <4 x i32> @sel_udiv0_vec(i1 %cond) {133; CHECK-LABEL: sel_udiv0_vec:134; CHECK: # %bb.0:135; CHECK-NEXT: retq136 %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>137 %div = udiv <4 x i32> %sel, zeroinitializer138 ret <4 x i32> %div139}140 141define <4 x i32> @sel_sdiv0_vec(i1 %cond) {142; CHECK-LABEL: sel_sdiv0_vec:143; CHECK: # %bb.0:144; CHECK-NEXT: retq145 %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>146 %div = sdiv <4 x i32> %sel, zeroinitializer147 ret <4 x i32> %div148}149 150; If any element of a constant divisor vector is zero, the whole op is undef.151 152define <4 x i32> @sdiv0elt_vec(<4 x i32> %x) {153; CHECK-LABEL: sdiv0elt_vec:154; CHECK: # %bb.0:155; CHECK-NEXT: retq156 %zero = and <4 x i32> %x, <i32 0, i32 0, i32 0, i32 0>157 %some_ones = or <4 x i32> %zero, <i32 0, i32 -1, i32 0, i32 3>158 %div = sdiv <4 x i32> <i32 -11, i32 -12, i32 -13, i32 -14>, %some_ones159 ret <4 x i32> %div160}161 162define <4 x i32> @udiv0elt_vec(<4 x i32> %x) {163; CHECK-LABEL: udiv0elt_vec:164; CHECK: # %bb.0:165; CHECK-NEXT: retq166 %div = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, <i32 0, i32 3, i32 4, i32 0>167 ret <4 x i32> %div168}169 170define <4 x i32> @urem0elt_vec(<4 x i32> %x) {171; CHECK-LABEL: urem0elt_vec:172; CHECK: # %bb.0:173; CHECK-NEXT: retq174 %zero = and <4 x i32> %x, <i32 0, i32 0, i32 0, i32 0>175 %some_ones = or <4 x i32> %zero, <i32 0, i32 0, i32 0, i32 3>176 %rem = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %some_ones177 ret <4 x i32> %rem178}179 180define <4 x i32> @srem0elt_vec(<4 x i32> %x) {181; CHECK-LABEL: srem0elt_vec:182; CHECK: # %bb.0:183; CHECK-NEXT: retq184 %rem = srem <4 x i32> <i32 -11, i32 -12, i32 -13, i32 -14>, <i32 -3, i32 -3, i32 0, i32 2>185 ret <4 x i32> %rem186}187 188