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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni -mattr=+avx512vl | FileCheck %s3 4declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)5 6define i32 @mul_i8i8(ptr%a, <16 x i8> %b, i32 %c) {7; CHECK-LABEL: mul_i8i8:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: vmovdqa (%rdi), %xmm110; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm211; CHECK-NEXT: vpdpbusd %xmm0, %xmm1, %xmm212; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]13; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm014; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]15; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm016; CHECK-NEXT: vmovd %xmm0, %eax17; CHECK-NEXT: addl %esi, %eax18; CHECK-NEXT: retq19entry:20 %0 = load <16 x i8>, ptr %a, align 1621 %1 = zext <16 x i8> %0 to <16 x i32>22 %2 = sext <16 x i8> %b to <16 x i32>23 %3 = mul nsw <16 x i32> %1, %224 %4 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %3)25 %op.extra = add nsw i32 %4, %c26 ret i32 %op.extra27}28 29define i32 @mul_i4i8(<16 x i4> %a, <16 x i8> %b, i32 %c) {30; CHECK-LABEL: mul_i4i8:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm033; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm234; CHECK-NEXT: vpdpbusd %xmm1, %xmm0, %xmm235; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]36; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm037; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]38; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm039; CHECK-NEXT: vmovd %xmm0, %eax40; CHECK-NEXT: addl %edi, %eax41; CHECK-NEXT: retq42entry:43 %0 = zext <16 x i4> %a to <16 x i32>44 %1 = sext <16 x i8> %b to <16 x i32>45 %2 = mul nsw <16 x i32> %0, %146 %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)47 %op.extra = add nsw i32 %3, %c48 ret i32 %op.extra49}50 51define i32 @mul_i4i4(<16 x i4> %a, <16 x i4> %b, i32 %c) {52; CHECK-LABEL: mul_i4i4:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vpsllw $4, %xmm1, %xmm155; CHECK-NEXT: vpsrlw $4, %xmm1, %xmm156; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]57; CHECK-NEXT: vpternlogd {{.*#+}} xmm1 = xmm2 ^ (xmm1 & m32bcst)58; CHECK-NEXT: vpsubb %xmm2, %xmm1, %xmm159; CHECK-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm060; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm261; CHECK-NEXT: vpdpbusd %xmm1, %xmm0, %xmm262; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]63; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm064; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]65; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm066; CHECK-NEXT: vmovd %xmm0, %eax67; CHECK-NEXT: addl %edi, %eax68; CHECK-NEXT: retq69entry:70 %0 = zext <16 x i4> %a to <16 x i32>71 %1 = sext <16 x i4> %b to <16 x i32>72 %2 = mul nsw <16 x i32> %0, %173 %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)74 %op.extra = add nsw i32 %3, %c75 ret i32 %op.extra76}77 78define i32 @mul_sext_i4i4(<16 x i4> %a, <16 x i4> %b, i32 %c) {79; CHECK-LABEL: mul_sext_i4i4:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero82; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero83; CHECK-NEXT: vpsllw $12, %ymm1, %ymm184; CHECK-NEXT: vpsraw $12, %ymm1, %ymm185; CHECK-NEXT: vpsllw $12, %ymm0, %ymm086; CHECK-NEXT: vpsraw $12, %ymm0, %ymm087; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm088; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm189; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm090; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]91; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm092; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]93; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm094; CHECK-NEXT: vmovd %xmm0, %eax95; CHECK-NEXT: addl %edi, %eax96; CHECK-NEXT: vzeroupper97; CHECK-NEXT: retq98entry:99 %0 = sext <16 x i4> %a to <16 x i32>100 %1 = sext <16 x i4> %b to <16 x i32>101 %2 = mul nsw <16 x i32> %0, %1102 %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)103 %op.extra = add nsw i32 %3, %c104 ret i32 %op.extra105}106 107define i32 @mul_zext_i4i4(<16 x i4> %a, <16 x i4> %b, i32 %c) {108; CHECK-LABEL: mul_zext_i4i4:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]111; CHECK-NEXT: vpand %xmm2, %xmm1, %xmm1112; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0113; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2114; CHECK-NEXT: vpdpbusd %xmm1, %xmm0, %xmm2115; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]116; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0117; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]118; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0119; CHECK-NEXT: vmovd %xmm0, %eax120; CHECK-NEXT: addl %edi, %eax121; CHECK-NEXT: retq122entry:123 %0 = zext <16 x i4> %a to <16 x i32>124 %1 = zext <16 x i4> %b to <16 x i32>125 %2 = mul nsw <16 x i32> %0, %1126 %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)127 %op.extra = add nsw i32 %3, %c128 ret i32 %op.extra129}130