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1; RUN: llc < %s -stack-symbol-ordering=0 -mcpu=generic -mattr=+avx -mtriple=x86_64-apple-darwin10 | FileCheck %s2; rdar://114964343 4; no VLAs or dynamic alignment5define i32 @t1() nounwind uwtable ssp {6entry:7 %a = alloca i32, align 48 call void @t1_helper(ptr %a) nounwind9 %0 = load i32, ptr %a, align 410 %add = add nsw i32 %0, 1311 ret i32 %add12 13; CHECK: _t114; CHECK-NOT: andq $-{{[0-9]+}}, %rsp15; CHECK: leaq [[OFFSET:[0-9]*]](%rsp), %rdi16; CHECK: callq _t1_helper17; CHECK: movl [[OFFSET]](%rsp), %eax18; CHECK: addl $13, %eax19}20 21declare void @t1_helper(ptr)22 23; dynamic realignment24define i32 @t2() nounwind uwtable ssp {25entry:26 %a = alloca i32, align 427 %v = alloca <8 x float>, align 3228 call void @t2_helper(ptr %a, ptr %v) nounwind29 %0 = load i32, ptr %a, align 430 %add = add nsw i32 %0, 1331 ret i32 %add32 33; CHECK: _t234; CHECK: pushq %rbp35; CHECK: movq %rsp, %rbp36; CHECK: andq $-32, %rsp37; CHECK: subq ${{[0-9]+}}, %rsp38;39; CHECK: leaq {{[0-9]*}}(%rsp), %rdi40; CHECK: movq %rsp, %rsi41; CHECK: callq _t2_helper42;43; CHECK: movq %rbp, %rsp44; CHECK: popq %rbp45}46 47declare void @t2_helper(ptr, ptr)48 49; VLAs50define i32 @t3(i64 %sz) nounwind uwtable ssp {51entry:52 %a = alloca i32, align 453 %vla = alloca i32, i64 %sz, align 1654 call void @t3_helper(ptr %a, ptr %vla) nounwind55 %0 = load i32, ptr %a, align 456 %add = add nsw i32 %0, 1357 ret i32 %add58 59; CHECK: _t360; CHECK: pushq %rbp61; CHECK: movq %rsp, %rbp62; CHECK-NOT: andq $-{{[0-9]+}}, %rsp63; CHECK: subq ${{[0-9]+}}, %rsp64;65; CHECK: movq %rbp, %rsp66; CHECK: popq %rbp67}68 69declare void @t3_helper(ptr, ptr)70 71; VLAs + Dynamic realignment72define i32 @t4(i64 %sz) nounwind uwtable ssp {73entry:74 %a = alloca i32, align 475 %v = alloca <8 x float>, align 3276 %vla = alloca i32, i64 %sz, align 1677 call void @t4_helper(ptr %a, ptr %vla, ptr %v) nounwind78 %0 = load i32, ptr %a, align 479 %add = add nsw i32 %0, 1380 ret i32 %add81 82; CHECK: _t483; CHECK: pushq %rbp84; CHECK: movq %rsp, %rbp85; CHECK: pushq %rbx86; CHECK: andq $-32, %rsp87; CHECK: subq ${{[0-9]+}}, %rsp88; CHECK: movq %rsp, %rbx89;90; CHECK: leaq {{[0-9]*}}(%rbx), %rdi91; CHECK: movq %rbx, %rdx92; CHECK: callq _t4_helper93;94; CHECK: leaq -{{[0-9]+}}(%rbp), %rsp95; CHECK: popq %rbx96; CHECK: popq %rbp97}98 99declare void @t4_helper(ptr, ptr, ptr)100 101; Spilling an AVX register shouldn't cause dynamic realignment102define i32 @t5(ptr nocapture %f) nounwind uwtable ssp {103entry:104 %a = alloca i32, align 4105 %0 = load <8 x float>, ptr %f, align 32106 call void @t5_helper1(ptr %a) nounwind107 call void @t5_helper2(<8 x float> %0) nounwind108 %1 = load i32, ptr %a, align 4109 %add = add nsw i32 %1, 13110 ret i32 %add111 112; CHECK: _t5113; CHECK: subq ${{[0-9]+}}, %rsp114;115; CHECK: vmovaps (%rdi), [[AVXREG:%ymm[0-9]+]]116; CHECK: vmovups [[AVXREG]], (%rsp)117; CHECK: leaq {{[0-9]+}}(%rsp), %rdi118; CHECK: callq _t5_helper1119; CHECK: vmovups (%rsp), %ymm0120; CHECK: callq _t5_helper2121; CHECK: movl {{[0-9]+}}(%rsp), %eax122}123 124declare void @t5_helper1(ptr)125 126declare void @t5_helper2(<8 x float>)127 128; VLAs + Dynamic realignment + Spill129; FIXME: RA has already reserved RBX, so we can't do dynamic realignment.130define i32 @t6(i64 %sz, ptr nocapture %f) nounwind uwtable ssp {131entry:132; CHECK: _t6133 %a = alloca i32, align 4134 %0 = load <8 x float>, ptr %f, align 32135 %vla = alloca i32, i64 %sz, align 16136 call void @t6_helper1(ptr %a, ptr %vla) nounwind137 call void @t6_helper2(<8 x float> %0) nounwind138 %1 = load i32, ptr %a, align 4139 %add = add nsw i32 %1, 13140 ret i32 %add141}142 143declare void @t6_helper1(ptr, ptr)144 145declare void @t6_helper2(<8 x float>)146 147; VLAs + Dynamic realignment + byval148; The byval adjust the sp after the prolog, but if we're restoring the sp from149; the base pointer we use the original adjustment.150%struct.struct_t = type { [5 x i32] }151 152define void @t7(i32 %size, ptr byval(%struct.struct_t) align 8 %arg1) nounwind uwtable {153entry:154 %x = alloca i32, align 32155 store i32 0, ptr %x, align 32156 %0 = zext i32 %size to i64157 %vla = alloca i32, i64 %0, align 16158 %1 = load i32, ptr %x, align 32159 call void @bar(i32 %1, ptr %vla, ptr byval(%struct.struct_t) align 8 %arg1)160 ret void161 162; CHECK: _t7163; CHECK: pushq %rbp164; CHECK: movq %rsp, %rbp165; CHECK: pushq %rbx166; CHECK: andq $-32, %rsp167; CHECK: subq ${{[0-9]+}}, %rsp168; CHECK: movq %rsp, %rbx169 170; Stack adjustment for byval171; CHECK: subq {{.*}}, %rsp172; CHECK: callq _bar173; CHECK-NOT: addq {{.*}}, %rsp174; CHECK: leaq -8(%rbp), %rsp175; CHECK: popq %rbx176; CHECK: popq %rbp177}178 179declare ptr @llvm.stacksave() nounwind180 181declare void @bar(i32, ptr, ptr byval(%struct.struct_t) align 8)182 183declare void @llvm.stackrestore(ptr) nounwind184