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1; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt | FileCheck %s2target triple = "x86_64-apple-macosx10.8.0"3 4; CHECK: mm25define i32 @mm2(ptr nocapture %p, i32 %n) nounwind uwtable readonly ssp {6entry:7 br label %do.body8 9; CHECK: do.body10; Loop body has no branches before the backedge.11; CHECK-NOT: LBB12do.body:13 %max.0 = phi i32 [ 0, %entry ], [ %max.1, %do.cond ]14 %min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]15 %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ]16 %p.addr.0 = phi ptr [ %p, %entry ], [ %incdec.ptr, %do.cond ]17 %incdec.ptr = getelementptr inbounds i32, ptr %p.addr.0, i64 118 %0 = load i32, ptr %p.addr.0, align 419 %cmp = icmp sgt i32 %0, %max.020 br i1 %cmp, label %do.cond, label %if.else21 22if.else:23 %cmp1 = icmp slt i32 %0, %min.024 %.min.0 = select i1 %cmp1, i32 %0, i32 %min.025 br label %do.cond26 27do.cond:28 %max.1 = phi i32 [ %0, %do.body ], [ %max.0, %if.else ]29 %min.1 = phi i32 [ %min.0, %do.body ], [ %.min.0, %if.else ]30; CHECK: decl %esi31; CHECK: jne LBB32 %dec = add i32 %n.addr.0, -133 %tobool = icmp eq i32 %dec, 034 br i1 %tobool, label %do.end, label %do.body35 36do.end:37 %sub = sub nsw i32 %max.1, %min.138 ret i32 %sub39}40 41; CHECK: multipreds42; Deal with alternative tail predecessors43; CHECK-NOT: LBB44; CHECK: cmov45; CHECK-NOT: LBB46; CHECK: cmov47; CHECK-NOT: LBB48; CHECK: fprintf49 50define void @multipreds(i32 %sw) nounwind uwtable ssp {51entry:52 switch i32 %sw, label %if.then29 [53 i32 0, label %if.then3754 i32 127, label %if.end4155 ]56 57if.then29:58 br label %if.end4159 60if.then37:61 br label %if.end4162 63if.end41:64 %exit_status.0 = phi i32 [ 2, %if.then29 ], [ 0, %if.then37 ], [ 66, %entry ]65 call void (...) @fprintf(i32 %exit_status.0) nounwind66 unreachable67}68 69declare void @fprintf(...) nounwind70 71; CHECK: BZ2_decompress72; This test case contains irreducible control flow, so MachineLoopInfo doesn't73; recognize the cycle in the CFG. This would confuse MachineTraceMetrics.74define void @BZ2_decompress(ptr %s) nounwind ssp {75entry:76 switch i32 undef, label %sw.default [77 i32 39, label %if.end.sw.bb2050_crit_edge78 i32 36, label %sw.bb178879 i32 37, label %if.end.sw.bb1855_crit_edge80 i32 40, label %sw.bb240981 i32 38, label %sw.bb198382 i32 44, label %if.end.sw.bb3058_crit_edge83 ]84 85if.end.sw.bb3058_crit_edge: ; preds = %entry86 br label %save_state_and_return87 88if.end.sw.bb1855_crit_edge: ; preds = %entry89 br label %save_state_and_return90 91if.end.sw.bb2050_crit_edge: ; preds = %entry92 br label %sw.bb205093 94sw.bb1788: ; preds = %entry95 br label %save_state_and_return96 97sw.bb1983: ; preds = %entry98 br i1 undef, label %save_state_and_return, label %if.then199099 100if.then1990: ; preds = %sw.bb1983101 br label %while.body2038102 103while.body2038: ; preds = %sw.bb2050, %if.then1990104 %groupPos.8 = phi i32 [ 0, %if.then1990 ], [ %groupPos.9, %sw.bb2050 ]105 br i1 undef, label %save_state_and_return, label %if.end2042106 107if.end2042: ; preds = %while.body2038108 br i1 undef, label %if.end2048, label %while.end2104109 110if.end2048: ; preds = %if.end2042111 %bsLive2054.pre = getelementptr inbounds i8, ptr %s, i32 8112 br label %sw.bb2050113 114sw.bb2050: ; preds = %if.end2048, %if.end.sw.bb2050_crit_edge115 %groupPos.9 = phi i32 [ 0, %if.end.sw.bb2050_crit_edge ], [ %groupPos.8, %if.end2048 ]116 %and2064 = and i32 undef, 1117 br label %while.body2038118 119while.end2104: ; preds = %if.end2042120 br i1 undef, label %save_state_and_return, label %if.end2117121 122if.end2117: ; preds = %while.end2104123 br i1 undef, label %while.body2161.lr.ph, label %while.body2145.lr.ph124 125while.body2145.lr.ph: ; preds = %if.end2117126 br label %save_state_and_return127 128while.body2161.lr.ph: ; preds = %if.end2117129 br label %save_state_and_return130 131sw.bb2409: ; preds = %entry132 br label %save_state_and_return133 134sw.default: ; preds = %entry135 call void @BZ2_bz__AssertH__fail() nounwind136 br label %save_state_and_return137 138save_state_and_return:139 %groupPos.14 = phi i32 [ 0, %sw.default ], [ %groupPos.8, %while.body2038 ], [ %groupPos.8, %while.end2104 ], [ 0, %if.end.sw.bb3058_crit_edge ], [ 0, %if.end.sw.bb1855_crit_edge ], [ %groupPos.8, %while.body2161.lr.ph ], [ %groupPos.8, %while.body2145.lr.ph ], [ 0, %sw.bb2409 ], [ 0, %sw.bb1788 ], [ 0, %sw.bb1983 ]140 store i32 %groupPos.14, ptr undef, align 4141 ret void142}143 144declare void @BZ2_bz__AssertH__fail()145 146; Make sure we don't speculate on div/idiv instructions147; CHECK: test_idiv148; CHECK-NOT: cmov149define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp {150 %1 = icmp eq i32 %b, 0151 br i1 %1, label %4, label %2152 153; <label>:2 ; preds = %0154 %3 = sdiv i32 %a, %b155 br label %4156 157; <label>:4 ; preds = %0, %2158 %5 = phi i32 [ %3, %2 ], [ %a, %0 ]159 ret i32 %5160}161 162; CHECK: test_div163; CHECK-NOT: cmov164define i32 @test_div(i32 %a, i32 %b) nounwind uwtable readnone ssp {165 %1 = icmp eq i32 %b, 0166 br i1 %1, label %4, label %2167 168; <label>:2 ; preds = %0169 %3 = udiv i32 %a, %b170 br label %4171 172; <label>:4 ; preds = %0, %2173 %5 = phi i32 [ %3, %2 ], [ %a, %0 ]174 ret i32 %5175}176