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1# RUN: llc -mtriple=x86_64-- -run-pass x86-compress-evex -verify-machineinstrs -mcpu=skx -o - %s | FileCheck %s2# This test verifies VEX encoding for AVX-512 instructions that use registers of low indexes and3# do not use zmm or mask registers and have a corresponding AVX/AVX2 opcode4 5--- |6 define void @evex_z256_to_vex_test() { ret void }7 define void @evex_z128_to_vex_test() { ret void }8 define void @evex_scalar_to_vex_test() { ret void }9 define void @evex_z256_to_evex_test() { ret void }10 define void @evex_z128_to_evex_test() { ret void }11 define void @evex_scalar_to_evex_test() { ret void }12...13---14 # CHECK-LABEL: name: evex_z256_to_vex_test15 # CHECK: bb.0:16 17name: evex_z256_to_vex_test18body: |19 bb.0:20 ; CHECK: VMOVAPDYmr $rdi, 1, $noreg, 0, $noreg, $ymm021 VMOVAPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm022 ; CHECK: $ymm0 = VMOVAPDYrm $rip, 1, $noreg, 0, $noreg23 $ymm0 = VMOVAPDZ256rm $rip, 1, $noreg, 0, $noreg24 ; CHECK: $ymm0 = VMOVAPDYrr $ymm025 $ymm0 = VMOVAPDZ256rr $ymm026 ; CHECK: VMOVAPSYmr $rdi, 1, $noreg, 0, $noreg, $ymm027 VMOVAPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm028 ; CHECK: $ymm0 = VMOVAPSYrm $rip, 1, $noreg, 0, $noreg29 $ymm0 = VMOVAPSZ256rm $rip, 1, $noreg, 0, $noreg30 ; CHECK: $ymm0 = VMOVAPSYrr $ymm031 $ymm0 = VMOVAPSZ256rr $ymm032 ; CHECK: $ymm0 = VMOVDDUPYrm $rip, 1, $noreg, 0, $noreg33 $ymm0 = VMOVDDUPZ256rm $rip, 1, $noreg, 0, $noreg34 ; CHECK: $ymm0 = VMOVDDUPYrr $ymm035 $ymm0 = VMOVDDUPZ256rr $ymm036 ; CHECK: VMOVDQAYmr $rdi, 1, $noreg, 0, $noreg, $ymm037 VMOVDQA32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm038 ; CHECK: $ymm0 = VMOVDQAYrm $rip, 1, $noreg, 0, $noreg39 $ymm0 = VMOVDQA32Z256rm $rip, 1, $noreg, 0, $noreg40 ; CHECK: $ymm0 = VMOVDQAYrr $ymm041 $ymm0 = VMOVDQA32Z256rr $ymm042 ; CHECK: VMOVDQAYmr $rdi, 1, $noreg, 0, $noreg, $ymm043 VMOVDQA64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm044 ; CHECK: $ymm0 = VMOVDQAYrm $rip, 1, $noreg, 0, $noreg45 $ymm0 = VMOVDQA64Z256rm $rip, 1, $noreg, 0, $noreg46 ; CHECK: $ymm0 = VMOVDQAYrr $ymm047 $ymm0 = VMOVDQA64Z256rr $ymm048 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm049 VMOVDQU16Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm050 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg51 $ymm0 = VMOVDQU16Z256rm $rip, 1, $noreg, 0, $noreg52 ; CHECK: $ymm0 = VMOVDQUYrr $ymm053 $ymm0 = VMOVDQU16Z256rr $ymm054 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm055 VMOVDQU32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm056 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg57 $ymm0 = VMOVDQU32Z256rm $rip, 1, $noreg, 0, $noreg58 ; CHECK: $ymm0 = VMOVDQUYrr $ymm059 $ymm0 = VMOVDQU32Z256rr $ymm060 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm061 VMOVDQU64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm062 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg63 $ymm0 = VMOVDQU64Z256rm $rip, 1, $noreg, 0, $noreg64 ; CHECK: $ymm0 = VMOVDQUYrr $ymm065 $ymm0 = VMOVDQU64Z256rr $ymm066 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm067 VMOVDQU8Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm068 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg69 $ymm0 = VMOVDQU8Z256rm $rip, 1, $noreg, 0, $noreg70 ; CHECK: $ymm0 = VMOVDQUYrr $ymm071 $ymm0 = VMOVDQU8Z256rr $ymm072 ; CHECK: $ymm0 = VMOVNTDQAYrm $rip, 1, $noreg, 0, $noreg73 $ymm0 = VMOVNTDQAZ256rm $rip, 1, $noreg, 0, $noreg74 ; CHECK: VMOVNTDQYmr $rdi, 1, $noreg, 0, $noreg, $ymm075 VMOVNTDQZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm076 ; CHECK: VMOVNTPDYmr $rdi, 1, $noreg, 0, $noreg, $ymm077 VMOVNTPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm078 ; CHECK: VMOVNTPSYmr $rdi, 1, $noreg, 0, $noreg, $ymm079 VMOVNTPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm080 ; CHECK: $ymm0 = VMOVSHDUPYrm $rip, 1, $noreg, 0, $noreg81 $ymm0 = VMOVSHDUPZ256rm $rip, 1, $noreg, 0, $noreg82 ; CHECK: $ymm0 = VMOVSHDUPYrr $ymm083 $ymm0 = VMOVSHDUPZ256rr $ymm084 ; CHECK: $ymm0 = VMOVSLDUPYrm $rip, 1, $noreg, 0, $noreg85 $ymm0 = VMOVSLDUPZ256rm $rip, 1, $noreg, 0, $noreg86 ; CHECK: $ymm0 = VMOVSLDUPYrr $ymm087 $ymm0 = VMOVSLDUPZ256rr $ymm088 ; CHECK: VMOVUPDYmr $rdi, 1, $noreg, 0, $noreg, $ymm089 VMOVUPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm090 ; CHECK: $ymm0 = VMOVUPDYrm $rip, 1, $noreg, 0, $noreg91 $ymm0 = VMOVUPDZ256rm $rip, 1, $noreg, 0, $noreg92 ; CHECK: $ymm0 = VMOVUPDYrr $ymm093 $ymm0 = VMOVUPDZ256rr $ymm094 ; CHECK: VMOVUPSYmr $rdi, 1, $noreg, 0, $noreg, $ymm095 VMOVUPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm096 ; CHECK: $ymm0 = VPANDYrm $ymm0, $rip, 1, $noreg, 0, $noreg97 $ymm0 = VPANDDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg98 ; CHECK: $ymm0 = VPANDYrr $ymm0, $ymm199 $ymm0 = VPANDDZ256rr $ymm0, $ymm1100 ; CHECK: $ymm0 = VPANDYrm $ymm0, $rip, 1, $noreg, 0, $noreg101 $ymm0 = VPANDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg102 ; CHECK: $ymm0 = VPANDYrr $ymm0, $ymm1103 $ymm0 = VPANDQZ256rr $ymm0, $ymm1104 ; CHECK: $ymm0 = VPANDNYrm $ymm0, $rip, 1, $noreg, 0, $noreg105 $ymm0 = VPANDNDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg106 ; CHECK: $ymm0 = VPANDNYrr $ymm0, $ymm1107 $ymm0 = VPANDNDZ256rr $ymm0, $ymm1108 ; CHECK: $ymm0 = VPANDNYrm $ymm0, $rip, 1, $noreg, 0, $noreg109 $ymm0 = VPANDNQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg110 ; CHECK: $ymm0 = VPANDNYrr $ymm0, $ymm1111 $ymm0 = VPANDNQZ256rr $ymm0, $ymm1112 ; CHECK: $ymm0 = VPAVGBYrm $ymm0, $rip, 1, $noreg, 0, $noreg113 $ymm0 = VPAVGBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg114 ; CHECK: $ymm0 = VPAVGBYrr $ymm0, $ymm1115 $ymm0 = VPAVGBZ256rr $ymm0, $ymm1116 ; CHECK: $ymm0 = VPAVGWYrm $ymm0, $rip, 1, $noreg, 0, $noreg117 $ymm0 = VPAVGWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg118 ; CHECK: $ymm0 = VPAVGWYrr $ymm0, $ymm1119 $ymm0 = VPAVGWZ256rr $ymm0, $ymm1120 ; CHECK: $ymm0 = VPADDBYrm $ymm0, $rip, 1, $noreg, 0, $noreg121 $ymm0 = VPADDBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg122 ; CHECK: $ymm0 = VPADDBYrr $ymm0, $ymm1123 $ymm0 = VPADDBZ256rr $ymm0, $ymm1124 ; CHECK: $ymm0 = VPADDDYrm $ymm0, $rip, 1, $noreg, 0, $noreg125 $ymm0 = VPADDDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg126 ; CHECK: $ymm0 = VPADDDYrr $ymm0, $ymm1127 $ymm0 = VPADDDZ256rr $ymm0, $ymm1128 ; CHECK: $ymm0 = VPADDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg129 $ymm0 = VPADDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg130 ; CHECK: $ymm0 = VPADDQYrr $ymm0, $ymm1131 $ymm0 = VPADDQZ256rr $ymm0, $ymm1132 ; CHECK: $ymm0 = VPADDSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg133 $ymm0 = VPADDSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg134 ; CHECK: $ymm0 = VPADDSBYrr $ymm0, $ymm1135 $ymm0 = VPADDSBZ256rr $ymm0, $ymm1136 ; CHECK: $ymm0 = VPADDSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg137 $ymm0 = VPADDSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg138 ; CHECK: $ymm0 = VPADDSWYrr $ymm0, $ymm1139 $ymm0 = VPADDSWZ256rr $ymm0, $ymm1140 ; CHECK: $ymm0 = VPADDUSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg141 $ymm0 = VPADDUSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg142 ; CHECK: $ymm0 = VPADDUSBYrr $ymm0, $ymm1143 $ymm0 = VPADDUSBZ256rr $ymm0, $ymm1144 ; CHECK: $ymm0 = VPADDUSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg145 $ymm0 = VPADDUSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg146 ; CHECK: $ymm0 = VPADDUSWYrr $ymm0, $ymm1147 $ymm0 = VPADDUSWZ256rr $ymm0, $ymm1148 ; CHECK: $ymm0 = VPADDWYrm $ymm0, $rip, 1, $noreg, 0, $noreg149 $ymm0 = VPADDWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg150 ; CHECK: $ymm0 = VPADDWYrr $ymm0, $ymm1151 $ymm0 = VPADDWZ256rr $ymm0, $ymm1152 ; CHECK: $ymm0 = VMULPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr153 $ymm0 = VMULPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr154 ; CHECK: $ymm0 = VMULPDYrr $ymm0, $ymm1, implicit $mxcsr155 $ymm0 = VMULPDZ256rr $ymm0, $ymm1, implicit $mxcsr156 ; CHECK: $ymm0 = VMULPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr157 $ymm0 = VMULPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr158 ; CHECK: $ymm0 = VMULPSYrr $ymm0, $ymm1, implicit $mxcsr159 $ymm0 = VMULPSZ256rr $ymm0, $ymm1, implicit $mxcsr160 ; CHECK: $ymm0 = VORPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg161 $ymm0 = VORPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg162 ; CHECK: $ymm0 = VORPDYrr $ymm0, $ymm1163 $ymm0 = VORPDZ256rr $ymm0, $ymm1164 ; CHECK: $ymm0 = VORPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg165 $ymm0 = VORPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg166 ; CHECK: $ymm0 = VORPSYrr $ymm0, $ymm1167 $ymm0 = VORPSZ256rr $ymm0, $ymm1168 ; CHECK: $ymm0 = VPMADDUBSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg169 $ymm0 = VPMADDUBSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg170 ; CHECK: $ymm0 = VPMADDUBSWYrr $ymm0, $ymm1171 $ymm0 = VPMADDUBSWZ256rr $ymm0, $ymm1172 ; CHECK: $ymm0 = VPMADDWDYrm $ymm0, $rip, 1, $noreg, 0, $noreg173 $ymm0 = VPMADDWDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg174 ; CHECK: $ymm0 = VPMADDWDYrr $ymm0, $ymm1175 $ymm0 = VPMADDWDZ256rr $ymm0, $ymm1176 ; CHECK: $ymm0 = VPMAXSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg177 $ymm0 = VPMAXSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg178 ; CHECK: $ymm0 = VPMAXSBYrr $ymm0, $ymm1179 $ymm0 = VPMAXSBZ256rr $ymm0, $ymm1180 ; CHECK: $ymm0 = VPMAXSDYrm $ymm0, $rip, 1, $noreg, 0, $noreg181 $ymm0 = VPMAXSDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg182 ; CHECK: $ymm0 = VPMAXSDYrr $ymm0, $ymm1183 $ymm0 = VPMAXSDZ256rr $ymm0, $ymm1184 ; CHECK: $ymm0 = VPMAXSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg185 $ymm0 = VPMAXSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg186 ; CHECK: $ymm0 = VPMAXSWYrr $ymm0, $ymm1187 $ymm0 = VPMAXSWZ256rr $ymm0, $ymm1188 ; CHECK: $ymm0 = VPMAXUBYrm $ymm0, $rip, 1, $noreg, 0, $noreg189 $ymm0 = VPMAXUBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg190 ; CHECK: $ymm0 = VPMAXUBYrr $ymm0, $ymm1191 $ymm0 = VPMAXUBZ256rr $ymm0, $ymm1192 ; CHECK: $ymm0 = VPMAXUDYrm $ymm0, $rip, 1, $noreg, 0, $noreg193 $ymm0 = VPMAXUDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg194 ; CHECK: $ymm0 = VPMAXUDYrr $ymm0, $ymm1195 $ymm0 = VPMAXUDZ256rr $ymm0, $ymm1196 ; CHECK: $ymm0 = VPMAXUWYrm $ymm0, $rip, 1, $noreg, 0, $noreg197 $ymm0 = VPMAXUWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg198 ; CHECK: $ymm0 = VPMAXUWYrr $ymm0, $ymm1199 $ymm0 = VPMAXUWZ256rr $ymm0, $ymm1200 ; CHECK: $ymm0 = VPMINSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg201 $ymm0 = VPMINSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg202 ; CHECK: $ymm0 = VPMINSBYrr $ymm0, $ymm1203 $ymm0 = VPMINSBZ256rr $ymm0, $ymm1204 ; CHECK: $ymm0 = VPMINSDYrm $ymm0, $rip, 1, $noreg, 0, $noreg205 $ymm0 = VPMINSDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg206 ; CHECK: $ymm0 = VPMINSDYrr $ymm0, $ymm1207 $ymm0 = VPMINSDZ256rr $ymm0, $ymm1208 ; CHECK: $ymm0 = VPMINSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg209 $ymm0 = VPMINSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg210 ; CHECK: $ymm0 = VPMINSWYrr $ymm0, $ymm1211 $ymm0 = VPMINSWZ256rr $ymm0, $ymm1212 ; CHECK: $ymm0 = VPMINUBYrm $ymm0, $rip, 1, $noreg, 0, $noreg213 $ymm0 = VPMINUBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg214 ; CHECK: $ymm0 = VPMINUBYrr $ymm0, $ymm1215 $ymm0 = VPMINUBZ256rr $ymm0, $ymm1216 ; CHECK: $ymm0 = VPMINUDYrm $ymm0, $rip, 1, $noreg, 0, $noreg217 $ymm0 = VPMINUDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg218 ; CHECK: $ymm0 = VPMINUDYrr $ymm0, $ymm1219 $ymm0 = VPMINUDZ256rr $ymm0, $ymm1220 ; CHECK: $ymm0 = VPMINUWYrm $ymm0, $rip, 1, $noreg, 0, $noreg221 $ymm0 = VPMINUWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg222 ; CHECK: $ymm0 = VPMINUWYrr $ymm0, $ymm1223 $ymm0 = VPMINUWZ256rr $ymm0, $ymm1224 ; CHECK: $ymm0 = VPMULDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg225 $ymm0 = VPMULDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg226 ; CHECK: $ymm0 = VPMULDQYrr $ymm0, $ymm1227 $ymm0 = VPMULDQZ256rr $ymm0, $ymm1228 ; CHECK: $ymm0 = VPMULHRSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg229 $ymm0 = VPMULHRSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg230 ; CHECK: $ymm0 = VPMULHRSWYrr $ymm0, $ymm1231 $ymm0 = VPMULHRSWZ256rr $ymm0, $ymm1232 ; CHECK: $ymm0 = VPMULHUWYrm $ymm0, $rip, 1, $noreg, 0, $noreg233 $ymm0 = VPMULHUWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg234 ; CHECK: $ymm0 = VPMULHUWYrr $ymm0, $ymm1235 $ymm0 = VPMULHUWZ256rr $ymm0, $ymm1236 ; CHECK: $ymm0 = VPMULHWYrm $ymm0, $rip, 1, $noreg, 0, $noreg237 $ymm0 = VPMULHWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg238 ; CHECK: $ymm0 = VPMULHWYrr $ymm0, $ymm1239 $ymm0 = VPMULHWZ256rr $ymm0, $ymm1240 ; CHECK: $ymm0 = VPMULLDYrm $ymm0, $rip, 1, $noreg, 0, $noreg241 $ymm0 = VPMULLDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg242 ; CHECK: $ymm0 = VPMULLDYrr $ymm0, $ymm1243 $ymm0 = VPMULLDZ256rr $ymm0, $ymm1244 ; CHECK: $ymm0 = VPMULLWYrm $ymm0, $rip, 1, $noreg, 0, $noreg245 $ymm0 = VPMULLWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg246 ; CHECK: $ymm0 = VPMULLWYrr $ymm0, $ymm1247 $ymm0 = VPMULLWZ256rr $ymm0, $ymm1248 ; CHECK: $ymm0 = VPMULUDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg249 $ymm0 = VPMULUDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg250 ; CHECK: $ymm0 = VPMULUDQYrr $ymm0, $ymm1251 $ymm0 = VPMULUDQZ256rr $ymm0, $ymm1252 ; CHECK: $ymm0 = VPORYrm $ymm0, $rip, 1, $noreg, 0, $noreg253 $ymm0 = VPORDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg254 ; CHECK: $ymm0 = VPORYrr $ymm0, $ymm1255 $ymm0 = VPORDZ256rr $ymm0, $ymm1256 ; CHECK: $ymm0 = VPORYrm $ymm0, $rip, 1, $noreg, 0, $noreg257 $ymm0 = VPORQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg258 ; CHECK: $ymm0 = VPORYrr $ymm0, $ymm1259 $ymm0 = VPORQZ256rr $ymm0, $ymm1260 ; CHECK: $ymm0 = VPSUBBYrm $ymm0, $rip, 1, $noreg, 0, $noreg261 $ymm0 = VPSUBBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg262 ; CHECK: $ymm0 = VPSUBBYrr $ymm0, $ymm1263 $ymm0 = VPSUBBZ256rr $ymm0, $ymm1264 ; CHECK: $ymm0 = VPSUBDYrm $ymm0, $rip, 1, $noreg, 0, $noreg265 $ymm0 = VPSUBDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg266 ; CHECK: $ymm0 = VPSUBDYrr $ymm0, $ymm1267 $ymm0 = VPSUBDZ256rr $ymm0, $ymm1268 ; CHECK: $ymm0 = VPSUBQYrm $ymm0, $rip, 1, $noreg, 0, $noreg269 $ymm0 = VPSUBQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg270 ; CHECK: $ymm0 = VPSUBQYrr $ymm0, $ymm1271 $ymm0 = VPSUBQZ256rr $ymm0, $ymm1272 ; CHECK: $ymm0 = VPSUBSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg273 $ymm0 = VPSUBSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg274 ; CHECK: $ymm0 = VPSUBSBYrr $ymm0, $ymm1275 $ymm0 = VPSUBSBZ256rr $ymm0, $ymm1276 ; CHECK: $ymm0 = VPSUBSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg277 $ymm0 = VPSUBSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg278 ; CHECK: $ymm0 = VPSUBSWYrr $ymm0, $ymm1279 $ymm0 = VPSUBSWZ256rr $ymm0, $ymm1280 ; CHECK: $ymm0 = VPSUBUSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg281 $ymm0 = VPSUBUSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg282 ; CHECK: $ymm0 = VPSUBUSBYrr $ymm0, $ymm1283 $ymm0 = VPSUBUSBZ256rr $ymm0, $ymm1284 ; CHECK: $ymm0 = VPSUBUSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg285 $ymm0 = VPSUBUSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg286 ; CHECK: $ymm0 = VPSUBUSWYrr $ymm0, $ymm1287 $ymm0 = VPSUBUSWZ256rr $ymm0, $ymm1288 ; CHECK: $ymm0 = VPSUBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg289 $ymm0 = VPSUBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg290 ; CHECK: $ymm0 = VPSUBWYrr $ymm0, $ymm1291 $ymm0 = VPSUBWZ256rr $ymm0, $ymm1292 ; CHECK: $ymm0 = VPXORYrm $ymm0, $rip, 1, $noreg, 0, $noreg293 $ymm0 = VPXORDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg294 ; CHECK: $ymm0 = VPXORYrr $ymm0, $ymm1295 $ymm0 = VPXORDZ256rr $ymm0, $ymm1296 ; CHECK: $ymm0 = VPXORYrm $ymm0, $rip, 1, $noreg, 0, $noreg297 $ymm0 = VPXORQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg298 ; CHECK: $ymm0 = VPXORYrr $ymm0, $ymm1299 $ymm0 = VPXORQZ256rr $ymm0, $ymm1300 ; CHECK: $ymm0 = VADDPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr301 $ymm0 = VADDPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr302 ; CHECK: $ymm0 = VADDPDYrr $ymm0, $ymm1, implicit $mxcsr303 $ymm0 = VADDPDZ256rr $ymm0, $ymm1, implicit $mxcsr304 ; CHECK: $ymm0 = VADDPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr305 $ymm0 = VADDPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr306 ; CHECK: $ymm0 = VADDPSYrr $ymm0, $ymm1, implicit $mxcsr307 $ymm0 = VADDPSZ256rr $ymm0, $ymm1, implicit $mxcsr308 ; CHECK: $ymm0 = VANDNPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg309 $ymm0 = VANDNPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg310 ; CHECK: $ymm0 = VANDNPDYrr $ymm0, $ymm1311 $ymm0 = VANDNPDZ256rr $ymm0, $ymm1312 ; CHECK: $ymm0 = VANDNPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg313 $ymm0 = VANDNPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg314 ; CHECK: $ymm0 = VANDNPSYrr $ymm0, $ymm1315 $ymm0 = VANDNPSZ256rr $ymm0, $ymm1316 ; CHECK: $ymm0 = VANDPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg317 $ymm0 = VANDPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg318 ; CHECK: $ymm0 = VANDPDYrr $ymm0, $ymm1319 $ymm0 = VANDPDZ256rr $ymm0, $ymm1320 ; CHECK: $ymm0 = VANDPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg321 $ymm0 = VANDPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg322 ; CHECK: $ymm0 = VANDPSYrr $ymm0, $ymm1323 $ymm0 = VANDPSZ256rr $ymm0, $ymm1324 ; CHECK: $ymm0 = VDIVPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr325 $ymm0 = VDIVPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr326 ; CHECK: $ymm0 = VDIVPDYrr $ymm0, $ymm1, implicit $mxcsr327 $ymm0 = VDIVPDZ256rr $ymm0, $ymm1, implicit $mxcsr328 ; CHECK: $ymm0 = VDIVPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr329 $ymm0 = VDIVPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr330 ; CHECK: $ymm0 = VDIVPSYrr $ymm0, $ymm1, implicit $mxcsr331 $ymm0 = VDIVPSZ256rr $ymm0, $ymm1, implicit $mxcsr332 ; CHECK: $ymm0 = VMAXCPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr333 $ymm0 = VMAXCPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr334 ; CHECK: $ymm0 = VMAXCPDYrr $ymm0, $ymm1, implicit $mxcsr335 $ymm0 = VMAXCPDZ256rr $ymm0, $ymm1, implicit $mxcsr336 ; CHECK: $ymm0 = VMAXCPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr337 $ymm0 = VMAXCPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr338 ; CHECK: $ymm0 = VMAXCPSYrr $ymm0, $ymm1, implicit $mxcsr339 $ymm0 = VMAXCPSZ256rr $ymm0, $ymm1, implicit $mxcsr340 ; CHECK: $ymm0 = VMAXPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr341 $ymm0 = VMAXPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr342 ; CHECK: $ymm0 = VMAXPDYrr $ymm0, $ymm1, implicit $mxcsr343 $ymm0 = VMAXPDZ256rr $ymm0, $ymm1, implicit $mxcsr344 ; CHECK: $ymm0 = VMAXPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr345 $ymm0 = VMAXPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr346 ; CHECK: $ymm0 = VMAXPSYrr $ymm0, $ymm1, implicit $mxcsr347 $ymm0 = VMAXPSZ256rr $ymm0, $ymm1, implicit $mxcsr348 ; CHECK: $ymm0 = VMINCPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr349 $ymm0 = VMINCPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr350 ; CHECK: $ymm0 = VMINCPDYrr $ymm0, $ymm1, implicit $mxcsr351 $ymm0 = VMINCPDZ256rr $ymm0, $ymm1, implicit $mxcsr352 ; CHECK: $ymm0 = VMINCPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr353 $ymm0 = VMINCPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr354 ; CHECK: $ymm0 = VMINCPSYrr $ymm0, $ymm1, implicit $mxcsr355 $ymm0 = VMINCPSZ256rr $ymm0, $ymm1, implicit $mxcsr356 ; CHECK: $ymm0 = VMINPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr357 $ymm0 = VMINPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr358 ; CHECK: $ymm0 = VMINPDYrr $ymm0, $ymm1, implicit $mxcsr359 $ymm0 = VMINPDZ256rr $ymm0, $ymm1, implicit $mxcsr360 ; CHECK: $ymm0 = VMINPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr361 $ymm0 = VMINPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr362 ; CHECK: $ymm0 = VMINPSYrr $ymm0, $ymm1, implicit $mxcsr363 $ymm0 = VMINPSZ256rr $ymm0, $ymm1, implicit $mxcsr364 ; CHECK: $ymm0 = VXORPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg365 $ymm0 = VXORPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg366 ; CHECK: $ymm0 = VXORPDYrr $ymm0, $ymm1367 $ymm0 = VXORPDZ256rr $ymm0, $ymm1368 ; CHECK: $ymm0 = VXORPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg369 $ymm0 = VXORPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg370 ; CHECK: $ymm0 = VXORPSYrr $ymm0, $ymm1371 $ymm0 = VXORPSZ256rr $ymm0, $ymm1372 ; CHECK: $ymm0 = VPACKSSDWYrm $ymm0, $rip, 1, $noreg, 0, $noreg373 $ymm0 = VPACKSSDWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg374 ; CHECK: $ymm0 = VPACKSSDWYrr $ymm0, $ymm1375 $ymm0 = VPACKSSDWZ256rr $ymm0, $ymm1376 ; CHECK: $ymm0 = VPACKSSWBYrm $ymm0, $rip, 1, $noreg, 0, $noreg377 $ymm0 = VPACKSSWBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg378 ; CHECK: $ymm0 = VPACKSSWBYrr $ymm0, $ymm1379 $ymm0 = VPACKSSWBZ256rr $ymm0, $ymm1380 ; CHECK: $ymm0 = VPACKUSDWYrm $ymm0, $rip, 1, $noreg, 0, $noreg381 $ymm0 = VPACKUSDWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg382 ; CHECK: $ymm0 = VPACKUSDWYrr $ymm0, $ymm1383 $ymm0 = VPACKUSDWZ256rr $ymm0, $ymm1384 ; CHECK: $ymm0 = VPACKUSWBYrm $ymm0, $rip, 1, $noreg, 0, $noreg385 $ymm0 = VPACKUSWBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg386 ; CHECK: $ymm0 = VPACKUSWBYrr $ymm0, $ymm1387 $ymm0 = VPACKUSWBZ256rr $ymm0, $ymm1388 ; CHECK: $ymm0 = VUNPCKHPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg389 $ymm0 = VUNPCKHPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg390 ; CHECK: $ymm0 = VUNPCKHPDYrr $ymm0, $ymm1391 $ymm0 = VUNPCKHPDZ256rr $ymm0, $ymm1392 ; CHECK: $ymm0 = VUNPCKHPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg393 $ymm0 = VUNPCKHPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg394 ; CHECK: $ymm0 = VUNPCKHPSYrr $ymm0, $ymm1395 $ymm0 = VUNPCKHPSZ256rr $ymm0, $ymm1396 ; CHECK: $ymm0 = VUNPCKLPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg397 $ymm0 = VUNPCKLPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg398 ; CHECK: $ymm0 = VUNPCKLPDYrr $ymm0, $ymm1399 $ymm0 = VUNPCKLPDZ256rr $ymm0, $ymm1400 ; CHECK: $ymm0 = VUNPCKLPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg401 $ymm0 = VUNPCKLPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg402 ; CHECK: $ymm0 = VUNPCKLPSYrr $ymm0, $ymm1403 $ymm0 = VUNPCKLPSZ256rr $ymm0, $ymm1404 ; CHECK: $ymm0 = VSUBPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr405 $ymm0 = VSUBPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr406 ; CHECK: $ymm0 = VSUBPDYrr $ymm0, $ymm1, implicit $mxcsr407 $ymm0 = VSUBPDZ256rr $ymm0, $ymm1, implicit $mxcsr408 ; CHECK: $ymm0 = VSUBPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr409 $ymm0 = VSUBPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr410 ; CHECK: $ymm0 = VSUBPSYrr $ymm0, $ymm1, implicit $mxcsr411 $ymm0 = VSUBPSZ256rr $ymm0, $ymm1, implicit $mxcsr412 ; CHECK: $ymm0 = VPUNPCKHBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg413 $ymm0 = VPUNPCKHBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg414 ; CHECK: $ymm0 = VPUNPCKHBWYrr $ymm0, $ymm1415 $ymm0 = VPUNPCKHBWZ256rr $ymm0, $ymm1416 ; CHECK: $ymm0 = VPUNPCKHDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg417 $ymm0 = VPUNPCKHDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg418 ; CHECK: $ymm0 = VPUNPCKHDQYrr $ymm0, $ymm1419 $ymm0 = VPUNPCKHDQZ256rr $ymm0, $ymm1420 ; CHECK: $ymm0 = VPUNPCKHQDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg421 $ymm0 = VPUNPCKHQDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg422 ; CHECK: $ymm0 = VPUNPCKHQDQYrr $ymm0, $ymm1423 $ymm0 = VPUNPCKHQDQZ256rr $ymm0, $ymm1424 ; CHECK: $ymm0 = VPUNPCKHWDYrm $ymm0, $rip, 1, $noreg, 0, $noreg425 $ymm0 = VPUNPCKHWDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg426 ; CHECK: $ymm0 = VPUNPCKHWDYrr $ymm0, $ymm1427 $ymm0 = VPUNPCKHWDZ256rr $ymm0, $ymm1428 ; CHECK: $ymm0 = VPUNPCKLBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg429 $ymm0 = VPUNPCKLBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg430 ; CHECK: $ymm0 = VPUNPCKLBWYrr $ymm0, $ymm1431 $ymm0 = VPUNPCKLBWZ256rr $ymm0, $ymm1432 ; CHECK: $ymm0 = VPUNPCKLDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg433 $ymm0 = VPUNPCKLDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg434 ; CHECK: $ymm0 = VPUNPCKLDQYrr $ymm0, $ymm1435 $ymm0 = VPUNPCKLDQZ256rr $ymm0, $ymm1436 ; CHECK: $ymm0 = VPUNPCKLQDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg437 $ymm0 = VPUNPCKLQDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg438 ; CHECK: $ymm0 = VPUNPCKLQDQYrr $ymm0, $ymm1439 $ymm0 = VPUNPCKLQDQZ256rr $ymm0, $ymm1440 ; CHECK: $ymm0 = VPUNPCKLWDYrm $ymm0, $rip, 1, $noreg, 0, $noreg441 $ymm0 = VPUNPCKLWDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg442 ; CHECK: $ymm0 = VPUNPCKLWDYrr $ymm0, $ymm1443 $ymm0 = VPUNPCKLWDZ256rr $ymm0, $ymm1444 ; CHECK: $ymm0 = VFMADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr445 $ymm0 = VFMADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr446 ; CHECK: $ymm0 = VFMADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr447 $ymm0 = VFMADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr448 ; CHECK: $ymm0 = VFMADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr449 $ymm0 = VFMADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr450 ; CHECK: $ymm0 = VFMADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr451 $ymm0 = VFMADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr452 ; CHECK: $ymm0 = VFMADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr453 $ymm0 = VFMADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr454 ; CHECK: $ymm0 = VFMADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr455 $ymm0 = VFMADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr456 ; CHECK: $ymm0 = VFMADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr457 $ymm0 = VFMADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr458 ; CHECK: $ymm0 = VFMADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr459 $ymm0 = VFMADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr460 ; CHECK: $ymm0 = VFMADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr461 $ymm0 = VFMADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr462 ; CHECK: $ymm0 = VFMADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr463 $ymm0 = VFMADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr464 ; CHECK: $ymm0 = VFMADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr465 $ymm0 = VFMADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr466 ; CHECK: $ymm0 = VFMADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr467 $ymm0 = VFMADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr468 ; CHECK: $ymm0 = VFMADDSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr469 $ymm0 = VFMADDSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr470 ; CHECK: $ymm0 = VFMADDSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr471 $ymm0 = VFMADDSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr472 ; CHECK: $ymm0 = VFMADDSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr473 $ymm0 = VFMADDSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr474 ; CHECK: $ymm0 = VFMADDSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr475 $ymm0 = VFMADDSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr476 ; CHECK: $ymm0 = VFMADDSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr477 $ymm0 = VFMADDSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr478 ; CHECK: $ymm0 = VFMADDSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr479 $ymm0 = VFMADDSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr480 ; CHECK: $ymm0 = VFMADDSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr481 $ymm0 = VFMADDSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr482 ; CHECK: $ymm0 = VFMADDSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr483 $ymm0 = VFMADDSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr484 ; CHECK: $ymm0 = VFMADDSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr485 $ymm0 = VFMADDSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr486 ; CHECK: $ymm0 = VFMADDSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr487 $ymm0 = VFMADDSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr488 ; CHECK: $ymm0 = VFMADDSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr489 $ymm0 = VFMADDSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr490 ; CHECK: $ymm0 = VFMADDSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr491 $ymm0 = VFMADDSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr492 ; CHECK: $ymm0 = VFMSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr493 $ymm0 = VFMSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr494 ; CHECK: $ymm0 = VFMSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr495 $ymm0 = VFMSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr496 ; CHECK: $ymm0 = VFMSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr497 $ymm0 = VFMSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr498 ; CHECK: $ymm0 = VFMSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr499 $ymm0 = VFMSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr500 ; CHECK: $ymm0 = VFMSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr501 $ymm0 = VFMSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr502 ; CHECK: $ymm0 = VFMSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr503 $ymm0 = VFMSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr504 ; CHECK: $ymm0 = VFMSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr505 $ymm0 = VFMSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr506 ; CHECK: $ymm0 = VFMSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr507 $ymm0 = VFMSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr508 ; CHECK: $ymm0 = VFMSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr509 $ymm0 = VFMSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr510 ; CHECK: $ymm0 = VFMSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr511 $ymm0 = VFMSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr512 ; CHECK: $ymm0 = VFMSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr513 $ymm0 = VFMSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr514 ; CHECK: $ymm0 = VFMSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr515 $ymm0 = VFMSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr516 ; CHECK: $ymm0 = VFMSUBADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr517 $ymm0 = VFMSUBADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr518 ; CHECK: $ymm0 = VFMSUBADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr519 $ymm0 = VFMSUBADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr520 ; CHECK: $ymm0 = VFMSUBADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr521 $ymm0 = VFMSUBADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr522 ; CHECK: $ymm0 = VFMSUBADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr523 $ymm0 = VFMSUBADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr524 ; CHECK: $ymm0 = VFMSUBADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr525 $ymm0 = VFMSUBADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr526 ; CHECK: $ymm0 = VFMSUBADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr527 $ymm0 = VFMSUBADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr528 ; CHECK: $ymm0 = VFMSUBADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr529 $ymm0 = VFMSUBADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr530 ; CHECK: $ymm0 = VFMSUBADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr531 $ymm0 = VFMSUBADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr532 ; CHECK: $ymm0 = VFMSUBADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr533 $ymm0 = VFMSUBADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr534 ; CHECK: $ymm0 = VFMSUBADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr535 $ymm0 = VFMSUBADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr536 ; CHECK: $ymm0 = VFMSUBADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr537 $ymm0 = VFMSUBADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr538 ; CHECK: $ymm0 = VFMSUBADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr539 $ymm0 = VFMSUBADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr540 ; CHECK: $ymm0 = VFNMADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr541 $ymm0 = VFNMADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr542 ; CHECK: $ymm0 = VFNMADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr543 $ymm0 = VFNMADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr544 ; CHECK: $ymm0 = VFNMADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr545 $ymm0 = VFNMADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr546 ; CHECK: $ymm0 = VFNMADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr547 $ymm0 = VFNMADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr548 ; CHECK: $ymm0 = VFNMADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr549 $ymm0 = VFNMADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr550 ; CHECK: $ymm0 = VFNMADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr551 $ymm0 = VFNMADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr552 ; CHECK: $ymm0 = VFNMADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr553 $ymm0 = VFNMADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr554 ; CHECK: $ymm0 = VFNMADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr555 $ymm0 = VFNMADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr556 ; CHECK: $ymm0 = VFNMADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr557 $ymm0 = VFNMADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr558 ; CHECK: $ymm0 = VFNMADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr559 $ymm0 = VFNMADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr560 ; CHECK: $ymm0 = VFNMADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr561 $ymm0 = VFNMADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr562 ; CHECK: $ymm0 = VFNMADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr563 $ymm0 = VFNMADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr564 ; CHECK: $ymm0 = VFNMSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr565 $ymm0 = VFNMSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr566 ; CHECK: $ymm0 = VFNMSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr567 $ymm0 = VFNMSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr568 ; CHECK: $ymm0 = VFNMSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr569 $ymm0 = VFNMSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr570 ; CHECK: $ymm0 = VFNMSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr571 $ymm0 = VFNMSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr572 ; CHECK: $ymm0 = VFNMSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr573 $ymm0 = VFNMSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr574 ; CHECK: $ymm0 = VFNMSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr575 $ymm0 = VFNMSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr576 ; CHECK: $ymm0 = VFNMSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr577 $ymm0 = VFNMSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr578 ; CHECK: $ymm0 = VFNMSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr579 $ymm0 = VFNMSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr580 ; CHECK: $ymm0 = VFNMSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr581 $ymm0 = VFNMSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr582 ; CHECK: $ymm0 = VFNMSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr583 $ymm0 = VFNMSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr584 ; CHECK: $ymm0 = VFNMSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr585 $ymm0 = VFNMSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr586 ; CHECK: $ymm0 = VFNMSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr587 $ymm0 = VFNMSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr588 ; CHECK: $ymm0 = VPSRADYri $ymm0, 7589 $ymm0 = VPSRADZ256ri $ymm0, 7590 ; CHECK: $ymm0 = VPSRADYrm $ymm0, $rip, 1, $noreg, 0, $noreg591 $ymm0 = VPSRADZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg592 ; CHECK: $ymm0 = VPSRADYrr $ymm0, $xmm1593 $ymm0 = VPSRADZ256rr $ymm0, $xmm1594 ; CHECK: $ymm0 = VPSRAVDYrm $ymm0, $rip, 1, $noreg, 0, $noreg595 $ymm0 = VPSRAVDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg596 ; CHECK: $ymm0 = VPSRAVDYrr $ymm0, $ymm1597 $ymm0 = VPSRAVDZ256rr $ymm0, $ymm1598 ; CHECK: $ymm0 = VPSRAWYri $ymm0, 7599 $ymm0 = VPSRAWZ256ri $ymm0, 7600 ; CHECK: $ymm0 = VPSRAWYrm $ymm0, $rip, 1, $noreg, 0, $noreg601 $ymm0 = VPSRAWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg602 ; CHECK: $ymm0 = VPSRAWYrr $ymm0, $xmm1603 $ymm0 = VPSRAWZ256rr $ymm0, $xmm1604 ; CHECK: $ymm0 = VPSRLDQYri $ymm0, 7605 $ymm0 = VPSRLDQZ256ri $ymm0, 7606 ; CHECK: $ymm0 = VPSRLDYri $ymm0, 7607 $ymm0 = VPSRLDZ256ri $ymm0, 7608 ; CHECK: $ymm0 = VPSRLDYrm $ymm0, $rip, 1, $noreg, 0, $noreg609 $ymm0 = VPSRLDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg610 ; CHECK: $ymm0 = VPSRLDYrr $ymm0, $xmm1611 $ymm0 = VPSRLDZ256rr $ymm0, $xmm1612 ; CHECK: $ymm0 = VPSRLQYri $ymm0, 7613 $ymm0 = VPSRLQZ256ri $ymm0, 7614 ; CHECK: $ymm0 = VPSRLQYrm $ymm0, $rip, 1, $noreg, 0, $noreg615 $ymm0 = VPSRLQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg616 ; CHECK: $ymm0 = VPSRLQYrr $ymm0, $xmm1617 $ymm0 = VPSRLQZ256rr $ymm0, $xmm1618 ; CHECK: $ymm0 = VPSRLVDYrm $ymm0, $rip, 1, $noreg, 0, $noreg619 $ymm0 = VPSRLVDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg620 ; CHECK: $ymm0 = VPSRLVDYrr $ymm0, $ymm1621 $ymm0 = VPSRLVDZ256rr $ymm0, $ymm1622 ; CHECK: $ymm0 = VPSRLVQYrm $ymm0, $rip, 1, $noreg, 0, $noreg623 $ymm0 = VPSRLVQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg624 ; CHECK: $ymm0 = VPSRLVQYrr $ymm0, $ymm1625 $ymm0 = VPSRLVQZ256rr $ymm0, $ymm1626 ; CHECK: $ymm0 = VPSRLWYri $ymm0, 7627 $ymm0 = VPSRLWZ256ri $ymm0, 7628 ; CHECK: $ymm0 = VPSRLWYrm $ymm0, $rip, 1, $noreg, 0, $noreg629 $ymm0 = VPSRLWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg630 ; CHECK: $ymm0 = VPSRLWYrr $ymm0, $xmm1631 $ymm0 = VPSRLWZ256rr $ymm0, $xmm1632 ; CHECK: $ymm0 = VPMOVSXBDYrm $rip, 1, $noreg, 0, $noreg633 $ymm0 = VPMOVSXBDZ256rm $rip, 1, $noreg, 0, $noreg634 ; CHECK: $ymm0 = VPMOVSXBDYrr $xmm0635 $ymm0 = VPMOVSXBDZ256rr $xmm0636 ; CHECK: $ymm0 = VPMOVSXBQYrm $rip, 1, $noreg, 0, $noreg637 $ymm0 = VPMOVSXBQZ256rm $rip, 1, $noreg, 0, $noreg638 ; CHECK: $ymm0 = VPMOVSXBQYrr $xmm0639 $ymm0 = VPMOVSXBQZ256rr $xmm0640 ; CHECK: $ymm0 = VPMOVSXBWYrm $rip, 1, $noreg, 0, $noreg641 $ymm0 = VPMOVSXBWZ256rm $rip, 1, $noreg, 0, $noreg642 ; CHECK: $ymm0 = VPMOVSXBWYrr $xmm0643 $ymm0 = VPMOVSXBWZ256rr $xmm0644 ; CHECK: $ymm0 = VPMOVSXDQYrm $rip, 1, $noreg, 0, $noreg645 $ymm0 = VPMOVSXDQZ256rm $rip, 1, $noreg, 0, $noreg646 ; CHECK: $ymm0 = VPMOVSXDQYrr $xmm0647 $ymm0 = VPMOVSXDQZ256rr $xmm0648 ; CHECK: $ymm0 = VPMOVSXWDYrm $rip, 1, $noreg, 0, $noreg649 $ymm0 = VPMOVSXWDZ256rm $rip, 1, $noreg, 0, $noreg650 ; CHECK: $ymm0 = VPMOVSXWDYrr $xmm0651 $ymm0 = VPMOVSXWDZ256rr $xmm0652 ; CHECK: $ymm0 = VPMOVSXWQYrm $rip, 1, $noreg, 0, $noreg653 $ymm0 = VPMOVSXWQZ256rm $rip, 1, $noreg, 0, $noreg654 ; CHECK: $ymm0 = VPMOVSXWQYrr $xmm0655 $ymm0 = VPMOVSXWQZ256rr $xmm0656 ; CHECK: $ymm0 = VPMOVZXBDYrm $rip, 1, $noreg, 0, $noreg657 $ymm0 = VPMOVZXBDZ256rm $rip, 1, $noreg, 0, $noreg658 ; CHECK: $ymm0 = VPMOVZXBDYrr $xmm0659 $ymm0 = VPMOVZXBDZ256rr $xmm0660 ; CHECK: $ymm0 = VPMOVZXBQYrm $rip, 1, $noreg, 0, $noreg661 $ymm0 = VPMOVZXBQZ256rm $rip, 1, $noreg, 0, $noreg662 ; CHECK: $ymm0 = VPMOVZXBQYrr $xmm0663 $ymm0 = VPMOVZXBQZ256rr $xmm0664 ; CHECK: $ymm0 = VPMOVZXBWYrm $rip, 1, $noreg, 0, $noreg665 $ymm0 = VPMOVZXBWZ256rm $rip, 1, $noreg, 0, $noreg666 ; CHECK: $ymm0 = VPMOVZXBWYrr $xmm0667 $ymm0 = VPMOVZXBWZ256rr $xmm0668 ; CHECK: $ymm0 = VPMOVZXDQYrm $rip, 1, $noreg, 0, $noreg669 $ymm0 = VPMOVZXDQZ256rm $rip, 1, $noreg, 0, $noreg670 ; CHECK: $ymm0 = VPMOVZXDQYrr $xmm0671 $ymm0 = VPMOVZXDQZ256rr $xmm0672 ; CHECK: $ymm0 = VPMOVZXWDYrm $rip, 1, $noreg, 0, $noreg673 $ymm0 = VPMOVZXWDZ256rm $rip, 1, $noreg, 0, $noreg674 ; CHECK: $ymm0 = VPMOVZXWDYrr $xmm0675 $ymm0 = VPMOVZXWDZ256rr $xmm0676 ; CHECK: $ymm0 = VPMOVZXWQYrm $rip, 1, $noreg, 0, $noreg677 $ymm0 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg678 ; CHECK: $ymm0 = VPMOVZXWQYrr $xmm0679 $ymm0 = VPMOVZXWQZ256rr $xmm0680 ; CHECK: $ymm0 = VBROADCASTF128rm $rip, 1, $noreg, 0, $noreg681 $ymm0 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg682 ; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg683 $ymm0 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg684 ; CHECK: $ymm0 = VBROADCASTSDYrr $xmm0685 $ymm0 = VBROADCASTF32X2Z256rr $xmm0686 ; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg687 $ymm0 = VBROADCASTSDZ256rm $rip, 1, $noreg, 0, $noreg688 ; CHECK: $ymm0 = VBROADCASTSDYrr $xmm0689 $ymm0 = VBROADCASTSDZ256rr $xmm0690 ; CHECK: $ymm0 = VBROADCASTSSYrm $rip, 1, $noreg, 0, $noreg691 $ymm0 = VBROADCASTSSZ256rm $rip, 1, $noreg, 0, $noreg692 ; CHECK: $ymm0 = VBROADCASTSSYrr $xmm0693 $ymm0 = VBROADCASTSSZ256rr $xmm0694 ; CHECK: $ymm0 = VPBROADCASTBYrm $rip, 1, $noreg, 0, $noreg695 $ymm0 = VPBROADCASTBZ256rm $rip, 1, $noreg, 0, $noreg696 ; CHECK: $ymm0 = VPBROADCASTBYrr $xmm0697 $ymm0 = VPBROADCASTBZ256rr $xmm0698 ; CHECK: $ymm0 = VPBROADCASTDYrm $rip, 1, $noreg, 0, $noreg699 $ymm0 = VPBROADCASTDZ256rm $rip, 1, $noreg, 0, $noreg700 ; CHECK: $ymm0 = VPBROADCASTDYrr $xmm0701 $ymm0 = VPBROADCASTDZ256rr $xmm0702 ; CHECK: $ymm0 = VPBROADCASTWYrm $rip, 1, $noreg, 0, $noreg703 $ymm0 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg704 ; CHECK: $ymm0 = VPBROADCASTWYrr $xmm0705 $ymm0 = VPBROADCASTWZ256rr $xmm0706 ; CHECK: $ymm0 = VBROADCASTI128rm $rip, 1, $noreg, 0, $noreg707 $ymm0 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg708 ; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg709 $ymm0 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg710 ; CHECK: $ymm0 = VPBROADCASTQYrr $xmm0711 $ymm0 = VBROADCASTI32X2Z256rr $xmm0712 ; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg713 $ymm0 = VPBROADCASTQZ256rm $rip, 1, $noreg, 0, $noreg714 ; CHECK: $ymm0 = VPBROADCASTQYrr $xmm0715 $ymm0 = VPBROADCASTQZ256rr $xmm0716 ; CHECK: $ymm0 = VPABSBYrm $rip, 1, $noreg, 0, $noreg717 $ymm0 = VPABSBZ256rm $rip, 1, $noreg, 0, $noreg718 ; CHECK: $ymm0 = VPABSBYrr $ymm0719 $ymm0 = VPABSBZ256rr $ymm0720 ; CHECK: $ymm0 = VPABSDYrm $rip, 1, $noreg, 0, $noreg721 $ymm0 = VPABSDZ256rm $rip, 1, $noreg, 0, $noreg722 ; CHECK: $ymm0 = VPABSDYrr $ymm0723 $ymm0 = VPABSDZ256rr $ymm0724 ; CHECK: $ymm0 = VPABSWYrm $rip, 1, $noreg, 0, $noreg725 $ymm0 = VPABSWZ256rm $rip, 1, $noreg, 0, $noreg726 ; CHECK: $ymm0 = VPABSWYrr $ymm0727 $ymm0 = VPABSWZ256rr $ymm0728 ; CHECK: $ymm0 = VPSADBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg729 $ymm0 = VPSADBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg730 ; CHECK: $ymm0 = VPSADBWYrr $ymm0, $ymm1731 $ymm0 = VPSADBWZ256rr $ymm0, $ymm1732 ; CHECK: $ymm0 = VPERMDYrm $ymm0, $rdi, 1, $noreg, 0, $noreg733 $ymm0 = VPERMDZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg734 ; CHECK: $ymm0 = VPERMDYrr $ymm1, $ymm0735 $ymm0 = VPERMDZ256rr $ymm1, $ymm0736 ; CHECK: $ymm0 = VPERMILPDYmi $rdi, 1, $noreg, 0, $noreg, 7737 $ymm0 = VPERMILPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7738 ; CHECK: $ymm0 = VPERMILPDYri $ymm0, 7739 $ymm0 = VPERMILPDZ256ri $ymm0, 7740 ; CHECK: $ymm0 = VPERMILPDYrm $ymm0, $rdi, 1, $noreg, 0, $noreg741 $ymm0 = VPERMILPDZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg742 ; CHECK: $ymm0 = VPERMILPDYrr $ymm1, $ymm0743 $ymm0 = VPERMILPDZ256rr $ymm1, $ymm0744 ; CHECK: $ymm0 = VPERMILPSYmi $rdi, 1, $noreg, 0, $noreg, 7745 $ymm0 = VPERMILPSZ256mi $rdi, 1, $noreg, 0, $noreg, 7746 ; CHECK: $ymm0 = VPERMILPSYri $ymm0, 7747 $ymm0 = VPERMILPSZ256ri $ymm0, 7748 ; CHECK: $ymm0 = VPERMILPSYrm $ymm0, $rdi, 1, $noreg, 0, $noreg749 $ymm0 = VPERMILPSZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg750 ; CHECK: $ymm0 = VPERMILPSYrr $ymm1, $ymm0751 $ymm0 = VPERMILPSZ256rr $ymm1, $ymm0752 ; CHECK: $ymm0 = VPERMPDYmi $rdi, 1, $noreg, 0, $noreg, 7753 $ymm0 = VPERMPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7754 ; CHECK: $ymm0 = VPERMPDYri $ymm0, 7755 $ymm0 = VPERMPDZ256ri $ymm0, 7756 ; CHECK: $ymm0 = VPERMPSYrm $ymm0, $rdi, 1, $noreg, 0, $noreg757 $ymm0 = VPERMPSZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg758 ; CHECK: $ymm0 = VPERMPSYrr $ymm1, $ymm0759 $ymm0 = VPERMPSZ256rr $ymm1, $ymm0760 ; CHECK: $ymm0 = VPERMQYmi $rdi, 1, $noreg, 0, $noreg, 7761 $ymm0 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 7762 ; CHECK: $ymm0 = VPERMQYri $ymm0, 7763 $ymm0 = VPERMQZ256ri $ymm0, 7764 ; CHECK: $ymm0 = VPSLLDQYri $ymm0, 14765 $ymm0 = VPSLLDQZ256ri $ymm0, 14766 ; CHECK: $ymm0 = VPSLLDYri $ymm0, 7767 $ymm0 = VPSLLDZ256ri $ymm0, 7768 ; CHECK: $ymm0 = VPSLLDYrm $ymm0, $rip, 1, $noreg, 0, $noreg769 $ymm0 = VPSLLDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg770 ; CHECK: $ymm0 = VPSLLDYrr $ymm0, $xmm0771 $ymm0 = VPSLLDZ256rr $ymm0, $xmm0772 ; CHECK: $ymm0 = VPSLLQYri $ymm0, 7773 $ymm0 = VPSLLQZ256ri $ymm0, 7774 ; CHECK: $ymm0 = VPSLLQYrm $ymm0, $rip, 1, $noreg, 0, $noreg775 $ymm0 = VPSLLQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg776 ; CHECK: $ymm0 = VPSLLQYrr $ymm0, $xmm0777 $ymm0 = VPSLLQZ256rr $ymm0, $xmm0778 ; CHECK: $ymm0 = VPSLLVDYrm $ymm0, $rip, 1, $noreg, 0, $noreg779 $ymm0 = VPSLLVDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg780 ; CHECK: $ymm0 = VPSLLVDYrr $ymm0, $ymm0781 $ymm0 = VPSLLVDZ256rr $ymm0, $ymm0782 ; CHECK: $ymm0 = VPSLLVQYrm $ymm0, $rip, 1, $noreg, 0, $noreg783 $ymm0 = VPSLLVQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg784 ; CHECK: $ymm0 = VPSLLVQYrr $ymm0, $ymm0785 $ymm0 = VPSLLVQZ256rr $ymm0, $ymm0786 ; CHECK: $ymm0 = VPSLLWYri $ymm0, 7787 $ymm0 = VPSLLWZ256ri $ymm0, 7788 ; CHECK: $ymm0 = VPSLLWYrm $ymm0, $rip, 1, $noreg, 0, $noreg789 $ymm0 = VPSLLWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg790 ; CHECK: $ymm0 = VPSLLWYrr $ymm0, $xmm0791 $ymm0 = VPSLLWZ256rr $ymm0, $xmm0792 ; CHECK: $ymm0 = VCVTDQ2PDYrm $rdi, 1, $noreg, 0, $noreg793 $ymm0 = VCVTDQ2PDZ256rm $rdi, 1, $noreg, 0, $noreg794 ; CHECK: $ymm0 = VCVTDQ2PDYrr $xmm0795 $ymm0 = VCVTDQ2PDZ256rr $xmm0796 ; CHECK: $ymm0 = VCVTDQ2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr797 $ymm0 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr798 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr799 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr800 ; CHECK: $xmm0 = VCVTPD2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr801 $xmm0 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr802 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr803 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr804 ; CHECK: $xmm0 = VCVTPD2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr805 $xmm0 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr806 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr807 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr808 ; CHECK: $ymm0 = VCVTPS2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr809 $ymm0 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr810 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr811 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr812 ; CHECK: $ymm0 = VCVTPS2PDYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr813 $ymm0 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr814 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr815 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr816 ; CHECK: VCVTPS2PHYmr $rdi, 1, $noreg, 0, $noreg, $ymm0, 0, implicit $mxcsr817 VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0, 0, implicit $mxcsr818 ; CHECK: $xmm0 = VCVTPS2PHYrr $ymm0, 0, implicit $mxcsr819 $xmm0 = VCVTPS2PHZ256rr $ymm0, 0, implicit $mxcsr820 ; CHECK: $ymm0 = VCVTPH2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr821 $ymm0 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr822 ; CHECK: $ymm0 = VCVTPH2PSYrr $xmm0, implicit $mxcsr823 $ymm0 = VCVTPH2PSZ256rr $xmm0, implicit $mxcsr824 ; CHECK: $xmm0 = VCVTTPD2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr825 $xmm0 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr826 ; CHECK: $xmm0 = VCVTTPD2DQYrr $ymm0, implicit $mxcsr827 $xmm0 = VCVTTPD2DQZ256rr $ymm0, implicit $mxcsr828 ; CHECK: $ymm0 = VCVTTPS2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr829 $ymm0 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr830 ; CHECK: $ymm0 = VCVTTPS2DQYrr $ymm0, implicit $mxcsr831 $ymm0 = VCVTTPS2DQZ256rr $ymm0, implicit $mxcsr832 ; CHECK: $ymm0 = VSQRTPDYm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr833 $ymm0 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr834 ; CHECK: $ymm0 = VSQRTPDYr $ymm0, implicit $mxcsr835 $ymm0 = VSQRTPDZ256r $ymm0, implicit $mxcsr836 ; CHECK: $ymm0 = VSQRTPSYm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr837 $ymm0 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr838 ; CHECK: $ymm0 = VSQRTPSYr $ymm0, implicit $mxcsr839 $ymm0 = VSQRTPSZ256r $ymm0, implicit $mxcsr840 ; CHECK: $ymm0 = VPALIGNRYrmi $ymm0, $rdi, 1, $noreg, 0, $noreg, 1841 $ymm0 = VPALIGNRZ256rmi $ymm0, $rdi, 1, $noreg, 0, $noreg, 1842 ; CHECK: $ymm0 = VPALIGNRYrri $ymm0, $ymm1, 1843 $ymm0 = VPALIGNRZ256rri $ymm0, $ymm1, 1844 ; CHECK: $ymm0 = VMOVUPSYrm $rdi, 1, $noreg, 0, $noreg845 $ymm0 = VMOVUPSZ256rm $rdi, 1, $noreg, 0, $noreg846 ; CHECK: $ymm0 = VMOVUPSYrr $ymm0847 $ymm0 = VMOVUPSZ256rr $ymm0848 ; CHECK: $ymm0 = VPSHUFBYrm $ymm0, $rdi, 1, $noreg, 0, $noreg849 $ymm0 = VPSHUFBZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg850 ; CHECK: $ymm0 = VPSHUFBYrr $ymm0, $ymm1851 $ymm0 = VPSHUFBZ256rr $ymm0, $ymm1852 ; CHECK: $ymm0 = VPSHUFDYmi $rdi, 1, $noreg, 0, $noreg, -24853 $ymm0 = VPSHUFDZ256mi $rdi, 1, $noreg, 0, $noreg, -24854 ; CHECK: $ymm0 = VPSHUFDYri $ymm0, -24855 $ymm0 = VPSHUFDZ256ri $ymm0, -24856 ; CHECK: $ymm0 = VPSHUFHWYmi $rdi, 1, $noreg, 0, $noreg, -24857 $ymm0 = VPSHUFHWZ256mi $rdi, 1, $noreg, 0, $noreg, -24858 ; CHECK: $ymm0 = VPSHUFHWYri $ymm0, -24859 $ymm0 = VPSHUFHWZ256ri $ymm0, -24860 ; CHECK: $ymm0 = VPSHUFLWYmi $rdi, 1, $noreg, 0, $noreg, -24861 $ymm0 = VPSHUFLWZ256mi $rdi, 1, $noreg, 0, $noreg, -24862 ; CHECK: $ymm0 = VPSHUFLWYri $ymm0, -24863 $ymm0 = VPSHUFLWZ256ri $ymm0, -24864 ; CHECK: $ymm0 = VSHUFPDYrmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24865 $ymm0 = VSHUFPDZ256rmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24866 ; CHECK: $ymm0 = VSHUFPDYrri $ymm0, $ymm1, -24867 $ymm0 = VSHUFPDZ256rri $ymm0, $ymm1, -24868 ; CHECK: $ymm0 = VSHUFPSYrmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24869 $ymm0 = VSHUFPSZ256rmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24870 ; CHECK: $ymm0 = VSHUFPSYrri $ymm0, $ymm1, -24871 $ymm0 = VSHUFPSZ256rri $ymm0, $ymm1, -24872 ; CHECK: $ymm0 = VROUNDPDYmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr873 $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr874 ; CHECK: $ymm0 = VROUNDPDYri $ymm0, 15, implicit $mxcsr875 $ymm0 = VRNDSCALEPDZ256rri $ymm0, 15, implicit $mxcsr876 ; CHECK: $ymm0 = VROUNDPSYmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr877 $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr878 ; CHECK: $ymm0 = VROUNDPSYri $ymm0, 15, implicit $mxcsr879 $ymm0 = VRNDSCALEPSZ256rri $ymm0, 15, implicit $mxcsr880 ; CHECK: $ymm0 = VPERM2F128rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 32881 $ymm0 = VSHUFF32X4Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228882 ; CHECK: $ymm0 = VPERM2F128rri $ymm0, $ymm1, 32883 $ymm0 = VSHUFF32X4Z256rri $ymm0, $ymm1, 228884 ; CHECK: $ymm0 = VPERM2F128rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 32885 $ymm0 = VSHUFF64X2Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228886 ; CHECK: $ymm0 = VPERM2F128rri $ymm0, $ymm1, 32887 $ymm0 = VSHUFF64X2Z256rri $ymm0, $ymm1, 228888 ; CHECK: $ymm0 = VPERM2I128rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 32889 $ymm0 = VSHUFI32X4Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228890 ; CHECK: $ymm0 = VPERM2I128rri $ymm0, $ymm1, 32891 $ymm0 = VSHUFI32X4Z256rri $ymm0, $ymm1, 228892 ; CHECK: $ymm0 = VPERM2I128rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 32893 $ymm0 = VSHUFI64X2Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228894 ; CHECK: $ymm0 = VPERM2I128rri $ymm0, $ymm1, 32895 $ymm0 = VSHUFI64X2Z256rri $ymm0, $ymm1, 228896 897 RET64898...899---900 # CHECK-LABEL: name: evex_z128_to_vex_test901 # CHECK: bb.0:902 903name: evex_z128_to_vex_test904body: |905 bb.0:906 ; CHECK: VMOVAPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0907 VMOVAPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0908 ; CHECK: $xmm0 = VMOVAPDrm $rip, 1, $noreg, 0, $noreg909 $xmm0 = VMOVAPDZ128rm $rip, 1, $noreg, 0, $noreg910 ; CHECK: $xmm0 = VMOVAPDrr $xmm0911 $xmm0 = VMOVAPDZ128rr $xmm0912 ; CHECK: VMOVAPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0913 VMOVAPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0914 ; CHECK: $xmm0 = VMOVAPSrm $rip, 1, $noreg, 0, $noreg915 $xmm0 = VMOVAPSZ128rm $rip, 1, $noreg, 0, $noreg916 ; CHECK: $xmm0 = VMOVAPSrr $xmm0917 $xmm0 = VMOVAPSZ128rr $xmm0918 ; CHECK: VMOVDQAmr $rdi, 1, $noreg, 0, $noreg, $xmm0919 VMOVDQA32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0920 ; CHECK: $xmm0 = VMOVDQArm $rip, 1, $noreg, 0, $noreg921 $xmm0 = VMOVDQA32Z128rm $rip, 1, $noreg, 0, $noreg922 ; CHECK: $xmm0 = VMOVDQArr $xmm0923 $xmm0 = VMOVDQA32Z128rr $xmm0924 ; CHECK: VMOVDQAmr $rdi, 1, $noreg, 0, $noreg, $xmm0925 VMOVDQA64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0926 ; CHECK: $xmm0 = VMOVDQArm $rip, 1, $noreg, 0, $noreg927 $xmm0 = VMOVDQA64Z128rm $rip, 1, $noreg, 0, $noreg928 ; CHECK: $xmm0 = VMOVDQArr $xmm0929 $xmm0 = VMOVDQA64Z128rr $xmm0930 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0931 VMOVDQU16Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0932 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg933 $xmm0 = VMOVDQU16Z128rm $rip, 1, $noreg, 0, $noreg934 ; CHECK: $xmm0 = VMOVDQUrr $xmm0935 $xmm0 = VMOVDQU16Z128rr $xmm0936 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0937 VMOVDQU32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0938 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg939 $xmm0 = VMOVDQU32Z128rm $rip, 1, $noreg, 0, $noreg940 ; CHECK: $xmm0 = VMOVDQUrr $xmm0941 $xmm0 = VMOVDQU32Z128rr $xmm0942 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0943 VMOVDQU64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0944 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg945 $xmm0 = VMOVDQU64Z128rm $rip, 1, $noreg, 0, $noreg946 ; CHECK: $xmm0 = VMOVDQUrr $xmm0947 $xmm0 = VMOVDQU64Z128rr $xmm0948 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0949 VMOVDQU8Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0950 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg951 $xmm0 = VMOVDQU8Z128rm $rip, 1, $noreg, 0, $noreg952 ; CHECK: $xmm0 = VMOVDQUrr $xmm0953 $xmm0 = VMOVDQU8Z128rr $xmm0954 ; CHECK: $xmm0 = VMOVNTDQArm $rip, 1, $noreg, 0, $noreg955 $xmm0 = VMOVNTDQAZ128rm $rip, 1, $noreg, 0, $noreg956 ; CHECK: VMOVUPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0957 VMOVUPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0958 ; CHECK: $xmm0 = VMOVUPDrm $rip, 1, $noreg, 0, $noreg959 $xmm0 = VMOVUPDZ128rm $rip, 1, $noreg, 0, $noreg960 ; CHECK: $xmm0 = VMOVUPDrr $xmm0961 $xmm0 = VMOVUPDZ128rr $xmm0962 ; CHECK: VMOVUPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0963 VMOVUPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0964 ; CHECK: $xmm0 = VMOVUPSrm $rip, 1, $noreg, 0, $noreg965 $xmm0 = VMOVUPSZ128rm $rip, 1, $noreg, 0, $noreg966 ; CHECK: $xmm0 = VMOVUPSrr $xmm0967 $xmm0 = VMOVUPSZ128rr $xmm0968 ; CHECK: VMOVNTDQmr $rdi, 1, $noreg, 0, $noreg, $xmm0969 VMOVNTDQZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0970 ; CHECK: VMOVNTPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0971 VMOVNTPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0972 ; CHECK: VMOVNTPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0973 VMOVNTPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0974 ; CHECK: $xmm0 = VPMOVSXBDrm $rip, 1, $noreg, 0, $noreg975 $xmm0 = VPMOVSXBDZ128rm $rip, 1, $noreg, 0, $noreg976 ; CHECK: $xmm0 = VPMOVSXBDrr $xmm0977 $xmm0 = VPMOVSXBDZ128rr $xmm0978 ; CHECK: $xmm0 = VPMOVSXBQrm $rip, 1, $noreg, 0, $noreg979 $xmm0 = VPMOVSXBQZ128rm $rip, 1, $noreg, 0, $noreg980 ; CHECK: $xmm0 = VPMOVSXBQrr $xmm0981 $xmm0 = VPMOVSXBQZ128rr $xmm0982 ; CHECK: $xmm0 = VPMOVSXBWrm $rip, 1, $noreg, 0, $noreg983 $xmm0 = VPMOVSXBWZ128rm $rip, 1, $noreg, 0, $noreg984 ; CHECK: $xmm0 = VPMOVSXBWrr $xmm0985 $xmm0 = VPMOVSXBWZ128rr $xmm0986 ; CHECK: $xmm0 = VPMOVSXDQrm $rip, 1, $noreg, 0, $noreg987 $xmm0 = VPMOVSXDQZ128rm $rip, 1, $noreg, 0, $noreg988 ; CHECK: $xmm0 = VPMOVSXDQrr $xmm0989 $xmm0 = VPMOVSXDQZ128rr $xmm0990 ; CHECK: $xmm0 = VPMOVSXWDrm $rip, 1, $noreg, 0, $noreg991 $xmm0 = VPMOVSXWDZ128rm $rip, 1, $noreg, 0, $noreg992 ; CHECK: $xmm0 = VPMOVSXWDrr $xmm0993 $xmm0 = VPMOVSXWDZ128rr $xmm0994 ; CHECK: $xmm0 = VPMOVSXWQrm $rip, 1, $noreg, 0, $noreg995 $xmm0 = VPMOVSXWQZ128rm $rip, 1, $noreg, 0, $noreg996 ; CHECK: $xmm0 = VPMOVSXWQrr $xmm0997 $xmm0 = VPMOVSXWQZ128rr $xmm0998 ; CHECK: $xmm0 = VPMOVZXBDrm $rip, 1, $noreg, 0, $noreg999 $xmm0 = VPMOVZXBDZ128rm $rip, 1, $noreg, 0, $noreg1000 ; CHECK: $xmm0 = VPMOVZXBDrr $xmm01001 $xmm0 = VPMOVZXBDZ128rr $xmm01002 ; CHECK: $xmm0 = VPMOVZXBQrm $rip, 1, $noreg, 0, $noreg1003 $xmm0 = VPMOVZXBQZ128rm $rip, 1, $noreg, 0, $noreg1004 ; CHECK: $xmm0 = VPMOVZXBQrr $xmm01005 $xmm0 = VPMOVZXBQZ128rr $xmm01006 ; CHECK: $xmm0 = VPMOVZXBWrm $rip, 1, $noreg, 0, $noreg1007 $xmm0 = VPMOVZXBWZ128rm $rip, 1, $noreg, 0, $noreg1008 ; CHECK: $xmm0 = VPMOVZXBWrr $xmm01009 $xmm0 = VPMOVZXBWZ128rr $xmm01010 ; CHECK: $xmm0 = VPMOVZXDQrm $rip, 1, $noreg, 0, $noreg1011 $xmm0 = VPMOVZXDQZ128rm $rip, 1, $noreg, 0, $noreg1012 ; CHECK: $xmm0 = VPMOVZXDQrr $xmm01013 $xmm0 = VPMOVZXDQZ128rr $xmm01014 ; CHECK: $xmm0 = VPMOVZXWDrm $rip, 1, $noreg, 0, $noreg1015 $xmm0 = VPMOVZXWDZ128rm $rip, 1, $noreg, 0, $noreg1016 ; CHECK: $xmm0 = VPMOVZXWDrr $xmm01017 $xmm0 = VPMOVZXWDZ128rr $xmm01018 ; CHECK: $xmm0 = VPMOVZXWQrm $rip, 1, $noreg, 0, $noreg1019 $xmm0 = VPMOVZXWQZ128rm $rip, 1, $noreg, 0, $noreg1020 ; CHECK: $xmm0 = VPMOVZXWQrr $xmm01021 $xmm0 = VPMOVZXWQZ128rr $xmm01022 ; CHECK: VMOVHPDmr $rdi, 1, $noreg, 0, $noreg, $xmm01023 VMOVHPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm01024 ; CHECK: $xmm0 = VMOVHPDrm $xmm0, $rdi, 1, $noreg, 0, $noreg1025 $xmm0 = VMOVHPDZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1026 ; CHECK: VMOVHPSmr $rdi, 1, $noreg, 0, $noreg, $xmm01027 VMOVHPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm01028 ; CHECK: $xmm0 = VMOVHPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg1029 $xmm0 = VMOVHPSZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1030 ; CHECK: VMOVLPDmr $rdi, 1, $noreg, 0, $noreg, $xmm01031 VMOVLPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm01032 ; CHECK: $xmm0 = VMOVLPDrm $xmm0, $rdi, 1, $noreg, 0, $noreg1033 $xmm0 = VMOVLPDZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1034 ; CHECK: VMOVLPSmr $rdi, 1, $noreg, 0, $noreg, $xmm01035 VMOVLPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm01036 ; CHECK: $xmm0 = VMOVLPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg1037 $xmm0 = VMOVLPSZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1038 ; CHECK: $xmm0 = VMAXCPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1039 $xmm0 = VMAXCPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1040 ; CHECK: $xmm0 = VMAXCPDrr $xmm0, $xmm1, implicit $mxcsr1041 $xmm0 = VMAXCPDZ128rr $xmm0, $xmm1, implicit $mxcsr1042 ; CHECK: $xmm0 = VMAXCPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1043 $xmm0 = VMAXCPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1044 ; CHECK: $xmm0 = VMAXCPSrr $xmm0, $xmm1, implicit $mxcsr1045 $xmm0 = VMAXCPSZ128rr $xmm0, $xmm1, implicit $mxcsr1046 ; CHECK: $xmm0 = VMAXPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1047 $xmm0 = VMAXPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1048 ; CHECK: $xmm0 = VMAXPDrr $xmm0, $xmm1, implicit $mxcsr1049 $xmm0 = VMAXPDZ128rr $xmm0, $xmm1, implicit $mxcsr1050 ; CHECK: $xmm0 = VMAXPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1051 $xmm0 = VMAXPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1052 ; CHECK: $xmm0 = VMAXPSrr $xmm0, $xmm1, implicit $mxcsr1053 $xmm0 = VMAXPSZ128rr $xmm0, $xmm1, implicit $mxcsr1054 ; CHECK: $xmm0 = VMINCPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1055 $xmm0 = VMINCPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1056 ; CHECK: $xmm0 = VMINCPDrr $xmm0, $xmm1, implicit $mxcsr1057 $xmm0 = VMINCPDZ128rr $xmm0, $xmm1, implicit $mxcsr1058 ; CHECK: $xmm0 = VMINCPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1059 $xmm0 = VMINCPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1060 ; CHECK: $xmm0 = VMINCPSrr $xmm0, $xmm1, implicit $mxcsr1061 $xmm0 = VMINCPSZ128rr $xmm0, $xmm1, implicit $mxcsr1062 ; CHECK: $xmm0 = VMINPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1063 $xmm0 = VMINPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1064 ; CHECK: $xmm0 = VMINPDrr $xmm0, $xmm1, implicit $mxcsr1065 $xmm0 = VMINPDZ128rr $xmm0, $xmm1, implicit $mxcsr1066 ; CHECK: $xmm0 = VMINPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1067 $xmm0 = VMINPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1068 ; CHECK: $xmm0 = VMINPSrr $xmm0, $xmm1, implicit $mxcsr1069 $xmm0 = VMINPSZ128rr $xmm0, $xmm1, implicit $mxcsr1070 ; CHECK: $xmm0 = VMULPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1071 $xmm0 = VMULPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1072 ; CHECK: $xmm0 = VMULPDrr $xmm0, $xmm1, implicit $mxcsr1073 $xmm0 = VMULPDZ128rr $xmm0, $xmm1, implicit $mxcsr1074 ; CHECK: $xmm0 = VMULPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1075 $xmm0 = VMULPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1076 ; CHECK: $xmm0 = VMULPSrr $xmm0, $xmm1, implicit $mxcsr1077 $xmm0 = VMULPSZ128rr $xmm0, $xmm1, implicit $mxcsr1078 ; CHECK: $xmm0 = VORPDrm $xmm0, $rip, 1, $noreg, 0, $noreg1079 $xmm0 = VORPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1080 ; CHECK: $xmm0 = VORPDrr $xmm0, $xmm11081 $xmm0 = VORPDZ128rr $xmm0, $xmm11082 ; CHECK: $xmm0 = VORPSrm $xmm0, $rip, 1, $noreg, 0, $noreg1083 $xmm0 = VORPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1084 ; CHECK: $xmm0 = VORPSrr $xmm0, $xmm11085 $xmm0 = VORPSZ128rr $xmm0, $xmm11086 ; CHECK: $xmm0 = VPADDBrm $xmm0, $rip, 1, $noreg, 0, $noreg1087 $xmm0 = VPADDBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1088 ; CHECK: $xmm0 = VPADDBrr $xmm0, $xmm11089 $xmm0 = VPADDBZ128rr $xmm0, $xmm11090 ; CHECK: $xmm0 = VPADDDrm $xmm0, $rip, 1, $noreg, 0, $noreg1091 $xmm0 = VPADDDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1092 ; CHECK: $xmm0 = VPADDDrr $xmm0, $xmm11093 $xmm0 = VPADDDZ128rr $xmm0, $xmm11094 ; CHECK: $xmm0 = VPADDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1095 $xmm0 = VPADDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1096 ; CHECK: $xmm0 = VPADDQrr $xmm0, $xmm11097 $xmm0 = VPADDQZ128rr $xmm0, $xmm11098 ; CHECK: $xmm0 = VPADDSBrm $xmm0, $rip, 1, $noreg, 0, $noreg1099 $xmm0 = VPADDSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1100 ; CHECK: $xmm0 = VPADDSBrr $xmm0, $xmm11101 $xmm0 = VPADDSBZ128rr $xmm0, $xmm11102 ; CHECK: $xmm0 = VPADDSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1103 $xmm0 = VPADDSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1104 ; CHECK: $xmm0 = VPADDSWrr $xmm0, $xmm11105 $xmm0 = VPADDSWZ128rr $xmm0, $xmm11106 ; CHECK: $xmm0 = VPADDUSBrm $xmm0, $rip, 1, $noreg, 0, $noreg1107 $xmm0 = VPADDUSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1108 ; CHECK: $xmm0 = VPADDUSBrr $xmm0, $xmm11109 $xmm0 = VPADDUSBZ128rr $xmm0, $xmm11110 ; CHECK: $xmm0 = VPADDUSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1111 $xmm0 = VPADDUSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1112 ; CHECK: $xmm0 = VPADDUSWrr $xmm0, $xmm11113 $xmm0 = VPADDUSWZ128rr $xmm0, $xmm11114 ; CHECK: $xmm0 = VPADDWrm $xmm0, $rip, 1, $noreg, 0, $noreg1115 $xmm0 = VPADDWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1116 ; CHECK: $xmm0 = VPADDWrr $xmm0, $xmm11117 $xmm0 = VPADDWZ128rr $xmm0, $xmm11118 ; CHECK: $xmm0 = VPANDrm $xmm0, $rip, 1, $noreg, 0, $noreg1119 $xmm0 = VPANDDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1120 ; CHECK: $xmm0 = VPANDrr $xmm0, $xmm11121 $xmm0 = VPANDDZ128rr $xmm0, $xmm11122 ; CHECK: $xmm0 = VPANDrm $xmm0, $rip, 1, $noreg, 0, $noreg1123 $xmm0 = VPANDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1124 ; CHECK: $xmm0 = VPANDrr $xmm0, $xmm11125 $xmm0 = VPANDQZ128rr $xmm0, $xmm11126 ; CHECK: $xmm0 = VPANDNrm $xmm0, $rip, 1, $noreg, 0, $noreg1127 $xmm0 = VPANDNDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1128 ; CHECK: $xmm0 = VPANDNrr $xmm0, $xmm11129 $xmm0 = VPANDNDZ128rr $xmm0, $xmm11130 ; CHECK: $xmm0 = VPANDNrm $xmm0, $rip, 1, $noreg, 0, $noreg1131 $xmm0 = VPANDNQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1132 ; CHECK: $xmm0 = VPANDNrr $xmm0, $xmm11133 $xmm0 = VPANDNQZ128rr $xmm0, $xmm11134 ; CHECK: $xmm0 = VPAVGBrm $xmm0, $rip, 1, $noreg, 0, $noreg1135 $xmm0 = VPAVGBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1136 ; CHECK: $xmm0 = VPAVGBrr $xmm0, $xmm11137 $xmm0 = VPAVGBZ128rr $xmm0, $xmm11138 ; CHECK: $xmm0 = VPAVGWrm $xmm0, $rip, 1, $noreg, 0, $noreg1139 $xmm0 = VPAVGWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1140 ; CHECK: $xmm0 = VPAVGWrr $xmm0, $xmm11141 $xmm0 = VPAVGWZ128rr $xmm0, $xmm11142 ; CHECK: $xmm0 = VPMAXSBrm $xmm0, $rip, 1, $noreg, 0, $noreg1143 $xmm0 = VPMAXSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1144 ; CHECK: $xmm0 = VPMAXSBrr $xmm0, $xmm11145 $xmm0 = VPMAXSBZ128rr $xmm0, $xmm11146 ; CHECK: $xmm0 = VPMAXSDrm $xmm0, $rip, 1, $noreg, 0, $noreg1147 $xmm0 = VPMAXSDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1148 ; CHECK: $xmm0 = VPMAXSDrr $xmm0, $xmm11149 $xmm0 = VPMAXSDZ128rr $xmm0, $xmm11150 ; CHECK: $xmm0 = VPMAXSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1151 $xmm0 = VPMAXSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1152 ; CHECK: $xmm0 = VPMAXSWrr $xmm0, $xmm11153 $xmm0 = VPMAXSWZ128rr $xmm0, $xmm11154 ; CHECK: $xmm0 = VPMAXUBrm $xmm0, $rip, 1, $noreg, 0, $noreg1155 $xmm0 = VPMAXUBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1156 ; CHECK: $xmm0 = VPMAXUBrr $xmm0, $xmm11157 $xmm0 = VPMAXUBZ128rr $xmm0, $xmm11158 ; CHECK: $xmm0 = VPMAXUDrm $xmm0, $rip, 1, $noreg, 0, $noreg1159 $xmm0 = VPMAXUDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1160 ; CHECK: $xmm0 = VPMAXUDrr $xmm0, $xmm11161 $xmm0 = VPMAXUDZ128rr $xmm0, $xmm11162 ; CHECK: $xmm0 = VPMAXUWrm $xmm0, $rip, 1, $noreg, 0, $noreg1163 $xmm0 = VPMAXUWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1164 ; CHECK: $xmm0 = VPMAXUWrr $xmm0, $xmm11165 $xmm0 = VPMAXUWZ128rr $xmm0, $xmm11166 ; CHECK: $xmm0 = VPMINSBrm $xmm0, $rip, 1, $noreg, 0, $noreg1167 $xmm0 = VPMINSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1168 ; CHECK: $xmm0 = VPMINSBrr $xmm0, $xmm11169 $xmm0 = VPMINSBZ128rr $xmm0, $xmm11170 ; CHECK: $xmm0 = VPMINSDrm $xmm0, $rip, 1, $noreg, 0, $noreg1171 $xmm0 = VPMINSDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1172 ; CHECK: $xmm0 = VPMINSDrr $xmm0, $xmm11173 $xmm0 = VPMINSDZ128rr $xmm0, $xmm11174 ; CHECK: $xmm0 = VPMINSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1175 $xmm0 = VPMINSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1176 ; CHECK: $xmm0 = VPMINSWrr $xmm0, $xmm11177 $xmm0 = VPMINSWZ128rr $xmm0, $xmm11178 ; CHECK: $xmm0 = VPMINUBrm $xmm0, $rip, 1, $noreg, 0, $noreg1179 $xmm0 = VPMINUBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1180 ; CHECK: $xmm0 = VPMINUBrr $xmm0, $xmm11181 $xmm0 = VPMINUBZ128rr $xmm0, $xmm11182 ; CHECK: $xmm0 = VPMINUDrm $xmm0, $rip, 1, $noreg, 0, $noreg1183 $xmm0 = VPMINUDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1184 ; CHECK: $xmm0 = VPMINUDrr $xmm0, $xmm11185 $xmm0 = VPMINUDZ128rr $xmm0, $xmm11186 ; CHECK: $xmm0 = VPMINUWrm $xmm0, $rip, 1, $noreg, 0, $noreg1187 $xmm0 = VPMINUWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1188 ; CHECK: $xmm0 = VPMINUWrr $xmm0, $xmm11189 $xmm0 = VPMINUWZ128rr $xmm0, $xmm11190 ; CHECK: $xmm0 = VPMULDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1191 $xmm0 = VPMULDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1192 ; CHECK: $xmm0 = VPMULDQrr $xmm0, $xmm11193 $xmm0 = VPMULDQZ128rr $xmm0, $xmm11194 ; CHECK: $xmm0 = VPMULHRSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1195 $xmm0 = VPMULHRSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1196 ; CHECK: $xmm0 = VPMULHRSWrr $xmm0, $xmm11197 $xmm0 = VPMULHRSWZ128rr $xmm0, $xmm11198 ; CHECK: $xmm0 = VPMULHUWrm $xmm0, $rip, 1, $noreg, 0, $noreg1199 $xmm0 = VPMULHUWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1200 ; CHECK: $xmm0 = VPMULHUWrr $xmm0, $xmm11201 $xmm0 = VPMULHUWZ128rr $xmm0, $xmm11202 ; CHECK: $xmm0 = VPMULHWrm $xmm0, $rip, 1, $noreg, 0, $noreg1203 $xmm0 = VPMULHWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1204 ; CHECK: $xmm0 = VPMULHWrr $xmm0, $xmm11205 $xmm0 = VPMULHWZ128rr $xmm0, $xmm11206 ; CHECK: $xmm0 = VPMULLDrm $xmm0, $rip, 1, $noreg, 0, $noreg1207 $xmm0 = VPMULLDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1208 ; CHECK: $xmm0 = VPMULLDrr $xmm0, $xmm11209 $xmm0 = VPMULLDZ128rr $xmm0, $xmm11210 ; CHECK: $xmm0 = VPMULLWrm $xmm0, $rip, 1, $noreg, 0, $noreg1211 $xmm0 = VPMULLWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1212 ; CHECK: $xmm0 = VPMULLWrr $xmm0, $xmm11213 $xmm0 = VPMULLWZ128rr $xmm0, $xmm11214 ; CHECK: $xmm0 = VPMULUDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1215 $xmm0 = VPMULUDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1216 ; CHECK: $xmm0 = VPMULUDQrr $xmm0, $xmm11217 $xmm0 = VPMULUDQZ128rr $xmm0, $xmm11218 ; CHECK: $xmm0 = VPORrm $xmm0, $rip, 1, $noreg, 0, $noreg1219 $xmm0 = VPORDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1220 ; CHECK: $xmm0 = VPORrr $xmm0, $xmm11221 $xmm0 = VPORDZ128rr $xmm0, $xmm11222 ; CHECK: $xmm0 = VPORrm $xmm0, $rip, 1, $noreg, 0, $noreg1223 $xmm0 = VPORQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1224 ; CHECK: $xmm0 = VPORrr $xmm0, $xmm11225 $xmm0 = VPORQZ128rr $xmm0, $xmm11226 ; CHECK: $xmm0 = VPSUBBrm $xmm0, $rip, 1, $noreg, 0, $noreg1227 $xmm0 = VPSUBBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1228 ; CHECK: $xmm0 = VPSUBBrr $xmm0, $xmm11229 $xmm0 = VPSUBBZ128rr $xmm0, $xmm11230 ; CHECK: $xmm0 = VPSUBDrm $xmm0, $rip, 1, $noreg, 0, $noreg1231 $xmm0 = VPSUBDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1232 ; CHECK: $xmm0 = VPSUBDrr $xmm0, $xmm11233 $xmm0 = VPSUBDZ128rr $xmm0, $xmm11234 ; CHECK: $xmm0 = VPSUBQrm $xmm0, $rip, 1, $noreg, 0, $noreg1235 $xmm0 = VPSUBQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1236 ; CHECK: $xmm0 = VPSUBQrr $xmm0, $xmm11237 $xmm0 = VPSUBQZ128rr $xmm0, $xmm11238 ; CHECK: $xmm0 = VPSUBSBrm $xmm0, $rip, 1, $noreg, 0, $noreg1239 $xmm0 = VPSUBSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1240 ; CHECK: $xmm0 = VPSUBSBrr $xmm0, $xmm11241 $xmm0 = VPSUBSBZ128rr $xmm0, $xmm11242 ; CHECK: $xmm0 = VPSUBSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1243 $xmm0 = VPSUBSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1244 ; CHECK: $xmm0 = VPSUBSWrr $xmm0, $xmm11245 $xmm0 = VPSUBSWZ128rr $xmm0, $xmm11246 ; CHECK: $xmm0 = VPSUBUSBrm $xmm0, $rip, 1, $noreg, 0, $noreg1247 $xmm0 = VPSUBUSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1248 ; CHECK: $xmm0 = VPSUBUSBrr $xmm0, $xmm11249 $xmm0 = VPSUBUSBZ128rr $xmm0, $xmm11250 ; CHECK: $xmm0 = VPSUBUSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1251 $xmm0 = VPSUBUSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1252 ; CHECK: $xmm0 = VPSUBUSWrr $xmm0, $xmm11253 $xmm0 = VPSUBUSWZ128rr $xmm0, $xmm11254 ; CHECK: $xmm0 = VPSUBWrm $xmm0, $rip, 1, $noreg, 0, $noreg1255 $xmm0 = VPSUBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1256 ; CHECK: $xmm0 = VPSUBWrr $xmm0, $xmm11257 $xmm0 = VPSUBWZ128rr $xmm0, $xmm11258 ; CHECK: $xmm0 = VADDPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1259 $xmm0 = VADDPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1260 ; CHECK: $xmm0 = VADDPDrr $xmm0, $xmm1, implicit $mxcsr1261 $xmm0 = VADDPDZ128rr $xmm0, $xmm1, implicit $mxcsr1262 ; CHECK: $xmm0 = VADDPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1263 $xmm0 = VADDPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1264 ; CHECK: $xmm0 = VADDPSrr $xmm0, $xmm1, implicit $mxcsr1265 $xmm0 = VADDPSZ128rr $xmm0, $xmm1, implicit $mxcsr1266 ; CHECK: $xmm0 = VANDNPDrm $xmm0, $rip, 1, $noreg, 0, $noreg1267 $xmm0 = VANDNPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1268 ; CHECK: $xmm0 = VANDNPDrr $xmm0, $xmm11269 $xmm0 = VANDNPDZ128rr $xmm0, $xmm11270 ; CHECK: $xmm0 = VANDNPSrm $xmm0, $rip, 1, $noreg, 0, $noreg1271 $xmm0 = VANDNPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1272 ; CHECK: $xmm0 = VANDNPSrr $xmm0, $xmm11273 $xmm0 = VANDNPSZ128rr $xmm0, $xmm11274 ; CHECK: $xmm0 = VANDPDrm $xmm0, $rip, 1, $noreg, 0, $noreg1275 $xmm0 = VANDPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1276 ; CHECK: $xmm0 = VANDPDrr $xmm0, $xmm11277 $xmm0 = VANDPDZ128rr $xmm0, $xmm11278 ; CHECK: $xmm0 = VANDPSrm $xmm0, $rip, 1, $noreg, 0, $noreg1279 $xmm0 = VANDPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1280 ; CHECK: $xmm0 = VANDPSrr $xmm0, $xmm11281 $xmm0 = VANDPSZ128rr $xmm0, $xmm11282 ; CHECK: $xmm0 = VDIVPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1283 $xmm0 = VDIVPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1284 ; CHECK: $xmm0 = VDIVPDrr $xmm0, $xmm1, implicit $mxcsr1285 $xmm0 = VDIVPDZ128rr $xmm0, $xmm1, implicit $mxcsr1286 ; CHECK: $xmm0 = VDIVPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1287 $xmm0 = VDIVPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1288 ; CHECK: $xmm0 = VDIVPSrr $xmm0, $xmm1, implicit $mxcsr1289 $xmm0 = VDIVPSZ128rr $xmm0, $xmm1, implicit $mxcsr1290 ; CHECK: $xmm0 = VPXORrm $xmm0, $rip, 1, $noreg, 0, $noreg1291 $xmm0 = VPXORDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1292 ; CHECK: $xmm0 = VPXORrr $xmm0, $xmm11293 $xmm0 = VPXORDZ128rr $xmm0, $xmm11294 ; CHECK: $xmm0 = VPXORrm $xmm0, $rip, 1, $noreg, 0, $noreg1295 $xmm0 = VPXORQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1296 ; CHECK: $xmm0 = VPXORrr $xmm0, $xmm11297 $xmm0 = VPXORQZ128rr $xmm0, $xmm11298 ; CHECK: $xmm0 = VSUBPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1299 $xmm0 = VSUBPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1300 ; CHECK: $xmm0 = VSUBPDrr $xmm0, $xmm1, implicit $mxcsr1301 $xmm0 = VSUBPDZ128rr $xmm0, $xmm1, implicit $mxcsr1302 ; CHECK: $xmm0 = VSUBPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1303 $xmm0 = VSUBPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1304 ; CHECK: $xmm0 = VSUBPSrr $xmm0, $xmm1, implicit $mxcsr1305 $xmm0 = VSUBPSZ128rr $xmm0, $xmm1, implicit $mxcsr1306 ; CHECK: $xmm0 = VXORPDrm $xmm0, $rip, 1, $noreg, 0, $noreg1307 $xmm0 = VXORPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1308 ; CHECK: $xmm0 = VXORPDrr $xmm0, $xmm11309 $xmm0 = VXORPDZ128rr $xmm0, $xmm11310 ; CHECK: $xmm0 = VXORPSrm $xmm0, $rip, 1, $noreg, 0, $noreg1311 $xmm0 = VXORPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1312 ; CHECK: $xmm0 = VXORPSrr $xmm0, $xmm11313 $xmm0 = VXORPSZ128rr $xmm0, $xmm11314 ; CHECK: $xmm0 = VPMADDUBSWrm $xmm0, $rip, 1, $noreg, 0, $noreg1315 $xmm0 = VPMADDUBSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1316 ; CHECK: $xmm0 = VPMADDUBSWrr $xmm0, $xmm11317 $xmm0 = VPMADDUBSWZ128rr $xmm0, $xmm11318 ; CHECK: $xmm0 = VPMADDWDrm $xmm0, $rip, 1, $noreg, 0, $noreg1319 $xmm0 = VPMADDWDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1320 ; CHECK: $xmm0 = VPMADDWDrr $xmm0, $xmm11321 $xmm0 = VPMADDWDZ128rr $xmm0, $xmm11322 ; CHECK: $xmm0 = VPACKSSDWrm $xmm0, $rip, 1, $noreg, 0, $noreg1323 $xmm0 = VPACKSSDWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1324 ; CHECK: $xmm0 = VPACKSSDWrr $xmm0, $xmm11325 $xmm0 = VPACKSSDWZ128rr $xmm0, $xmm11326 ; CHECK: $xmm0 = VPACKSSWBrm $xmm0, $rip, 1, $noreg, 0, $noreg1327 $xmm0 = VPACKSSWBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1328 ; CHECK: $xmm0 = VPACKSSWBrr $xmm0, $xmm11329 $xmm0 = VPACKSSWBZ128rr $xmm0, $xmm11330 ; CHECK: $xmm0 = VPACKUSDWrm $xmm0, $rip, 1, $noreg, 0, $noreg1331 $xmm0 = VPACKUSDWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1332 ; CHECK: $xmm0 = VPACKUSDWrr $xmm0, $xmm11333 $xmm0 = VPACKUSDWZ128rr $xmm0, $xmm11334 ; CHECK: $xmm0 = VPACKUSWBrm $xmm0, $rip, 1, $noreg, 0, $noreg1335 $xmm0 = VPACKUSWBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1336 ; CHECK: $xmm0 = VPACKUSWBrr $xmm0, $xmm11337 $xmm0 = VPACKUSWBZ128rr $xmm0, $xmm11338 ; CHECK: $xmm0 = VPUNPCKHBWrm $xmm0, $rip, 1, $noreg, 0, $noreg1339 $xmm0 = VPUNPCKHBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1340 ; CHECK: $xmm0 = VPUNPCKHBWrr $xmm0, $xmm11341 $xmm0 = VPUNPCKHBWZ128rr $xmm0, $xmm11342 ; CHECK: $xmm0 = VPUNPCKHDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1343 $xmm0 = VPUNPCKHDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1344 ; CHECK: $xmm0 = VPUNPCKHDQrr $xmm0, $xmm11345 $xmm0 = VPUNPCKHDQZ128rr $xmm0, $xmm11346 ; CHECK: $xmm0 = VPUNPCKHQDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1347 $xmm0 = VPUNPCKHQDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1348 ; CHECK: $xmm0 = VPUNPCKHQDQrr $xmm0, $xmm11349 $xmm0 = VPUNPCKHQDQZ128rr $xmm0, $xmm11350 ; CHECK: $xmm0 = VPUNPCKHWDrm $xmm0, $rip, 1, $noreg, 0, $noreg1351 $xmm0 = VPUNPCKHWDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1352 ; CHECK: $xmm0 = VPUNPCKHWDrr $xmm0, $xmm11353 $xmm0 = VPUNPCKHWDZ128rr $xmm0, $xmm11354 ; CHECK: $xmm0 = VPUNPCKLBWrm $xmm0, $rip, 1, $noreg, 0, $noreg1355 $xmm0 = VPUNPCKLBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1356 ; CHECK: $xmm0 = VPUNPCKLBWrr $xmm0, $xmm11357 $xmm0 = VPUNPCKLBWZ128rr $xmm0, $xmm11358 ; CHECK: $xmm0 = VPUNPCKLDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1359 $xmm0 = VPUNPCKLDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1360 ; CHECK: $xmm0 = VPUNPCKLDQrr $xmm0, $xmm11361 $xmm0 = VPUNPCKLDQZ128rr $xmm0, $xmm11362 ; CHECK: $xmm0 = VPUNPCKLQDQrm $xmm0, $rip, 1, $noreg, 0, $noreg1363 $xmm0 = VPUNPCKLQDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1364 ; CHECK: $xmm0 = VPUNPCKLQDQrr $xmm0, $xmm11365 $xmm0 = VPUNPCKLQDQZ128rr $xmm0, $xmm11366 ; CHECK: $xmm0 = VPUNPCKLWDrm $xmm0, $rip, 1, $noreg, 0, $noreg1367 $xmm0 = VPUNPCKLWDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1368 ; CHECK: $xmm0 = VPUNPCKLWDrr $xmm0, $xmm11369 $xmm0 = VPUNPCKLWDZ128rr $xmm0, $xmm11370 ; CHECK: $xmm0 = VUNPCKHPDrm $xmm0, $rip, 1, $noreg, 0, $noreg1371 $xmm0 = VUNPCKHPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1372 ; CHECK: $xmm0 = VUNPCKHPDrr $xmm0, $xmm11373 $xmm0 = VUNPCKHPDZ128rr $xmm0, $xmm11374 ; CHECK: $xmm0 = VUNPCKHPSrm $xmm0, $rip, 1, $noreg, 0, $noreg1375 $xmm0 = VUNPCKHPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1376 ; CHECK: $xmm0 = VUNPCKHPSrr $xmm0, $xmm11377 $xmm0 = VUNPCKHPSZ128rr $xmm0, $xmm11378 ; CHECK: $xmm0 = VUNPCKLPDrm $xmm0, $rip, 1, $noreg, 0, $noreg1379 $xmm0 = VUNPCKLPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1380 ; CHECK: $xmm0 = VUNPCKLPDrr $xmm0, $xmm11381 $xmm0 = VUNPCKLPDZ128rr $xmm0, $xmm11382 ; CHECK: $xmm0 = VUNPCKLPSrm $xmm0, $rip, 1, $noreg, 0, $noreg1383 $xmm0 = VUNPCKLPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1384 ; CHECK: $xmm0 = VUNPCKLPSrr $xmm0, $xmm11385 $xmm0 = VUNPCKLPSZ128rr $xmm0, $xmm11386 ; CHECK: $xmm0 = VFMADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1387 $xmm0 = VFMADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1388 ; CHECK: $xmm0 = VFMADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1389 $xmm0 = VFMADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1390 ; CHECK: $xmm0 = VFMADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1391 $xmm0 = VFMADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1392 ; CHECK: $xmm0 = VFMADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1393 $xmm0 = VFMADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1394 ; CHECK: $xmm0 = VFMADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1395 $xmm0 = VFMADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1396 ; CHECK: $xmm0 = VFMADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1397 $xmm0 = VFMADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1398 ; CHECK: $xmm0 = VFMADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1399 $xmm0 = VFMADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1400 ; CHECK: $xmm0 = VFMADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1401 $xmm0 = VFMADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1402 ; CHECK: $xmm0 = VFMADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1403 $xmm0 = VFMADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1404 ; CHECK: $xmm0 = VFMADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1405 $xmm0 = VFMADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1406 ; CHECK: $xmm0 = VFMADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1407 $xmm0 = VFMADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1408 ; CHECK: $xmm0 = VFMADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1409 $xmm0 = VFMADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1410 ; CHECK: $xmm0 = VFMADDSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1411 $xmm0 = VFMADDSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1412 ; CHECK: $xmm0 = VFMADDSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1413 $xmm0 = VFMADDSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1414 ; CHECK: $xmm0 = VFMADDSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1415 $xmm0 = VFMADDSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1416 ; CHECK: $xmm0 = VFMADDSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1417 $xmm0 = VFMADDSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1418 ; CHECK: $xmm0 = VFMADDSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1419 $xmm0 = VFMADDSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1420 ; CHECK: $xmm0 = VFMADDSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1421 $xmm0 = VFMADDSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1422 ; CHECK: $xmm0 = VFMADDSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1423 $xmm0 = VFMADDSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1424 ; CHECK: $xmm0 = VFMADDSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1425 $xmm0 = VFMADDSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1426 ; CHECK: $xmm0 = VFMADDSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1427 $xmm0 = VFMADDSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1428 ; CHECK: $xmm0 = VFMADDSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1429 $xmm0 = VFMADDSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1430 ; CHECK: $xmm0 = VFMADDSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1431 $xmm0 = VFMADDSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1432 ; CHECK: $xmm0 = VFMADDSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1433 $xmm0 = VFMADDSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1434 ; CHECK: $xmm0 = VFMSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1435 $xmm0 = VFMSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1436 ; CHECK: $xmm0 = VFMSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1437 $xmm0 = VFMSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1438 ; CHECK: $xmm0 = VFMSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1439 $xmm0 = VFMSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1440 ; CHECK: $xmm0 = VFMSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1441 $xmm0 = VFMSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1442 ; CHECK: $xmm0 = VFMSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1443 $xmm0 = VFMSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1444 ; CHECK: $xmm0 = VFMSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1445 $xmm0 = VFMSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1446 ; CHECK: $xmm0 = VFMSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1447 $xmm0 = VFMSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1448 ; CHECK: $xmm0 = VFMSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1449 $xmm0 = VFMSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1450 ; CHECK: $xmm0 = VFMSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1451 $xmm0 = VFMSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1452 ; CHECK: $xmm0 = VFMSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1453 $xmm0 = VFMSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1454 ; CHECK: $xmm0 = VFMSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1455 $xmm0 = VFMSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1456 ; CHECK: $xmm0 = VFMSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1457 $xmm0 = VFMSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1458 ; CHECK: $xmm0 = VFMSUBADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1459 $xmm0 = VFMSUBADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1460 ; CHECK: $xmm0 = VFMSUBADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1461 $xmm0 = VFMSUBADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1462 ; CHECK: $xmm0 = VFMSUBADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1463 $xmm0 = VFMSUBADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1464 ; CHECK: $xmm0 = VFMSUBADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1465 $xmm0 = VFMSUBADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1466 ; CHECK: $xmm0 = VFMSUBADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1467 $xmm0 = VFMSUBADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1468 ; CHECK: $xmm0 = VFMSUBADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1469 $xmm0 = VFMSUBADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1470 ; CHECK: $xmm0 = VFMSUBADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1471 $xmm0 = VFMSUBADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1472 ; CHECK: $xmm0 = VFMSUBADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1473 $xmm0 = VFMSUBADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1474 ; CHECK: $xmm0 = VFMSUBADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1475 $xmm0 = VFMSUBADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1476 ; CHECK: $xmm0 = VFMSUBADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1477 $xmm0 = VFMSUBADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1478 ; CHECK: $xmm0 = VFMSUBADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1479 $xmm0 = VFMSUBADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1480 ; CHECK: $xmm0 = VFMSUBADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1481 $xmm0 = VFMSUBADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1482 ; CHECK: $xmm0 = VFNMADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1483 $xmm0 = VFNMADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1484 ; CHECK: $xmm0 = VFNMADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1485 $xmm0 = VFNMADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1486 ; CHECK: $xmm0 = VFNMADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1487 $xmm0 = VFNMADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1488 ; CHECK: $xmm0 = VFNMADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1489 $xmm0 = VFNMADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1490 ; CHECK: $xmm0 = VFNMADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1491 $xmm0 = VFNMADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1492 ; CHECK: $xmm0 = VFNMADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1493 $xmm0 = VFNMADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1494 ; CHECK: $xmm0 = VFNMADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1495 $xmm0 = VFNMADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1496 ; CHECK: $xmm0 = VFNMADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1497 $xmm0 = VFNMADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1498 ; CHECK: $xmm0 = VFNMADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1499 $xmm0 = VFNMADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1500 ; CHECK: $xmm0 = VFNMADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1501 $xmm0 = VFNMADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1502 ; CHECK: $xmm0 = VFNMADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1503 $xmm0 = VFNMADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1504 ; CHECK: $xmm0 = VFNMADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1505 $xmm0 = VFNMADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1506 ; CHECK: $xmm0 = VFNMSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1507 $xmm0 = VFNMSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1508 ; CHECK: $xmm0 = VFNMSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1509 $xmm0 = VFNMSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1510 ; CHECK: $xmm0 = VFNMSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1511 $xmm0 = VFNMSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1512 ; CHECK: $xmm0 = VFNMSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1513 $xmm0 = VFNMSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1514 ; CHECK: $xmm0 = VFNMSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1515 $xmm0 = VFNMSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1516 ; CHECK: $xmm0 = VFNMSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1517 $xmm0 = VFNMSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1518 ; CHECK: $xmm0 = VFNMSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1519 $xmm0 = VFNMSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1520 ; CHECK: $xmm0 = VFNMSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1521 $xmm0 = VFNMSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1522 ; CHECK: $xmm0 = VFNMSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1523 $xmm0 = VFNMSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1524 ; CHECK: $xmm0 = VFNMSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1525 $xmm0 = VFNMSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1526 ; CHECK: $xmm0 = VFNMSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1527 $xmm0 = VFNMSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1528 ; CHECK: $xmm0 = VFNMSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1529 $xmm0 = VFNMSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr1530 ; CHECK: $xmm0 = VPSLLDri $xmm0, 71531 $xmm0 = VPSLLDZ128ri $xmm0, 71532 ; CHECK: $xmm0 = VPSLLDrm $xmm0, $rip, 1, $noreg, 0, $noreg1533 $xmm0 = VPSLLDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1534 ; CHECK: $xmm0 = VPSLLDrr $xmm0, $xmm01535 $xmm0 = VPSLLDZ128rr $xmm0, $xmm01536 ; CHECK: $xmm0 = VPSLLQri $xmm0, 71537 $xmm0 = VPSLLQZ128ri $xmm0, 71538 ; CHECK: $xmm0 = VPSLLQrm $xmm0, $rip, 1, $noreg, 0, $noreg1539 $xmm0 = VPSLLQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1540 ; CHECK: $xmm0 = VPSLLQrr $xmm0, $xmm01541 $xmm0 = VPSLLQZ128rr $xmm0, $xmm01542 ; CHECK: $xmm0 = VPSLLVDrm $xmm0, $rip, 1, $noreg, 0, $noreg1543 $xmm0 = VPSLLVDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1544 ; CHECK: $xmm0 = VPSLLVDrr $xmm0, $xmm01545 $xmm0 = VPSLLVDZ128rr $xmm0, $xmm01546 ; CHECK: $xmm0 = VPSLLVQrm $xmm0, $rip, 1, $noreg, 0, $noreg1547 $xmm0 = VPSLLVQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1548 ; CHECK: $xmm0 = VPSLLVQrr $xmm0, $xmm01549 $xmm0 = VPSLLVQZ128rr $xmm0, $xmm01550 ; CHECK: $xmm0 = VPSLLWri $xmm0, 71551 $xmm0 = VPSLLWZ128ri $xmm0, 71552 ; CHECK: $xmm0 = VPSLLWrm $xmm0, $rip, 1, $noreg, 0, $noreg1553 $xmm0 = VPSLLWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1554 ; CHECK: $xmm0 = VPSLLWrr $xmm0, $xmm01555 $xmm0 = VPSLLWZ128rr $xmm0, $xmm01556 ; CHECK: $xmm0 = VPSRADri $xmm0, 71557 $xmm0 = VPSRADZ128ri $xmm0, 71558 ; CHECK: $xmm0 = VPSRADrm $xmm0, $rip, 1, $noreg, 0, $noreg1559 $xmm0 = VPSRADZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1560 ; CHECK: $xmm0 = VPSRADrr $xmm0, $xmm01561 $xmm0 = VPSRADZ128rr $xmm0, $xmm01562 ; CHECK: $xmm0 = VPSRAVDrm $xmm0, $rip, 1, $noreg, 0, $noreg1563 $xmm0 = VPSRAVDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1564 ; CHECK: $xmm0 = VPSRAVDrr $xmm0, $xmm01565 $xmm0 = VPSRAVDZ128rr $xmm0, $xmm01566 ; CHECK: $xmm0 = VPSRAWri $xmm0, 71567 $xmm0 = VPSRAWZ128ri $xmm0, 71568 ; CHECK: $xmm0 = VPSRAWrm $xmm0, $rip, 1, $noreg, 0, $noreg1569 $xmm0 = VPSRAWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1570 ; CHECK: $xmm0 = VPSRAWrr $xmm0, $xmm01571 $xmm0 = VPSRAWZ128rr $xmm0, $xmm01572 ; CHECK: $xmm0 = VPSRLDQri $xmm0, 141573 $xmm0 = VPSRLDQZ128ri $xmm0, 141574 ; CHECK: $xmm0 = VPSRLDri $xmm0, 71575 $xmm0 = VPSRLDZ128ri $xmm0, 71576 ; CHECK: $xmm0 = VPSRLDrm $xmm0, $rip, 1, $noreg, 0, $noreg1577 $xmm0 = VPSRLDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1578 ; CHECK: $xmm0 = VPSRLDrr $xmm0, $xmm01579 $xmm0 = VPSRLDZ128rr $xmm0, $xmm01580 ; CHECK: $xmm0 = VPSRLQri $xmm0, 71581 $xmm0 = VPSRLQZ128ri $xmm0, 71582 ; CHECK: $xmm0 = VPSRLQrm $xmm0, $rip, 1, $noreg, 0, $noreg1583 $xmm0 = VPSRLQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1584 ; CHECK: $xmm0 = VPSRLQrr $xmm0, $xmm01585 $xmm0 = VPSRLQZ128rr $xmm0, $xmm01586 ; CHECK: $xmm0 = VPSRLVDrm $xmm0, $rip, 1, $noreg, 0, $noreg1587 $xmm0 = VPSRLVDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1588 ; CHECK: $xmm0 = VPSRLVDrr $xmm0, $xmm01589 $xmm0 = VPSRLVDZ128rr $xmm0, $xmm01590 ; CHECK: $xmm0 = VPSRLVQrm $xmm0, $rip, 1, $noreg, 0, $noreg1591 $xmm0 = VPSRLVQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1592 ; CHECK: $xmm0 = VPSRLVQrr $xmm0, $xmm01593 $xmm0 = VPSRLVQZ128rr $xmm0, $xmm01594 ; CHECK: $xmm0 = VPSRLWri $xmm0, 71595 $xmm0 = VPSRLWZ128ri $xmm0, 71596 ; CHECK: $xmm0 = VPSRLWrm $xmm0, $rip, 1, $noreg, 0, $noreg1597 $xmm0 = VPSRLWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1598 ; CHECK: $xmm0 = VPSRLWrr $xmm0, $xmm01599 $xmm0 = VPSRLWZ128rr $xmm0, $xmm01600 ; CHECK: $xmm0 = VPERMILPDmi $rdi, 1, $noreg, 0, $noreg, 91601 $xmm0 = VPERMILPDZ128mi $rdi, 1, $noreg, 0, $noreg, 91602 ; CHECK: $xmm0 = VPERMILPDri $xmm0, 91603 $xmm0 = VPERMILPDZ128ri $xmm0, 91604 ; CHECK: $xmm0 = VPERMILPDrm $xmm0, $rdi, 1, $noreg, 0, $noreg1605 $xmm0 = VPERMILPDZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1606 ; CHECK: $xmm0 = VPERMILPDrr $xmm0, $xmm11607 $xmm0 = VPERMILPDZ128rr $xmm0, $xmm11608 ; CHECK: $xmm0 = VPERMILPSmi $rdi, 1, $noreg, 0, $noreg, 91609 $xmm0 = VPERMILPSZ128mi $rdi, 1, $noreg, 0, $noreg, 91610 ; CHECK: $xmm0 = VPERMILPSri $xmm0, 91611 $xmm0 = VPERMILPSZ128ri $xmm0, 91612 ; CHECK: $xmm0 = VPERMILPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg1613 $xmm0 = VPERMILPSZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1614 ; CHECK: $xmm0 = VPERMILPSrr $xmm0, $xmm11615 $xmm0 = VPERMILPSZ128rr $xmm0, $xmm11616 ; CHECK: $xmm0 = VCVTPH2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1617 $xmm0 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1618 ; CHECK: $xmm0 = VCVTPH2PSrr $xmm0, implicit $mxcsr1619 $xmm0 = VCVTPH2PSZ128rr $xmm0, implicit $mxcsr1620 ; CHECK: $xmm0 = VCVTDQ2PDrm $rdi, 1, $noreg, 0, $noreg1621 $xmm0 = VCVTDQ2PDZ128rm $rdi, 1, $noreg, 0, $noreg1622 ; CHECK: $xmm0 = VCVTDQ2PDrr $xmm01623 $xmm0 = VCVTDQ2PDZ128rr $xmm01624 ; CHECK: $xmm0 = VCVTDQ2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1625 $xmm0 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1626 ; CHECK: $xmm0 = VCVTDQ2PSrr $xmm0, implicit $mxcsr1627 $xmm0 = VCVTDQ2PSZ128rr $xmm0, implicit $mxcsr1628 ; CHECK: $xmm0 = VCVTPD2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1629 $xmm0 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1630 ; CHECK: $xmm0 = VCVTPD2DQrr $xmm0, implicit $mxcsr1631 $xmm0 = VCVTPD2DQZ128rr $xmm0, implicit $mxcsr1632 ; CHECK: $xmm0 = VCVTPD2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1633 $xmm0 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1634 ; CHECK: $xmm0 = VCVTPD2PSrr $xmm0, implicit $mxcsr1635 $xmm0 = VCVTPD2PSZ128rr $xmm0, implicit $mxcsr1636 ; CHECK: $xmm0 = VCVTPS2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1637 $xmm0 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1638 ; CHECK: $xmm0 = VCVTPS2DQrr $xmm0, implicit $mxcsr1639 $xmm0 = VCVTPS2DQZ128rr $xmm0, implicit $mxcsr1640 ; CHECK: $xmm0 = VCVTPS2PDrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1641 $xmm0 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1642 ; CHECK: $xmm0 = VCVTPS2PDrr $xmm0, implicit $mxcsr1643 $xmm0 = VCVTPS2PDZ128rr $xmm0, implicit $mxcsr1644 ; CHECK: $xmm0 = VCVTTPD2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1645 $xmm0 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1646 ; CHECK: $xmm0 = VCVTTPD2DQrr $xmm0, implicit $mxcsr1647 $xmm0 = VCVTTPD2DQZ128rr $xmm0, implicit $mxcsr1648 ; CHECK: $xmm0 = VCVTTPS2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1649 $xmm0 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1650 ; CHECK: $xmm0 = VCVTTPS2DQrr $xmm0, implicit $mxcsr1651 $xmm0 = VCVTTPS2DQZ128rr $xmm0, implicit $mxcsr1652 ; CHECK: $xmm0 = VSQRTPDm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1653 $xmm0 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1654 ; CHECK: $xmm0 = VSQRTPDr $xmm0, implicit $mxcsr1655 $xmm0 = VSQRTPDZ128r $xmm0, implicit $mxcsr1656 ; CHECK: $xmm0 = VSQRTPSm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1657 $xmm0 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr1658 ; CHECK: $xmm0 = VSQRTPSr $xmm0, implicit $mxcsr1659 $xmm0 = VSQRTPSZ128r $xmm0, implicit $mxcsr1660 ; CHECK: $xmm0 = VMOVDDUPrm $rdi, 1, $noreg, 0, $noreg1661 $xmm0 = VMOVDDUPZ128rm $rdi, 1, $noreg, 0, $noreg1662 ; CHECK: $xmm0 = VMOVDDUPrr $xmm01663 $xmm0 = VMOVDDUPZ128rr $xmm01664 ; CHECK: $xmm0 = VMOVSHDUPrm $rdi, 1, $noreg, 0, $noreg1665 $xmm0 = VMOVSHDUPZ128rm $rdi, 1, $noreg, 0, $noreg1666 ; CHECK: $xmm0 = VMOVSHDUPrr $xmm01667 $xmm0 = VMOVSHDUPZ128rr $xmm01668 ; CHECK: $xmm0 = VMOVSLDUPrm $rdi, 1, $noreg, 0, $noreg1669 $xmm0 = VMOVSLDUPZ128rm $rdi, 1, $noreg, 0, $noreg1670 ; CHECK: $xmm0 = VMOVSLDUPrr $xmm01671 $xmm0 = VMOVSLDUPZ128rr $xmm01672 ; CHECK: $xmm0 = VPSHUFBrm $xmm0, $rdi, 1, $noreg, 0, $noreg1673 $xmm0 = VPSHUFBZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg1674 ; CHECK: $xmm0 = VPSHUFBrr $xmm0, $xmm11675 $xmm0 = VPSHUFBZ128rr $xmm0, $xmm11676 ; CHECK: $xmm0 = VPSHUFDmi $rdi, 1, $noreg, 0, $noreg, -241677 $xmm0 = VPSHUFDZ128mi $rdi, 1, $noreg, 0, $noreg, -241678 ; CHECK: $xmm0 = VPSHUFDri $xmm0, -241679 $xmm0 = VPSHUFDZ128ri $xmm0, -241680 ; CHECK: $xmm0 = VPSHUFHWmi $rdi, 1, $noreg, 0, $noreg, -241681 $xmm0 = VPSHUFHWZ128mi $rdi, 1, $noreg, 0, $noreg, -241682 ; CHECK: $xmm0 = VPSHUFHWri $xmm0, -241683 $xmm0 = VPSHUFHWZ128ri $xmm0, -241684 ; CHECK: $xmm0 = VPSHUFLWmi $rdi, 1, $noreg, 0, $noreg, -241685 $xmm0 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -241686 ; CHECK: $xmm0 = VPSHUFLWri $xmm0, -241687 $xmm0 = VPSHUFLWZ128ri $xmm0, -241688 ; CHECK: $xmm0 = VPSLLDQri $xmm0, 71689 $xmm0 = VPSLLDQZ128ri $xmm0, 71690 ; CHECK: $xmm0 = VSHUFPDrmi $xmm0, $rip, 1, $noreg, 0, $noreg, -241691 $xmm0 = VSHUFPDZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, -241692 ; CHECK: $xmm0 = VSHUFPDrri $xmm0, $xmm1, -241693 $xmm0 = VSHUFPDZ128rri $xmm0, $xmm1, -241694 ; CHECK: $xmm0 = VSHUFPSrmi $xmm0, $rip, 1, $noreg, 0, $noreg, -241695 $xmm0 = VSHUFPSZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, -241696 ; CHECK: $xmm0 = VSHUFPSrri $xmm0, $xmm1, -241697 $xmm0 = VSHUFPSZ128rri $xmm0, $xmm1, -241698 ; CHECK: $xmm0 = VPSADBWrm $xmm0, $rip, 1, $noreg, 0, $noreg1699 $xmm0 = VPSADBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg1700 ; CHECK: $xmm0 = VPSADBWrr $xmm0, $xmm11701 $xmm0 = VPSADBWZ128rr $xmm0, $xmm11702 ; CHECK: $xmm0 = VBROADCASTSSrm $rip, 1, $noreg, 0, $noreg1703 $xmm0 = VBROADCASTSSZ128rm $rip, 1, $noreg, 0, $noreg1704 ; CHECK: $xmm0 = VBROADCASTSSrr $xmm01705 $xmm0 = VBROADCASTSSZ128rr $xmm01706 ; CHECK: $xmm0 = VPBROADCASTBrm $rip, 1, $noreg, 0, $noreg1707 $xmm0 = VPBROADCASTBZ128rm $rip, 1, $noreg, 0, $noreg1708 ; CHECK: $xmm0 = VPBROADCASTBrr $xmm01709 $xmm0 = VPBROADCASTBZ128rr $xmm01710 ; CHECK: $xmm0 = VPBROADCASTDrm $rip, 1, $noreg, 0, $noreg1711 $xmm0 = VPBROADCASTDZ128rm $rip, 1, $noreg, 0, $noreg1712 ; CHECK: $xmm0 = VPBROADCASTDrr $xmm01713 $xmm0 = VPBROADCASTDZ128rr $xmm01714 ; CHECK: $xmm0 = VPBROADCASTQrm $rip, 1, $noreg, 0, $noreg1715 $xmm0 = VPBROADCASTQZ128rm $rip, 1, $noreg, 0, $noreg1716 ; CHECK: $xmm0 = VPBROADCASTQrr $xmm01717 $xmm0 = VPBROADCASTQZ128rr $xmm01718 ; CHECK: $xmm0 = VPBROADCASTWrm $rip, 1, $noreg, 0, $noreg1719 $xmm0 = VPBROADCASTWZ128rm $rip, 1, $noreg, 0, $noreg1720 ; CHECK: $xmm0 = VPBROADCASTWrr $xmm01721 $xmm0 = VPBROADCASTWZ128rr $xmm01722 ; CHECK: $xmm0 = VPBROADCASTQrm $rip, 1, $noreg, 0, $noreg1723 $xmm0 = VBROADCASTI32X2Z128rm $rip, 1, $noreg, 0, $noreg1724 ; CHECK: $xmm0 = VPBROADCASTQrr $xmm01725 $xmm0 = VBROADCASTI32X2Z128rr $xmm01726 ; CHECK: $xmm0 = VCVTPS2PHrr $xmm0, 2, implicit $mxcsr1727 $xmm0 = VCVTPS2PHZ128rr $xmm0, 2, implicit $mxcsr1728 ; CHECK: VCVTPS2PHmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 2, implicit $mxcsr1729 VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0, 2, implicit $mxcsr1730 ; CHECK: $xmm0 = VPABSBrm $rip, 1, $noreg, 0, $noreg1731 $xmm0 = VPABSBZ128rm $rip, 1, $noreg, 0, $noreg1732 ; CHECK: $xmm0 = VPABSBrr $xmm01733 $xmm0 = VPABSBZ128rr $xmm01734 ; CHECK: $xmm0 = VPABSDrm $rip, 1, $noreg, 0, $noreg1735 $xmm0 = VPABSDZ128rm $rip, 1, $noreg, 0, $noreg1736 ; CHECK: $xmm0 = VPABSDrr $xmm01737 $xmm0 = VPABSDZ128rr $xmm01738 ; CHECK: $xmm0 = VPABSWrm $rip, 1, $noreg, 0, $noreg1739 $xmm0 = VPABSWZ128rm $rip, 1, $noreg, 0, $noreg1740 ; CHECK: $xmm0 = VPABSWrr $xmm01741 $xmm0 = VPABSWZ128rr $xmm01742 ; CHECK: $xmm0 = VPALIGNRrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 151743 $xmm0 = VPALIGNRZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, 151744 ; CHECK: $xmm0 = VPALIGNRrri $xmm0, $xmm1, 151745 $xmm0 = VPALIGNRZ128rri $xmm0, $xmm1, 151746 ; CHECK: $xmm0 = VPALIGNRrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 41747 $xmm0 = VALIGNDZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, 11748 ; CHECK: $xmm0 = VPALIGNRrri $xmm0, $xmm1, 41749 $xmm0 = VALIGNDZ128rri $xmm0, $xmm1, 11750 ; CHECK: $xmm0 = VPALIGNRrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 81751 $xmm0 = VALIGNQZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, 11752 ; CHECK: $xmm0 = VPALIGNRrri $xmm0, $xmm1, 81753 $xmm0 = VALIGNQZ128rri $xmm0, $xmm1, 11754 ; CHECK: $xmm0 = VROUNDPDmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr1755 $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr1756 ; CHECK: $xmm0 = VROUNDPDri $xmm0, 15, implicit $mxcsr1757 $xmm0 = VRNDSCALEPDZ128rri $xmm0, 15, implicit $mxcsr1758 ; CHECK: $xmm0 = VROUNDPSmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr1759 $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr1760 ; CHECK: $xmm0 = VROUNDPSri $xmm0, 15, implicit $mxcsr1761 $xmm0 = VRNDSCALEPSZ128rri $xmm0, 15, implicit $mxcsr1762 1763 RET641764...1765---1766 # CHECK-LABEL: name: evex_scalar_to_vex_test1767 # CHECK: bb.0:1768 1769name: evex_scalar_to_vex_test1770body: |1771 bb.0:1772 1773 ; CHECK: $xmm0 = VADDSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1774 $xmm0 = VADDSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1775 ; CHECK: $xmm0 = VADDSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1776 $xmm0 = VADDSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1777 ; CHECK: $xmm0 = VADDSDrr $xmm0, $xmm1, implicit $mxcsr1778 $xmm0 = VADDSDZrr $xmm0, $xmm1, implicit $mxcsr1779 ; CHECK: $xmm0 = VADDSDrr_Int $xmm0, $xmm1, implicit $mxcsr1780 $xmm0 = VADDSDZrr_Int $xmm0, $xmm1, implicit $mxcsr1781 ; CHECK: $xmm0 = VADDSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1782 $xmm0 = VADDSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1783 ; CHECK: $xmm0 = VADDSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1784 $xmm0 = VADDSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1785 ; CHECK: $xmm0 = VADDSSrr $xmm0, $xmm1, implicit $mxcsr1786 $xmm0 = VADDSSZrr $xmm0, $xmm1, implicit $mxcsr1787 ; CHECK: $xmm0 = VADDSSrr_Int $xmm0, $xmm1, implicit $mxcsr1788 $xmm0 = VADDSSZrr_Int $xmm0, $xmm1, implicit $mxcsr1789 ; CHECK: $xmm0 = VDIVSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1790 $xmm0 = VDIVSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1791 ; CHECK: $xmm0 = VDIVSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1792 $xmm0 = VDIVSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1793 ; CHECK: $xmm0 = VDIVSDrr $xmm0, $xmm1, implicit $mxcsr1794 $xmm0 = VDIVSDZrr $xmm0, $xmm1, implicit $mxcsr1795 ; CHECK: $xmm0 = VDIVSDrr_Int $xmm0, $xmm1, implicit $mxcsr1796 $xmm0 = VDIVSDZrr_Int $xmm0, $xmm1, implicit $mxcsr1797 ; CHECK: $xmm0 = VDIVSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1798 $xmm0 = VDIVSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1799 ; CHECK: $xmm0 = VDIVSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1800 $xmm0 = VDIVSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1801 ; CHECK: $xmm0 = VDIVSSrr $xmm0, $xmm1, implicit $mxcsr1802 $xmm0 = VDIVSSZrr $xmm0, $xmm1, implicit $mxcsr1803 ; CHECK: $xmm0 = VDIVSSrr_Int $xmm0, $xmm1, implicit $mxcsr1804 $xmm0 = VDIVSSZrr_Int $xmm0, $xmm1, implicit $mxcsr1805 ; CHECK: $xmm0 = VMAXCSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1806 $xmm0 = VMAXCSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1807 ; CHECK: $xmm0 = VMAXCSDrr $xmm0, $xmm1, implicit $mxcsr1808 $xmm0 = VMAXCSDZrr $xmm0, $xmm1, implicit $mxcsr1809 ; CHECK: $xmm0 = VMAXCSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1810 $xmm0 = VMAXCSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1811 ; CHECK: $xmm0 = VMAXCSSrr $xmm0, $xmm1, implicit $mxcsr1812 $xmm0 = VMAXCSSZrr $xmm0, $xmm1, implicit $mxcsr1813 ; CHECK: $xmm0 = VMAXSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1814 $xmm0 = VMAXSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1815 ; CHECK: $xmm0 = VMAXSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1816 $xmm0 = VMAXSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1817 ; CHECK: $xmm0 = VMAXSDrr $xmm0, $xmm1, implicit $mxcsr1818 $xmm0 = VMAXSDZrr $xmm0, $xmm1, implicit $mxcsr1819 ; CHECK: $xmm0 = VMAXSDrr_Int $xmm0, $xmm1, implicit $mxcsr1820 $xmm0 = VMAXSDZrr_Int $xmm0, $xmm1, implicit $mxcsr1821 ; CHECK: $xmm0 = VMAXSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1822 $xmm0 = VMAXSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1823 ; CHECK: $xmm0 = VMAXSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1824 $xmm0 = VMAXSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1825 ; CHECK: $xmm0 = VMAXSSrr $xmm0, $xmm1, implicit $mxcsr1826 $xmm0 = VMAXSSZrr $xmm0, $xmm1, implicit $mxcsr1827 ; CHECK: $xmm0 = VMAXSSrr_Int $xmm0, $xmm1, implicit $mxcsr1828 $xmm0 = VMAXSSZrr_Int $xmm0, $xmm1, implicit $mxcsr1829 ; CHECK: $xmm0 = VMINCSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1830 $xmm0 = VMINCSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1831 ; CHECK: $xmm0 = VMINCSDrr $xmm0, $xmm1, implicit $mxcsr1832 $xmm0 = VMINCSDZrr $xmm0, $xmm1, implicit $mxcsr1833 ; CHECK: $xmm0 = VMINCSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1834 $xmm0 = VMINCSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1835 ; CHECK: $xmm0 = VMINCSSrr $xmm0, $xmm1, implicit $mxcsr1836 $xmm0 = VMINCSSZrr $xmm0, $xmm1, implicit $mxcsr1837 ; CHECK: $xmm0 = VMINSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1838 $xmm0 = VMINSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1839 ; CHECK: $xmm0 = VMINSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1840 $xmm0 = VMINSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1841 ; CHECK: $xmm0 = VMINSDrr $xmm0, $xmm1, implicit $mxcsr1842 $xmm0 = VMINSDZrr $xmm0, $xmm1, implicit $mxcsr1843 ; CHECK: $xmm0 = VMINSDrr_Int $xmm0, $xmm1, implicit $mxcsr1844 $xmm0 = VMINSDZrr_Int $xmm0, $xmm1, implicit $mxcsr1845 ; CHECK: $xmm0 = VMINSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1846 $xmm0 = VMINSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1847 ; CHECK: $xmm0 = VMINSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1848 $xmm0 = VMINSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1849 ; CHECK: $xmm0 = VMINSSrr $xmm0, $xmm1, implicit $mxcsr1850 $xmm0 = VMINSSZrr $xmm0, $xmm1, implicit $mxcsr1851 ; CHECK: $xmm0 = VMINSSrr_Int $xmm0, $xmm1, implicit $mxcsr1852 $xmm0 = VMINSSZrr_Int $xmm0, $xmm1, implicit $mxcsr1853 ; CHECK: $xmm0 = VMULSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1854 $xmm0 = VMULSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1855 ; CHECK: $xmm0 = VMULSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1856 $xmm0 = VMULSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1857 ; CHECK: $xmm0 = VMULSDrr $xmm0, $xmm1, implicit $mxcsr1858 $xmm0 = VMULSDZrr $xmm0, $xmm1, implicit $mxcsr1859 ; CHECK: $xmm0 = VMULSDrr_Int $xmm0, $xmm1, implicit $mxcsr1860 $xmm0 = VMULSDZrr_Int $xmm0, $xmm1, implicit $mxcsr1861 ; CHECK: $xmm0 = VMULSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1862 $xmm0 = VMULSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1863 ; CHECK: $xmm0 = VMULSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1864 $xmm0 = VMULSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1865 ; CHECK: $xmm0 = VMULSSrr $xmm0, $xmm1, implicit $mxcsr1866 $xmm0 = VMULSSZrr $xmm0, $xmm1, implicit $mxcsr1867 ; CHECK: $xmm0 = VMULSSrr_Int $xmm0, $xmm1, implicit $mxcsr1868 $xmm0 = VMULSSZrr_Int $xmm0, $xmm1, implicit $mxcsr1869 ; CHECK: $xmm0 = VSUBSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1870 $xmm0 = VSUBSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1871 ; CHECK: $xmm0 = VSUBSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1872 $xmm0 = VSUBSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1873 ; CHECK: $xmm0 = VSUBSDrr $xmm0, $xmm1, implicit $mxcsr1874 $xmm0 = VSUBSDZrr $xmm0, $xmm1, implicit $mxcsr1875 ; CHECK: $xmm0 = VSUBSDrr_Int $xmm0, $xmm1, implicit $mxcsr1876 $xmm0 = VSUBSDZrr_Int $xmm0, $xmm1, implicit $mxcsr1877 ; CHECK: $xmm0 = VSUBSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1878 $xmm0 = VSUBSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1879 ; CHECK: $xmm0 = VSUBSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1880 $xmm0 = VSUBSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr1881 ; CHECK: $xmm0 = VSUBSSrr $xmm0, $xmm1, implicit $mxcsr1882 $xmm0 = VSUBSSZrr $xmm0, $xmm1, implicit $mxcsr1883 ; CHECK: $xmm0 = VSUBSSrr_Int $xmm0, $xmm1, implicit $mxcsr1884 $xmm0 = VSUBSSZrr_Int $xmm0, $xmm1, implicit $mxcsr1885 ; CHECK: $xmm0 = VFMADD132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1886 $xmm0 = VFMADD132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1887 ; CHECK: $xmm0 = VFMADD132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1888 $xmm0 = VFMADD132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1889 ; CHECK: $xmm0 = VFMADD132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1890 $xmm0 = VFMADD132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1891 ; CHECK: $xmm0 = VFMADD132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1892 $xmm0 = VFMADD132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1893 ; CHECK: $xmm0 = VFMADD132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1894 $xmm0 = VFMADD132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1895 ; CHECK: $xmm0 = VFMADD132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1896 $xmm0 = VFMADD132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1897 ; CHECK: $xmm0 = VFMADD132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1898 $xmm0 = VFMADD132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1899 ; CHECK: $xmm0 = VFMADD132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1900 $xmm0 = VFMADD132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1901 ; CHECK: $xmm0 = VFMADD213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1902 $xmm0 = VFMADD213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1903 ; CHECK: $xmm0 = VFMADD213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1904 $xmm0 = VFMADD213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1905 ; CHECK: $xmm0 = VFMADD213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1906 $xmm0 = VFMADD213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1907 ; CHECK: $xmm0 = VFMADD213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1908 $xmm0 = VFMADD213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1909 ; CHECK: $xmm0 = VFMADD213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1910 $xmm0 = VFMADD213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1911 ; CHECK: $xmm0 = VFMADD213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1912 $xmm0 = VFMADD213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1913 ; CHECK: $xmm0 = VFMADD213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1914 $xmm0 = VFMADD213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1915 ; CHECK: $xmm0 = VFMADD213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1916 $xmm0 = VFMADD213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1917 ; CHECK: $xmm0 = VFMADD231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1918 $xmm0 = VFMADD231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1919 ; CHECK: $xmm0 = VFMADD231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1920 $xmm0 = VFMADD231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1921 ; CHECK: $xmm0 = VFMADD231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1922 $xmm0 = VFMADD231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1923 ; CHECK: $xmm0 = VFMADD231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1924 $xmm0 = VFMADD231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1925 ; CHECK: $xmm0 = VFMADD231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1926 $xmm0 = VFMADD231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1927 ; CHECK: $xmm0 = VFMADD231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1928 $xmm0 = VFMADD231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1929 ; CHECK: $xmm0 = VFMADD231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1930 $xmm0 = VFMADD231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1931 ; CHECK: $xmm0 = VFMADD231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1932 $xmm0 = VFMADD231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1933 ; CHECK: $xmm0 = VFMSUB132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1934 $xmm0 = VFMSUB132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1935 ; CHECK: $xmm0 = VFMSUB132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1936 $xmm0 = VFMSUB132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1937 ; CHECK: $xmm0 = VFMSUB132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1938 $xmm0 = VFMSUB132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1939 ; CHECK: $xmm0 = VFMSUB132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1940 $xmm0 = VFMSUB132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1941 ; CHECK: $xmm0 = VFMSUB132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1942 $xmm0 = VFMSUB132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1943 ; CHECK: $xmm0 = VFMSUB132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1944 $xmm0 = VFMSUB132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1945 ; CHECK: $xmm0 = VFMSUB132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1946 $xmm0 = VFMSUB132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1947 ; CHECK: $xmm0 = VFMSUB132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1948 $xmm0 = VFMSUB132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1949 ; CHECK: $xmm0 = VFMSUB213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1950 $xmm0 = VFMSUB213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1951 ; CHECK: $xmm0 = VFMSUB213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1952 $xmm0 = VFMSUB213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1953 ; CHECK: $xmm0 = VFMSUB213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1954 $xmm0 = VFMSUB213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1955 ; CHECK: $xmm0 = VFMSUB213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1956 $xmm0 = VFMSUB213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1957 ; CHECK: $xmm0 = VFMSUB213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1958 $xmm0 = VFMSUB213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1959 ; CHECK: $xmm0 = VFMSUB213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1960 $xmm0 = VFMSUB213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1961 ; CHECK: $xmm0 = VFMSUB213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1962 $xmm0 = VFMSUB213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1963 ; CHECK: $xmm0 = VFMSUB213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1964 $xmm0 = VFMSUB213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1965 ; CHECK: $xmm0 = VFMSUB231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1966 $xmm0 = VFMSUB231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1967 ; CHECK: $xmm0 = VFMSUB231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1968 $xmm0 = VFMSUB231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1969 ; CHECK: $xmm0 = VFMSUB231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1970 $xmm0 = VFMSUB231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1971 ; CHECK: $xmm0 = VFMSUB231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1972 $xmm0 = VFMSUB231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1973 ; CHECK: $xmm0 = VFMSUB231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1974 $xmm0 = VFMSUB231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1975 ; CHECK: $xmm0 = VFMSUB231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1976 $xmm0 = VFMSUB231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1977 ; CHECK: $xmm0 = VFMSUB231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1978 $xmm0 = VFMSUB231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1979 ; CHECK: $xmm0 = VFMSUB231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1980 $xmm0 = VFMSUB231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1981 ; CHECK: $xmm0 = VFNMADD132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1982 $xmm0 = VFNMADD132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1983 ; CHECK: $xmm0 = VFNMADD132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1984 $xmm0 = VFNMADD132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1985 ; CHECK: $xmm0 = VFNMADD132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr1986 $xmm0 = VFNMADD132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1987 ; CHECK: $xmm0 = VFNMADD132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1988 $xmm0 = VFNMADD132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1989 ; CHECK: $xmm0 = VFNMADD132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1990 $xmm0 = VFNMADD132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1991 ; CHECK: $xmm0 = VFNMADD132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1992 $xmm0 = VFNMADD132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1993 ; CHECK: $xmm0 = VFNMADD132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr1994 $xmm0 = VFNMADD132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr1995 ; CHECK: $xmm0 = VFNMADD132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1996 $xmm0 = VFNMADD132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr1997 ; CHECK: $xmm0 = VFNMADD213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1998 $xmm0 = VFNMADD213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr1999 ; CHECK: $xmm0 = VFNMADD213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2000 $xmm0 = VFNMADD213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2001 ; CHECK: $xmm0 = VFNMADD213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr2002 $xmm0 = VFNMADD213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2003 ; CHECK: $xmm0 = VFNMADD213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2004 $xmm0 = VFNMADD213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2005 ; CHECK: $xmm0 = VFNMADD213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2006 $xmm0 = VFNMADD213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2007 ; CHECK: $xmm0 = VFNMADD213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2008 $xmm0 = VFNMADD213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2009 ; CHECK: $xmm0 = VFNMADD213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr2010 $xmm0 = VFNMADD213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2011 ; CHECK: $xmm0 = VFNMADD213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2012 $xmm0 = VFNMADD213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2013 ; CHECK: $xmm0 = VFNMADD231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2014 $xmm0 = VFNMADD231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2015 ; CHECK: $xmm0 = VFNMADD231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2016 $xmm0 = VFNMADD231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2017 ; CHECK: $xmm0 = VFNMADD231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr2018 $xmm0 = VFNMADD231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2019 ; CHECK: $xmm0 = VFNMADD231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2020 $xmm0 = VFNMADD231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2021 ; CHECK: $xmm0 = VFNMADD231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2022 $xmm0 = VFNMADD231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2023 ; CHECK: $xmm0 = VFNMADD231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2024 $xmm0 = VFNMADD231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2025 ; CHECK: $xmm0 = VFNMADD231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr2026 $xmm0 = VFNMADD231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2027 ; CHECK: $xmm0 = VFNMADD231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2028 $xmm0 = VFNMADD231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2029 ; CHECK: $xmm0 = VFNMSUB132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2030 $xmm0 = VFNMSUB132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2031 ; CHECK: $xmm0 = VFNMSUB132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2032 $xmm0 = VFNMSUB132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2033 ; CHECK: $xmm0 = VFNMSUB132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr2034 $xmm0 = VFNMSUB132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2035 ; CHECK: $xmm0 = VFNMSUB132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2036 $xmm0 = VFNMSUB132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2037 ; CHECK: $xmm0 = VFNMSUB132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2038 $xmm0 = VFNMSUB132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2039 ; CHECK: $xmm0 = VFNMSUB132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2040 $xmm0 = VFNMSUB132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2041 ; CHECK: $xmm0 = VFNMSUB132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr2042 $xmm0 = VFNMSUB132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2043 ; CHECK: $xmm0 = VFNMSUB132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2044 $xmm0 = VFNMSUB132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2045 ; CHECK: $xmm0 = VFNMSUB213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2046 $xmm0 = VFNMSUB213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2047 ; CHECK: $xmm0 = VFNMSUB213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2048 $xmm0 = VFNMSUB213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2049 ; CHECK: $xmm0 = VFNMSUB213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr2050 $xmm0 = VFNMSUB213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2051 ; CHECK: $xmm0 = VFNMSUB213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2052 $xmm0 = VFNMSUB213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2053 ; CHECK: $xmm0 = VFNMSUB213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2054 $xmm0 = VFNMSUB213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2055 ; CHECK: $xmm0 = VFNMSUB213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2056 $xmm0 = VFNMSUB213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2057 ; CHECK: $xmm0 = VFNMSUB213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr2058 $xmm0 = VFNMSUB213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2059 ; CHECK: $xmm0 = VFNMSUB213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2060 $xmm0 = VFNMSUB213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2061 ; CHECK: $xmm0 = VFNMSUB231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2062 $xmm0 = VFNMSUB231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2063 ; CHECK: $xmm0 = VFNMSUB231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2064 $xmm0 = VFNMSUB231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2065 ; CHECK: $xmm0 = VFNMSUB231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr2066 $xmm0 = VFNMSUB231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2067 ; CHECK: $xmm0 = VFNMSUB231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2068 $xmm0 = VFNMSUB231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2069 ; CHECK: $xmm0 = VFNMSUB231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2070 $xmm0 = VFNMSUB231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2071 ; CHECK: $xmm0 = VFNMSUB231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2072 $xmm0 = VFNMSUB231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2073 ; CHECK: $xmm0 = VFNMSUB231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr2074 $xmm0 = VFNMSUB231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr2075 ; CHECK: $xmm0 = VFNMSUB231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2076 $xmm0 = VFNMSUB231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr2077 ; CHECK: VPEXTRBmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32078 VPEXTRBZmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32079 ; CHECK: $eax = VPEXTRBrri $xmm0, 12080 $eax = VPEXTRBZrri $xmm0, 12081 ; CHECK: VPEXTRDmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32082 VPEXTRDZmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32083 ; CHECK: $eax = VPEXTRDrri $xmm0, 12084 $eax = VPEXTRDZrri $xmm0, 12085 ; CHECK: VPEXTRQmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32086 VPEXTRQZmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32087 ; CHECK: $rax = VPEXTRQrri $xmm0, 12088 $rax = VPEXTRQZrri $xmm0, 12089 ; CHECK: VPEXTRWmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32090 VPEXTRWZmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 32091 ; CHECK: $eax = VPEXTRWrri $xmm0, 12092 $eax = VPEXTRWZrri $xmm0, 12093 ; CHECK: $xmm0 = VPINSRBrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32094 $xmm0 = VPINSRBZrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32095 ; CHECK: $xmm0 = VPINSRBrri $xmm0, $edi, 52096 $xmm0 = VPINSRBZrri $xmm0, $edi, 52097 ; CHECK: $xmm0 = VPINSRDrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32098 $xmm0 = VPINSRDZrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32099 ; CHECK: $xmm0 = VPINSRDrri $xmm0, $edi, 52100 $xmm0 = VPINSRDZrri $xmm0, $edi, 52101 ; CHECK: $xmm0 = VPINSRQrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32102 $xmm0 = VPINSRQZrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32103 ; CHECK: $xmm0 = VPINSRQrri $xmm0, $rdi, 52104 $xmm0 = VPINSRQZrri $xmm0, $rdi, 52105 ; CHECK: $xmm0 = VPINSRWrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32106 $xmm0 = VPINSRWZrmi $xmm0, $rsi, 1, $noreg, 0, $noreg, 32107 ; CHECK: $xmm0 = VPINSRWrri $xmm0, $edi, 52108 $xmm0 = VPINSRWZrri $xmm0, $edi, 52109 ; CHECK: $xmm0 = VSQRTSDm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2110 $xmm0 = VSQRTSDZm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2111 ; CHECK: $xmm0 = VSQRTSDm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2112 $xmm0 = VSQRTSDZm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2113 ; CHECK: $xmm0 = VSQRTSDr $xmm0, $xmm0, implicit $mxcsr2114 $xmm0 = VSQRTSDZr $xmm0, $xmm0, implicit $mxcsr2115 ; CHECK: $xmm0 = VSQRTSDr_Int $xmm0, $xmm0, implicit $mxcsr2116 $xmm0 = VSQRTSDZr_Int $xmm0, $xmm0, implicit $mxcsr2117 ; CHECK: $xmm0 = VSQRTSSm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2118 $xmm0 = VSQRTSSZm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2119 ; CHECK: $xmm0 = VSQRTSSm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2120 $xmm0 = VSQRTSSZm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2121 ; CHECK: $xmm0 = VSQRTSSr $xmm0, $xmm1, implicit $mxcsr2122 $xmm0 = VSQRTSSZr $xmm0, $xmm1, implicit $mxcsr2123 ; CHECK: $xmm0 = VSQRTSSr_Int $xmm0, $xmm1, implicit $mxcsr2124 $xmm0 = VSQRTSSZr_Int $xmm0, $xmm1, implicit $mxcsr2125 ; CHECK: $rdi = VCVTSD2SI64rr_Int $xmm0, implicit $mxcsr2126 $rdi = VCVTSD2SI64Zrr_Int $xmm0, implicit $mxcsr2127 ; CHECK: $edi = VCVTSD2SIrr_Int $xmm0, implicit $mxcsr2128 $edi = VCVTSD2SIZrr_Int $xmm0, implicit $mxcsr2129 ; CHECK: $xmm0 = VCVTSD2SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2130 $xmm0 = VCVTSD2SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2131 ; CHECK: $xmm0 = VCVTSD2SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2132 $xmm0 = VCVTSD2SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2133 ; CHECK: $xmm0 = VCVTSD2SSrr $xmm0, $xmm1, implicit $mxcsr2134 $xmm0 = VCVTSD2SSZrr $xmm0, $xmm1, implicit $mxcsr2135 ; CHECK: $xmm0 = VCVTSD2SSrr_Int $xmm0, $xmm1, implicit $mxcsr2136 $xmm0 = VCVTSD2SSZrr_Int $xmm0, $xmm1, implicit $mxcsr2137 ; CHECK: $xmm0 = VCVTSI2SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg2138 $xmm0 = VCVTSI2SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg2139 ; CHECK: $xmm0 = VCVTSI2SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg2140 $xmm0 = VCVTSI2SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg2141 ; CHECK: $xmm0 = VCVTSI2SDrr $xmm0, $edi2142 $xmm0 = VCVTSI2SDZrr $xmm0, $edi2143 ; CHECK: $xmm0 = VCVTSI2SDrr_Int $xmm0, $edi2144 $xmm0 = VCVTSI2SDZrr_Int $xmm0, $edi2145 ; CHECK: $xmm0 = VCVTSI2SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2146 $xmm0 = VCVTSI2SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2147 ; CHECK: $xmm0 = VCVTSI2SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2148 $xmm0 = VCVTSI2SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2149 ; CHECK: $xmm0 = VCVTSI2SSrr $xmm0, $edi, implicit $mxcsr2150 $xmm0 = VCVTSI2SSZrr $xmm0, $edi, implicit $mxcsr2151 ; CHECK: $xmm0 = VCVTSI2SSrr_Int $xmm0, $edi, implicit $mxcsr2152 $xmm0 = VCVTSI2SSZrr_Int $xmm0, $edi, implicit $mxcsr2153 ; CHECK: $xmm0 = VCVTSI642SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2154 $xmm0 = VCVTSI642SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2155 ; CHECK: $xmm0 = VCVTSI642SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2156 $xmm0 = VCVTSI642SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2157 ; CHECK: $xmm0 = VCVTSI642SDrr $xmm0, $rdi, implicit $mxcsr2158 $xmm0 = VCVTSI642SDZrr $xmm0, $rdi, implicit $mxcsr2159 ; CHECK: $xmm0 = VCVTSI642SDrr_Int $xmm0, $rdi, implicit $mxcsr2160 $xmm0 = VCVTSI642SDZrr_Int $xmm0, $rdi, implicit $mxcsr2161 ; CHECK: $xmm0 = VCVTSI642SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2162 $xmm0 = VCVTSI642SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2163 ; CHECK: $xmm0 = VCVTSI642SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2164 $xmm0 = VCVTSI642SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2165 ; CHECK: $xmm0 = VCVTSI642SSrr $xmm0, $rdi, implicit $mxcsr2166 $xmm0 = VCVTSI642SSZrr $xmm0, $rdi, implicit $mxcsr2167 ; CHECK: $xmm0 = VCVTSI642SSrr_Int $xmm0, $rdi, implicit $mxcsr2168 $xmm0 = VCVTSI642SSZrr_Int $xmm0, $rdi, implicit $mxcsr2169 ; CHECK: $xmm0 = VCVTSS2SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2170 $xmm0 = VCVTSS2SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2171 ; CHECK: $xmm0 = VCVTSS2SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2172 $xmm0 = VCVTSS2SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2173 ; CHECK: $xmm0 = VCVTSS2SDrr $xmm0, $xmm1, implicit $mxcsr2174 $xmm0 = VCVTSS2SDZrr $xmm0, $xmm1, implicit $mxcsr2175 ; CHECK: $xmm0 = VCVTSS2SDrr_Int $xmm0, $xmm1, implicit $mxcsr2176 $xmm0 = VCVTSS2SDZrr_Int $xmm0, $xmm1, implicit $mxcsr2177 ; CHECK: $rdi = VCVTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2178 $rdi = VCVTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2179 ; CHECK: $rdi = VCVTSS2SI64rr_Int $xmm0, implicit $mxcsr2180 $rdi = VCVTSS2SI64Zrr_Int $xmm0, implicit $mxcsr2181 ; CHECK: $edi = VCVTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2182 $edi = VCVTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2183 ; CHECK: $edi = VCVTSS2SIrr_Int $xmm0, implicit $mxcsr2184 $edi = VCVTSS2SIZrr_Int $xmm0, implicit $mxcsr2185 ; CHECK: $rdi = VCVTTSD2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2186 $rdi = VCVTTSD2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2187 ; CHECK: $rdi = VCVTTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2188 $rdi = VCVTTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2189 ; CHECK: $rdi = VCVTTSD2SI64rr $xmm0, implicit $mxcsr2190 $rdi = VCVTTSD2SI64Zrr $xmm0, implicit $mxcsr2191 ; CHECK: $rdi = VCVTTSD2SI64rr_Int $xmm0, implicit $mxcsr2192 $rdi = VCVTTSD2SI64Zrr_Int $xmm0, implicit $mxcsr2193 ; CHECK: $edi = VCVTTSD2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2194 $edi = VCVTTSD2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2195 ; CHECK: $edi = VCVTTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2196 $edi = VCVTTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2197 ; CHECK: $edi = VCVTTSD2SIrr $xmm0, implicit $mxcsr2198 $edi = VCVTTSD2SIZrr $xmm0, implicit $mxcsr2199 ; CHECK: $edi = VCVTTSD2SIrr_Int $xmm0, implicit $mxcsr2200 $edi = VCVTTSD2SIZrr_Int $xmm0, implicit $mxcsr2201 ; CHECK: $rdi = VCVTTSS2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2202 $rdi = VCVTTSS2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2203 ; CHECK: $rdi = VCVTTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2204 $rdi = VCVTTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2205 ; CHECK: $rdi = VCVTTSS2SI64rr $xmm0, implicit $mxcsr2206 $rdi = VCVTTSS2SI64Zrr $xmm0, implicit $mxcsr2207 ; CHECK: $rdi = VCVTTSS2SI64rr_Int $xmm0, implicit $mxcsr2208 $rdi = VCVTTSS2SI64Zrr_Int $xmm0, implicit $mxcsr2209 ; CHECK: $edi = VCVTTSS2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2210 $edi = VCVTTSS2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2211 ; CHECK: $edi = VCVTTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2212 $edi = VCVTTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr2213 ; CHECK: $edi = VCVTTSS2SIrr $xmm0, implicit $mxcsr2214 $edi = VCVTTSS2SIZrr $xmm0, implicit $mxcsr2215 ; CHECK: $edi = VCVTTSS2SIrr_Int $xmm0, implicit $mxcsr2216 $edi = VCVTTSS2SIZrr_Int $xmm0, implicit $mxcsr2217 ; CHECK: $xmm0 = VMOV64toSDrr $rdi2218 $xmm0 = VMOV64toSDZrr $rdi2219 ; CHECK: $xmm0 = VMOVDI2SSrr $eax2220 $xmm0 = VMOVDI2SSZrr $eax2221 ; CHECK: VMOVSDmr $rdi, 1, $noreg, 0, $noreg, $xmm02222 VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm02223 ; CHECK: $xmm0 = VMOVSDrm $rip, 1, $noreg, 0, $noreg2224 $xmm0 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg2225 ; CHECK: $xmm0 = VMOVSDrm_alt $rip, 1, $noreg, 0, $noreg2226 $xmm0 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg2227 ; CHECK: $xmm0 = VMOVSDrr $xmm0, $xmm12228 $xmm0 = VMOVSDZrr $xmm0, $xmm12229 ; CHECK: $rax = VMOVSDto64rr $xmm02230 $rax = VMOVSDto64Zrr $xmm02231 ; CHECK: VMOVSSmr $rdi, 1, $noreg, 0, $noreg, $xmm02232 VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm02233 ; CHECK: $xmm0 = VMOVSSrm $rip, 1, $noreg, 0, $noreg2234 $xmm0 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg2235 ; CHECK: $xmm0 = VMOVSSrm_alt $rip, 1, $noreg, 0, $noreg2236 $xmm0 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg2237 ; CHECK: $xmm0 = VMOVSSrr $xmm0, $xmm12238 $xmm0 = VMOVSSZrr $xmm0, $xmm12239 ; CHECK: $eax = VMOVSS2DIrr $xmm02240 $eax = VMOVSS2DIZrr $xmm02241 ; CHECK: $xmm0 = VMOV64toPQIrr $rdi2242 $xmm0 = VMOV64toPQIZrr $rdi2243 ; CHECK: $xmm0 = VMOV64toPQIrm $rdi, 1, $noreg, 0, $noreg2244 $xmm0 = VMOV64toPQIZrm $rdi, 1, $noreg, 0, $noreg2245 ; CHECK: $xmm0 = VMOV64toSDrr $rdi2246 $xmm0 = VMOV64toSDZrr $rdi2247 ; CHECK: $xmm0 = VMOVDI2PDIrm $rip, 1, $noreg, 0, $noreg2248 $xmm0 = VMOVDI2PDIZrm $rip, 1, $noreg, 0, $noreg2249 ; CHECK: $xmm0 = VMOVDI2PDIrr $edi2250 $xmm0 = VMOVDI2PDIZrr $edi2251 ; CHECK: $xmm0 = VMOVLHPSrr $xmm0, $xmm12252 $xmm0 = VMOVLHPSZrr $xmm0, $xmm12253 ; CHECK: $xmm0 = VMOVHLPSrr $xmm0, $xmm12254 $xmm0 = VMOVHLPSZrr $xmm0, $xmm12255 ; CHECK: VMOVPDI2DImr $rdi, 1, $noreg, 0, $noreg, $xmm02256 VMOVPDI2DIZmr $rdi, 1, $noreg, 0, $noreg, $xmm02257 ; CHECK: $edi = VMOVPDI2DIrr $xmm02258 $edi = VMOVPDI2DIZrr $xmm02259 ; CHECK: $xmm0 = VMOVPQI2QIrr $xmm02260 $xmm0 = VMOVPQI2QIZrr $xmm02261 ; CHECK: VMOVPQI2QImr $rdi, 1, $noreg, 0, $noreg, $xmm02262 VMOVPQI2QIZmr $rdi, 1, $noreg, 0, $noreg, $xmm02263 ; CHECK: $rdi = VMOVPQIto64rr $xmm02264 $rdi = VMOVPQIto64Zrr $xmm02265 ; CHECK: VMOVPQIto64mr $rdi, 1, $noreg, 0, $noreg, $xmm02266 VMOVPQIto64Zmr $rdi, 1, $noreg, 0, $noreg, $xmm02267 ; CHECK: $xmm0 = VMOVQI2PQIrm $rip, 1, $noreg, 0, $noreg2268 $xmm0 = VMOVQI2PQIZrm $rip, 1, $noreg, 0, $noreg2269 ; CHECK: $xmm0 = VMOVZPQILo2PQIrr $xmm02270 $xmm0 = VMOVZPQILo2PQIZrr $xmm02271 ; CHECK: VCOMISDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2272 VCOMISDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2273 ; CHECK: VCOMISDrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2274 VCOMISDZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2275 ; CHECK: VCOMISSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2276 VCOMISSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2277 ; CHECK: VCOMISSrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2278 VCOMISSZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2279 ; CHECK: VUCOMISDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2280 VUCOMISDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2281 ; CHECK: VUCOMISDrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2282 VUCOMISDZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2283 ; CHECK: VUCOMISSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2284 VUCOMISSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2285 ; CHECK: VUCOMISSrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2286 VUCOMISSZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2287 ; CHECK: VCOMISDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2288 VCOMISDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2289 ; CHECK: VCOMISDrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2290 VCOMISDZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2291 ; CHECK: VCOMISSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2292 VCOMISSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2293 ; CHECK: VCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2294 VCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2295 ; CHECK: VUCOMISDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2296 VUCOMISDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2297 ; CHECK: VUCOMISDrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2298 VUCOMISDZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2299 ; CHECK: VUCOMISSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2300 VUCOMISSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr2301 ; CHECK: VUCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2302 VUCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr2303 ; CHECK: VEXTRACTPSmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 12304 VEXTRACTPSZmri $rdi, 1, $noreg, 0, $noreg, $xmm0, 12305 ; CHECK: $eax = VEXTRACTPSrri $xmm0, 12306 $eax = VEXTRACTPSZrri $xmm0, 12307 ; CHECK: $xmm0 = VINSERTPSrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 12308 $xmm0 = VINSERTPSZrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 12309 ; CHECK: $xmm0 = VINSERTPSrri $xmm0, $xmm0, 12310 $xmm0 = VINSERTPSZrri $xmm0, $xmm0, 12311 ; CHECK: $xmm0 = VROUNDSDmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2312 $xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2313 ; CHECK: $xmm0 = VROUNDSDri $xmm0, $xmm1, 15, implicit $mxcsr2314 $xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 15, implicit $mxcsr2315 ; CHECK: $xmm0 = VROUNDSSmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2316 $xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2317 ; CHECK: $xmm0 = VROUNDSSri $xmm0, $xmm1, 15, implicit $mxcsr2318 $xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 15, implicit $mxcsr2319 ; CHECK: $xmm0 = VROUNDSDmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2320 $xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2321 ; CHECK: $xmm0 = VROUNDSDri_Int $xmm0, $xmm1, 15, implicit $mxcsr2322 $xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 15, implicit $mxcsr2323 ; CHECK: $xmm0 = VROUNDSSmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2324 $xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr2325 ; CHECK: $xmm0 = VROUNDSSri_Int $xmm0, $xmm1, 15, implicit $mxcsr2326 $xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 15, implicit $mxcsr2327 2328 RET642329...2330---2331 # CHECK-LABEL: name: evex_z256_to_evex_test2332 # CHECK: bb.0:2333 2334name: evex_z256_to_evex_test2335body: |2336 bb.0:2337 ; CHECK: VMOVAPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162338 VMOVAPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162339 ; CHECK: $ymm16 = VMOVAPDZ256rm $rip, 1, $noreg, 0, $noreg2340 $ymm16 = VMOVAPDZ256rm $rip, 1, $noreg, 0, $noreg2341 ; CHECK: $ymm16 = VMOVAPDZ256rr $ymm162342 $ymm16 = VMOVAPDZ256rr $ymm162343 ; CHECK: VMOVAPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162344 VMOVAPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162345 ; CHECK: $ymm16 = VMOVAPSZ256rm $rip, 1, $noreg, 0, $noreg2346 $ymm16 = VMOVAPSZ256rm $rip, 1, $noreg, 0, $noreg2347 ; CHECK: $ymm16 = VMOVAPSZ256rr $ymm162348 $ymm16 = VMOVAPSZ256rr $ymm162349 ; CHECK: $ymm16 = VMOVDDUPZ256rm $rip, 1, $noreg, 0, $noreg2350 $ymm16 = VMOVDDUPZ256rm $rip, 1, $noreg, 0, $noreg2351 ; CHECK: $ymm16 = VMOVDDUPZ256rr $ymm162352 $ymm16 = VMOVDDUPZ256rr $ymm162353 ; CHECK: VMOVDQA32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162354 VMOVDQA32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162355 ; CHECK: $ymm16 = VMOVDQA32Z256rm $rip, 1, $noreg, 0, $noreg2356 $ymm16 = VMOVDQA32Z256rm $rip, 1, $noreg, 0, $noreg2357 ; CHECK: $ymm16 = VMOVDQA32Z256rr $ymm162358 $ymm16 = VMOVDQA32Z256rr $ymm162359 ; CHECK: VMOVDQA64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162360 VMOVDQA64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162361 ; CHECK: $ymm16 = VMOVDQA64Z256rm $rip, 1, $noreg, 0, $noreg2362 $ymm16 = VMOVDQA64Z256rm $rip, 1, $noreg, 0, $noreg2363 ; CHECK: $ymm16 = VMOVDQA64Z256rr $ymm162364 $ymm16 = VMOVDQA64Z256rr $ymm162365 ; CHECK: VMOVDQU16Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162366 VMOVDQU16Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162367 ; CHECK: $ymm16 = VMOVDQU16Z256rm $rip, 1, $noreg, 0, $noreg2368 $ymm16 = VMOVDQU16Z256rm $rip, 1, $noreg, 0, $noreg2369 ; CHECK: $ymm16 = VMOVDQU16Z256rr $ymm162370 $ymm16 = VMOVDQU16Z256rr $ymm162371 ; CHECK: VMOVDQU32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162372 VMOVDQU32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162373 ; CHECK: $ymm16 = VMOVDQU32Z256rm $rip, 1, $noreg, 0, $noreg2374 $ymm16 = VMOVDQU32Z256rm $rip, 1, $noreg, 0, $noreg2375 ; CHECK: $ymm16 = VMOVDQU32Z256rr $ymm162376 $ymm16 = VMOVDQU32Z256rr $ymm162377 ; CHECK: VMOVDQU64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162378 VMOVDQU64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162379 ; CHECK: $ymm16 = VMOVDQU64Z256rm $rip, 1, $noreg, 0, $noreg2380 $ymm16 = VMOVDQU64Z256rm $rip, 1, $noreg, 0, $noreg2381 ; CHECK: $ymm16 = VMOVDQU64Z256rr $ymm162382 $ymm16 = VMOVDQU64Z256rr $ymm162383 ; CHECK: VMOVDQU8Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162384 VMOVDQU8Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm162385 ; CHECK: $ymm16 = VMOVDQU8Z256rm $rip, 1, $noreg, 0, $noreg2386 $ymm16 = VMOVDQU8Z256rm $rip, 1, $noreg, 0, $noreg2387 ; CHECK: $ymm16 = VMOVDQU8Z256rr $ymm162388 $ymm16 = VMOVDQU8Z256rr $ymm162389 ; CHECK: $ymm16 = VMOVNTDQAZ256rm $rip, 1, $noreg, 0, $noreg2390 $ymm16 = VMOVNTDQAZ256rm $rip, 1, $noreg, 0, $noreg2391 ; CHECK: VMOVNTDQZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162392 VMOVNTDQZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162393 ; CHECK: VMOVNTPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162394 VMOVNTPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162395 ; CHECK: VMOVNTPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162396 VMOVNTPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162397 ; CHECK: $ymm16 = VMOVSHDUPZ256rm $rip, 1, $noreg, 0, $noreg2398 $ymm16 = VMOVSHDUPZ256rm $rip, 1, $noreg, 0, $noreg2399 ; CHECK: $ymm16 = VMOVSHDUPZ256rr $ymm162400 $ymm16 = VMOVSHDUPZ256rr $ymm162401 ; CHECK: $ymm16 = VMOVSLDUPZ256rm $rip, 1, $noreg, 0, $noreg2402 $ymm16 = VMOVSLDUPZ256rm $rip, 1, $noreg, 0, $noreg2403 ; CHECK: $ymm16 = VMOVSLDUPZ256rr $ymm162404 $ymm16 = VMOVSLDUPZ256rr $ymm162405 ; CHECK: VMOVUPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162406 VMOVUPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162407 ; CHECK: $ymm16 = VMOVUPDZ256rm $rip, 1, $noreg, 0, $noreg2408 $ymm16 = VMOVUPDZ256rm $rip, 1, $noreg, 0, $noreg2409 ; CHECK: $ymm16 = VMOVUPDZ256rr $ymm162410 $ymm16 = VMOVUPDZ256rr $ymm162411 ; CHECK: VMOVUPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162412 VMOVUPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm162413 ; CHECK: $ymm16 = VPANDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2414 $ymm16 = VPANDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2415 ; CHECK: $ymm16 = VPANDDZ256rr $ymm16, $ymm12416 $ymm16 = VPANDDZ256rr $ymm16, $ymm12417 ; CHECK: $ymm16 = VPANDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2418 $ymm16 = VPANDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2419 ; CHECK: $ymm16 = VPANDQZ256rr $ymm16, $ymm12420 $ymm16 = VPANDQZ256rr $ymm16, $ymm12421 ; CHECK: $ymm16 = VPANDNDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2422 $ymm16 = VPANDNDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2423 ; CHECK: $ymm16 = VPANDNDZ256rr $ymm16, $ymm12424 $ymm16 = VPANDNDZ256rr $ymm16, $ymm12425 ; CHECK: $ymm16 = VPANDNQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2426 $ymm16 = VPANDNQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2427 ; CHECK: $ymm16 = VPANDNQZ256rr $ymm16, $ymm12428 $ymm16 = VPANDNQZ256rr $ymm16, $ymm12429 ; CHECK: $ymm16 = VPAVGBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2430 $ymm16 = VPAVGBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2431 ; CHECK: $ymm16 = VPAVGBZ256rr $ymm16, $ymm12432 $ymm16 = VPAVGBZ256rr $ymm16, $ymm12433 ; CHECK: $ymm16 = VPAVGWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2434 $ymm16 = VPAVGWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2435 ; CHECK: $ymm16 = VPAVGWZ256rr $ymm16, $ymm12436 $ymm16 = VPAVGWZ256rr $ymm16, $ymm12437 ; CHECK: $ymm16 = VPADDBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2438 $ymm16 = VPADDBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2439 ; CHECK: $ymm16 = VPADDBZ256rr $ymm16, $ymm12440 $ymm16 = VPADDBZ256rr $ymm16, $ymm12441 ; CHECK: $ymm16 = VPADDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2442 $ymm16 = VPADDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2443 ; CHECK: $ymm16 = VPADDDZ256rr $ymm16, $ymm12444 $ymm16 = VPADDDZ256rr $ymm16, $ymm12445 ; CHECK: $ymm16 = VPADDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2446 $ymm16 = VPADDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2447 ; CHECK: $ymm16 = VPADDQZ256rr $ymm16, $ymm12448 $ymm16 = VPADDQZ256rr $ymm16, $ymm12449 ; CHECK: $ymm16 = VPADDSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2450 $ymm16 = VPADDSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2451 ; CHECK: $ymm16 = VPADDSBZ256rr $ymm16, $ymm12452 $ymm16 = VPADDSBZ256rr $ymm16, $ymm12453 ; CHECK: $ymm16 = VPADDSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2454 $ymm16 = VPADDSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2455 ; CHECK: $ymm16 = VPADDSWZ256rr $ymm16, $ymm12456 $ymm16 = VPADDSWZ256rr $ymm16, $ymm12457 ; CHECK: $ymm16 = VPADDUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2458 $ymm16 = VPADDUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2459 ; CHECK: $ymm16 = VPADDUSBZ256rr $ymm16, $ymm12460 $ymm16 = VPADDUSBZ256rr $ymm16, $ymm12461 ; CHECK: $ymm16 = VPADDUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2462 $ymm16 = VPADDUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2463 ; CHECK: $ymm16 = VPADDUSWZ256rr $ymm16, $ymm12464 $ymm16 = VPADDUSWZ256rr $ymm16, $ymm12465 ; CHECK: $ymm16 = VPADDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2466 $ymm16 = VPADDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2467 ; CHECK: $ymm16 = VPADDWZ256rr $ymm16, $ymm12468 $ymm16 = VPADDWZ256rr $ymm16, $ymm12469 ; CHECK: $ymm16 = VMULPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2470 $ymm16 = VMULPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2471 ; CHECK: $ymm16 = VMULPDZ256rr $ymm16, $ymm1, implicit $mxcsr2472 $ymm16 = VMULPDZ256rr $ymm16, $ymm1, implicit $mxcsr2473 ; CHECK: $ymm16 = VMULPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2474 $ymm16 = VMULPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2475 ; CHECK: $ymm16 = VMULPSZ256rr $ymm16, $ymm1, implicit $mxcsr2476 $ymm16 = VMULPSZ256rr $ymm16, $ymm1, implicit $mxcsr2477 ; CHECK: $ymm16 = VORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2478 $ymm16 = VORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2479 ; CHECK: $ymm16 = VORPDZ256rr $ymm16, $ymm12480 $ymm16 = VORPDZ256rr $ymm16, $ymm12481 ; CHECK: $ymm16 = VORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2482 $ymm16 = VORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2483 ; CHECK: $ymm16 = VORPSZ256rr $ymm16, $ymm12484 $ymm16 = VORPSZ256rr $ymm16, $ymm12485 ; CHECK: $ymm16 = VPMADDUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2486 $ymm16 = VPMADDUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2487 ; CHECK: $ymm16 = VPMADDUBSWZ256rr $ymm16, $ymm12488 $ymm16 = VPMADDUBSWZ256rr $ymm16, $ymm12489 ; CHECK: $ymm16 = VPMADDWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2490 $ymm16 = VPMADDWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2491 ; CHECK: $ymm16 = VPMADDWDZ256rr $ymm16, $ymm12492 $ymm16 = VPMADDWDZ256rr $ymm16, $ymm12493 ; CHECK: $ymm16 = VPMAXSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2494 $ymm16 = VPMAXSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2495 ; CHECK: $ymm16 = VPMAXSBZ256rr $ymm16, $ymm12496 $ymm16 = VPMAXSBZ256rr $ymm16, $ymm12497 ; CHECK: $ymm16 = VPMAXSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2498 $ymm16 = VPMAXSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2499 ; CHECK: $ymm16 = VPMAXSDZ256rr $ymm16, $ymm12500 $ymm16 = VPMAXSDZ256rr $ymm16, $ymm12501 ; CHECK: $ymm16 = VPMAXSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2502 $ymm16 = VPMAXSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2503 ; CHECK: $ymm16 = VPMAXSWZ256rr $ymm16, $ymm12504 $ymm16 = VPMAXSWZ256rr $ymm16, $ymm12505 ; CHECK: $ymm16 = VPMAXUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2506 $ymm16 = VPMAXUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2507 ; CHECK: $ymm16 = VPMAXUBZ256rr $ymm16, $ymm12508 $ymm16 = VPMAXUBZ256rr $ymm16, $ymm12509 ; CHECK: $ymm16 = VPMAXUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2510 $ymm16 = VPMAXUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2511 ; CHECK: $ymm16 = VPMAXUDZ256rr $ymm16, $ymm12512 $ymm16 = VPMAXUDZ256rr $ymm16, $ymm12513 ; CHECK: $ymm16 = VPMAXUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2514 $ymm16 = VPMAXUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2515 ; CHECK: $ymm16 = VPMAXUWZ256rr $ymm16, $ymm12516 $ymm16 = VPMAXUWZ256rr $ymm16, $ymm12517 ; CHECK: $ymm16 = VPMINSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2518 $ymm16 = VPMINSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2519 ; CHECK: $ymm16 = VPMINSBZ256rr $ymm16, $ymm12520 $ymm16 = VPMINSBZ256rr $ymm16, $ymm12521 ; CHECK: $ymm16 = VPMINSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2522 $ymm16 = VPMINSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2523 ; CHECK: $ymm16 = VPMINSDZ256rr $ymm16, $ymm12524 $ymm16 = VPMINSDZ256rr $ymm16, $ymm12525 ; CHECK: $ymm16 = VPMINSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2526 $ymm16 = VPMINSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2527 ; CHECK: $ymm16 = VPMINSWZ256rr $ymm16, $ymm12528 $ymm16 = VPMINSWZ256rr $ymm16, $ymm12529 ; CHECK: $ymm16 = VPMINUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2530 $ymm16 = VPMINUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2531 ; CHECK: $ymm16 = VPMINUBZ256rr $ymm16, $ymm12532 $ymm16 = VPMINUBZ256rr $ymm16, $ymm12533 ; CHECK: $ymm16 = VPMINUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2534 $ymm16 = VPMINUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2535 ; CHECK: $ymm16 = VPMINUDZ256rr $ymm16, $ymm12536 $ymm16 = VPMINUDZ256rr $ymm16, $ymm12537 ; CHECK: $ymm16 = VPMINUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2538 $ymm16 = VPMINUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2539 ; CHECK: $ymm16 = VPMINUWZ256rr $ymm16, $ymm12540 $ymm16 = VPMINUWZ256rr $ymm16, $ymm12541 ; CHECK: $ymm16 = VPMULDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2542 $ymm16 = VPMULDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2543 ; CHECK: $ymm16 = VPMULDQZ256rr $ymm16, $ymm12544 $ymm16 = VPMULDQZ256rr $ymm16, $ymm12545 ; CHECK: $ymm16 = VPMULHRSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2546 $ymm16 = VPMULHRSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2547 ; CHECK: $ymm16 = VPMULHRSWZ256rr $ymm16, $ymm12548 $ymm16 = VPMULHRSWZ256rr $ymm16, $ymm12549 ; CHECK: $ymm16 = VPMULHUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2550 $ymm16 = VPMULHUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2551 ; CHECK: $ymm16 = VPMULHUWZ256rr $ymm16, $ymm12552 $ymm16 = VPMULHUWZ256rr $ymm16, $ymm12553 ; CHECK: $ymm16 = VPMULHWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2554 $ymm16 = VPMULHWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2555 ; CHECK: $ymm16 = VPMULHWZ256rr $ymm16, $ymm12556 $ymm16 = VPMULHWZ256rr $ymm16, $ymm12557 ; CHECK: $ymm16 = VPMULLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2558 $ymm16 = VPMULLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2559 ; CHECK: $ymm16 = VPMULLDZ256rr $ymm16, $ymm12560 $ymm16 = VPMULLDZ256rr $ymm16, $ymm12561 ; CHECK: $ymm16 = VPMULLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2562 $ymm16 = VPMULLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2563 ; CHECK: $ymm16 = VPMULLWZ256rr $ymm16, $ymm12564 $ymm16 = VPMULLWZ256rr $ymm16, $ymm12565 ; CHECK: $ymm16 = VPMULUDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2566 $ymm16 = VPMULUDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2567 ; CHECK: $ymm16 = VPMULUDQZ256rr $ymm16, $ymm12568 $ymm16 = VPMULUDQZ256rr $ymm16, $ymm12569 ; CHECK: $ymm16 = VPORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2570 $ymm16 = VPORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2571 ; CHECK: $ymm16 = VPORDZ256rr $ymm16, $ymm12572 $ymm16 = VPORDZ256rr $ymm16, $ymm12573 ; CHECK: $ymm16 = VPORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2574 $ymm16 = VPORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2575 ; CHECK: $ymm16 = VPORQZ256rr $ymm16, $ymm12576 $ymm16 = VPORQZ256rr $ymm16, $ymm12577 ; CHECK: $ymm16 = VPSUBBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2578 $ymm16 = VPSUBBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2579 ; CHECK: $ymm16 = VPSUBBZ256rr $ymm16, $ymm12580 $ymm16 = VPSUBBZ256rr $ymm16, $ymm12581 ; CHECK: $ymm16 = VPSUBDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2582 $ymm16 = VPSUBDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2583 ; CHECK: $ymm16 = VPSUBDZ256rr $ymm16, $ymm12584 $ymm16 = VPSUBDZ256rr $ymm16, $ymm12585 ; CHECK: $ymm16 = VPSUBQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2586 $ymm16 = VPSUBQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2587 ; CHECK: $ymm16 = VPSUBQZ256rr $ymm16, $ymm12588 $ymm16 = VPSUBQZ256rr $ymm16, $ymm12589 ; CHECK: $ymm16 = VPSUBSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2590 $ymm16 = VPSUBSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2591 ; CHECK: $ymm16 = VPSUBSBZ256rr $ymm16, $ymm12592 $ymm16 = VPSUBSBZ256rr $ymm16, $ymm12593 ; CHECK: $ymm16 = VPSUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2594 $ymm16 = VPSUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2595 ; CHECK: $ymm16 = VPSUBSWZ256rr $ymm16, $ymm12596 $ymm16 = VPSUBSWZ256rr $ymm16, $ymm12597 ; CHECK: $ymm16 = VPSUBUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2598 $ymm16 = VPSUBUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2599 ; CHECK: $ymm16 = VPSUBUSBZ256rr $ymm16, $ymm12600 $ymm16 = VPSUBUSBZ256rr $ymm16, $ymm12601 ; CHECK: $ymm16 = VPSUBUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2602 $ymm16 = VPSUBUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2603 ; CHECK: $ymm16 = VPSUBUSWZ256rr $ymm16, $ymm12604 $ymm16 = VPSUBUSWZ256rr $ymm16, $ymm12605 ; CHECK: $ymm16 = VPSUBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2606 $ymm16 = VPSUBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2607 ; CHECK: $ymm16 = VPSUBWZ256rr $ymm16, $ymm12608 $ymm16 = VPSUBWZ256rr $ymm16, $ymm12609 ; CHECK: $ymm16 = VPXORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2610 $ymm16 = VPXORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2611 ; CHECK: $ymm16 = VPXORDZ256rr $ymm16, $ymm12612 $ymm16 = VPXORDZ256rr $ymm16, $ymm12613 ; CHECK: $ymm16 = VPXORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2614 $ymm16 = VPXORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2615 ; CHECK: $ymm16 = VPXORQZ256rr $ymm16, $ymm12616 $ymm16 = VPXORQZ256rr $ymm16, $ymm12617 ; CHECK: $ymm16 = VADDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2618 $ymm16 = VADDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2619 ; CHECK: $ymm16 = VADDPDZ256rr $ymm16, $ymm1, implicit $mxcsr2620 $ymm16 = VADDPDZ256rr $ymm16, $ymm1, implicit $mxcsr2621 ; CHECK: $ymm16 = VADDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2622 $ymm16 = VADDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2623 ; CHECK: $ymm16 = VADDPSZ256rr $ymm16, $ymm1, implicit $mxcsr2624 $ymm16 = VADDPSZ256rr $ymm16, $ymm1, implicit $mxcsr2625 ; CHECK: $ymm16 = VANDNPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2626 $ymm16 = VANDNPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2627 ; CHECK: $ymm16 = VANDNPDZ256rr $ymm16, $ymm12628 $ymm16 = VANDNPDZ256rr $ymm16, $ymm12629 ; CHECK: $ymm16 = VANDNPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2630 $ymm16 = VANDNPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2631 ; CHECK: $ymm16 = VANDNPSZ256rr $ymm16, $ymm12632 $ymm16 = VANDNPSZ256rr $ymm16, $ymm12633 ; CHECK: $ymm16 = VANDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2634 $ymm16 = VANDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2635 ; CHECK: $ymm16 = VANDPDZ256rr $ymm16, $ymm12636 $ymm16 = VANDPDZ256rr $ymm16, $ymm12637 ; CHECK: $ymm16 = VANDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2638 $ymm16 = VANDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2639 ; CHECK: $ymm16 = VANDPSZ256rr $ymm16, $ymm12640 $ymm16 = VANDPSZ256rr $ymm16, $ymm12641 ; CHECK: $ymm16 = VDIVPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2642 $ymm16 = VDIVPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2643 ; CHECK: $ymm16 = VDIVPDZ256rr $ymm16, $ymm1, implicit $mxcsr2644 $ymm16 = VDIVPDZ256rr $ymm16, $ymm1, implicit $mxcsr2645 ; CHECK: $ymm16 = VDIVPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2646 $ymm16 = VDIVPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2647 ; CHECK: $ymm16 = VDIVPSZ256rr $ymm16, $ymm1, implicit $mxcsr2648 $ymm16 = VDIVPSZ256rr $ymm16, $ymm1, implicit $mxcsr2649 ; CHECK: $ymm16 = VMAXCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2650 $ymm16 = VMAXCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2651 ; CHECK: $ymm16 = VMAXCPDZ256rr $ymm16, $ymm1, implicit $mxcsr2652 $ymm16 = VMAXCPDZ256rr $ymm16, $ymm1, implicit $mxcsr2653 ; CHECK: $ymm16 = VMAXCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2654 $ymm16 = VMAXCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2655 ; CHECK: $ymm16 = VMAXCPSZ256rr $ymm16, $ymm1, implicit $mxcsr2656 $ymm16 = VMAXCPSZ256rr $ymm16, $ymm1, implicit $mxcsr2657 ; CHECK: $ymm16 = VMAXPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2658 $ymm16 = VMAXPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2659 ; CHECK: $ymm16 = VMAXPDZ256rr $ymm16, $ymm1, implicit $mxcsr2660 $ymm16 = VMAXPDZ256rr $ymm16, $ymm1, implicit $mxcsr2661 ; CHECK: $ymm16 = VMAXPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2662 $ymm16 = VMAXPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2663 ; CHECK: $ymm16 = VMAXPSZ256rr $ymm16, $ymm1, implicit $mxcsr2664 $ymm16 = VMAXPSZ256rr $ymm16, $ymm1, implicit $mxcsr2665 ; CHECK: $ymm16 = VMINCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2666 $ymm16 = VMINCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2667 ; CHECK: $ymm16 = VMINCPDZ256rr $ymm16, $ymm1, implicit $mxcsr2668 $ymm16 = VMINCPDZ256rr $ymm16, $ymm1, implicit $mxcsr2669 ; CHECK: $ymm16 = VMINCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2670 $ymm16 = VMINCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2671 ; CHECK: $ymm16 = VMINCPSZ256rr $ymm16, $ymm1, implicit $mxcsr2672 $ymm16 = VMINCPSZ256rr $ymm16, $ymm1, implicit $mxcsr2673 ; CHECK: $ymm16 = VMINPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2674 $ymm16 = VMINPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2675 ; CHECK: $ymm16 = VMINPDZ256rr $ymm16, $ymm1, implicit $mxcsr2676 $ymm16 = VMINPDZ256rr $ymm16, $ymm1, implicit $mxcsr2677 ; CHECK: $ymm16 = VMINPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2678 $ymm16 = VMINPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2679 ; CHECK: $ymm16 = VMINPSZ256rr $ymm16, $ymm1, implicit $mxcsr2680 $ymm16 = VMINPSZ256rr $ymm16, $ymm1, implicit $mxcsr2681 ; CHECK: $ymm16 = VXORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2682 $ymm16 = VXORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2683 ; CHECK: $ymm16 = VXORPDZ256rr $ymm16, $ymm12684 $ymm16 = VXORPDZ256rr $ymm16, $ymm12685 ; CHECK: $ymm16 = VXORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2686 $ymm16 = VXORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2687 ; CHECK: $ymm16 = VXORPSZ256rr $ymm16, $ymm12688 $ymm16 = VXORPSZ256rr $ymm16, $ymm12689 ; CHECK: $ymm16 = VPACKSSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2690 $ymm16 = VPACKSSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2691 ; CHECK: $ymm16 = VPACKSSDWZ256rr $ymm16, $ymm12692 $ymm16 = VPACKSSDWZ256rr $ymm16, $ymm12693 ; CHECK: $ymm16 = VPACKSSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2694 $ymm16 = VPACKSSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2695 ; CHECK: $ymm16 = VPACKSSWBZ256rr $ymm16, $ymm12696 $ymm16 = VPACKSSWBZ256rr $ymm16, $ymm12697 ; CHECK: $ymm16 = VPACKUSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2698 $ymm16 = VPACKUSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2699 ; CHECK: $ymm16 = VPACKUSDWZ256rr $ymm16, $ymm12700 $ymm16 = VPACKUSDWZ256rr $ymm16, $ymm12701 ; CHECK: $ymm16 = VPACKUSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2702 $ymm16 = VPACKUSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2703 ; CHECK: $ymm16 = VPACKUSWBZ256rr $ymm16, $ymm12704 $ymm16 = VPACKUSWBZ256rr $ymm16, $ymm12705 ; CHECK: $ymm16 = VUNPCKHPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2706 $ymm16 = VUNPCKHPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2707 ; CHECK: $ymm16 = VUNPCKHPDZ256rr $ymm16, $ymm12708 $ymm16 = VUNPCKHPDZ256rr $ymm16, $ymm12709 ; CHECK: $ymm16 = VUNPCKHPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2710 $ymm16 = VUNPCKHPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2711 ; CHECK: $ymm16 = VUNPCKHPSZ256rr $ymm16, $ymm12712 $ymm16 = VUNPCKHPSZ256rr $ymm16, $ymm12713 ; CHECK: $ymm16 = VUNPCKLPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2714 $ymm16 = VUNPCKLPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2715 ; CHECK: $ymm16 = VUNPCKLPDZ256rr $ymm16, $ymm12716 $ymm16 = VUNPCKLPDZ256rr $ymm16, $ymm12717 ; CHECK: $ymm16 = VUNPCKLPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2718 $ymm16 = VUNPCKLPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2719 ; CHECK: $ymm16 = VUNPCKLPSZ256rr $ymm16, $ymm12720 $ymm16 = VUNPCKLPSZ256rr $ymm16, $ymm12721 ; CHECK: $ymm16 = VSUBPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2722 $ymm16 = VSUBPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2723 ; CHECK: $ymm16 = VSUBPDZ256rr $ymm16, $ymm1, implicit $mxcsr2724 $ymm16 = VSUBPDZ256rr $ymm16, $ymm1, implicit $mxcsr2725 ; CHECK: $ymm16 = VSUBPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2726 $ymm16 = VSUBPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr2727 ; CHECK: $ymm16 = VSUBPSZ256rr $ymm16, $ymm1, implicit $mxcsr2728 $ymm16 = VSUBPSZ256rr $ymm16, $ymm1, implicit $mxcsr2729 ; CHECK: $ymm16 = VPUNPCKHBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2730 $ymm16 = VPUNPCKHBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2731 ; CHECK: $ymm16 = VPUNPCKHBWZ256rr $ymm16, $ymm12732 $ymm16 = VPUNPCKHBWZ256rr $ymm16, $ymm12733 ; CHECK: $ymm16 = VPUNPCKHDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2734 $ymm16 = VPUNPCKHDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2735 ; CHECK: $ymm16 = VPUNPCKHDQZ256rr $ymm16, $ymm12736 $ymm16 = VPUNPCKHDQZ256rr $ymm16, $ymm12737 ; CHECK: $ymm16 = VPUNPCKHQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2738 $ymm16 = VPUNPCKHQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2739 ; CHECK: $ymm16 = VPUNPCKHQDQZ256rr $ymm16, $ymm12740 $ymm16 = VPUNPCKHQDQZ256rr $ymm16, $ymm12741 ; CHECK: $ymm16 = VPUNPCKHWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2742 $ymm16 = VPUNPCKHWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2743 ; CHECK: $ymm16 = VPUNPCKHWDZ256rr $ymm16, $ymm12744 $ymm16 = VPUNPCKHWDZ256rr $ymm16, $ymm12745 ; CHECK: $ymm16 = VPUNPCKLBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2746 $ymm16 = VPUNPCKLBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2747 ; CHECK: $ymm16 = VPUNPCKLBWZ256rr $ymm16, $ymm12748 $ymm16 = VPUNPCKLBWZ256rr $ymm16, $ymm12749 ; CHECK: $ymm16 = VPUNPCKLDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2750 $ymm16 = VPUNPCKLDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2751 ; CHECK: $ymm16 = VPUNPCKLDQZ256rr $ymm16, $ymm12752 $ymm16 = VPUNPCKLDQZ256rr $ymm16, $ymm12753 ; CHECK: $ymm16 = VPUNPCKLQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2754 $ymm16 = VPUNPCKLQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2755 ; CHECK: $ymm16 = VPUNPCKLQDQZ256rr $ymm16, $ymm12756 $ymm16 = VPUNPCKLQDQZ256rr $ymm16, $ymm12757 ; CHECK: $ymm16 = VPUNPCKLWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2758 $ymm16 = VPUNPCKLWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2759 ; CHECK: $ymm16 = VPUNPCKLWDZ256rr $ymm16, $ymm12760 $ymm16 = VPUNPCKLWDZ256rr $ymm16, $ymm12761 ; CHECK: $ymm16 = VFMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2762 $ymm16 = VFMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2763 ; CHECK: $ymm16 = VFMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2764 $ymm16 = VFMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2765 ; CHECK: $ymm16 = VFMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2766 $ymm16 = VFMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2767 ; CHECK: $ymm16 = VFMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2768 $ymm16 = VFMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2769 ; CHECK: $ymm16 = VFMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2770 $ymm16 = VFMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2771 ; CHECK: $ymm16 = VFMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2772 $ymm16 = VFMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2773 ; CHECK: $ymm16 = VFMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2774 $ymm16 = VFMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2775 ; CHECK: $ymm16 = VFMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2776 $ymm16 = VFMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2777 ; CHECK: $ymm16 = VFMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2778 $ymm16 = VFMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2779 ; CHECK: $ymm16 = VFMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2780 $ymm16 = VFMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2781 ; CHECK: $ymm16 = VFMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2782 $ymm16 = VFMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2783 ; CHECK: $ymm16 = VFMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2784 $ymm16 = VFMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2785 ; CHECK: $ymm16 = VFMADDSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2786 $ymm16 = VFMADDSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2787 ; CHECK: $ymm16 = VFMADDSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2788 $ymm16 = VFMADDSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2789 ; CHECK: $ymm16 = VFMADDSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2790 $ymm16 = VFMADDSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2791 ; CHECK: $ymm16 = VFMADDSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2792 $ymm16 = VFMADDSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2793 ; CHECK: $ymm16 = VFMADDSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2794 $ymm16 = VFMADDSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2795 ; CHECK: $ymm16 = VFMADDSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2796 $ymm16 = VFMADDSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2797 ; CHECK: $ymm16 = VFMADDSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2798 $ymm16 = VFMADDSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2799 ; CHECK: $ymm16 = VFMADDSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2800 $ymm16 = VFMADDSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2801 ; CHECK: $ymm16 = VFMADDSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2802 $ymm16 = VFMADDSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2803 ; CHECK: $ymm16 = VFMADDSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2804 $ymm16 = VFMADDSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2805 ; CHECK: $ymm16 = VFMADDSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2806 $ymm16 = VFMADDSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2807 ; CHECK: $ymm16 = VFMADDSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2808 $ymm16 = VFMADDSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2809 ; CHECK: $ymm16 = VFMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2810 $ymm16 = VFMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2811 ; CHECK: $ymm16 = VFMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2812 $ymm16 = VFMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2813 ; CHECK: $ymm16 = VFMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2814 $ymm16 = VFMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2815 ; CHECK: $ymm16 = VFMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2816 $ymm16 = VFMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2817 ; CHECK: $ymm16 = VFMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2818 $ymm16 = VFMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2819 ; CHECK: $ymm16 = VFMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2820 $ymm16 = VFMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2821 ; CHECK: $ymm16 = VFMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2822 $ymm16 = VFMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2823 ; CHECK: $ymm16 = VFMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2824 $ymm16 = VFMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2825 ; CHECK: $ymm16 = VFMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2826 $ymm16 = VFMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2827 ; CHECK: $ymm16 = VFMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2828 $ymm16 = VFMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2829 ; CHECK: $ymm16 = VFMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2830 $ymm16 = VFMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2831 ; CHECK: $ymm16 = VFMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2832 $ymm16 = VFMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2833 ; CHECK: $ymm16 = VFMSUBADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2834 $ymm16 = VFMSUBADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2835 ; CHECK: $ymm16 = VFMSUBADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2836 $ymm16 = VFMSUBADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2837 ; CHECK: $ymm16 = VFMSUBADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2838 $ymm16 = VFMSUBADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2839 ; CHECK: $ymm16 = VFMSUBADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2840 $ymm16 = VFMSUBADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2841 ; CHECK: $ymm16 = VFMSUBADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2842 $ymm16 = VFMSUBADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2843 ; CHECK: $ymm16 = VFMSUBADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2844 $ymm16 = VFMSUBADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2845 ; CHECK: $ymm16 = VFMSUBADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2846 $ymm16 = VFMSUBADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2847 ; CHECK: $ymm16 = VFMSUBADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2848 $ymm16 = VFMSUBADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2849 ; CHECK: $ymm16 = VFMSUBADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2850 $ymm16 = VFMSUBADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2851 ; CHECK: $ymm16 = VFMSUBADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2852 $ymm16 = VFMSUBADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2853 ; CHECK: $ymm16 = VFMSUBADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2854 $ymm16 = VFMSUBADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2855 ; CHECK: $ymm16 = VFMSUBADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2856 $ymm16 = VFMSUBADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2857 ; CHECK: $ymm16 = VFNMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2858 $ymm16 = VFNMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2859 ; CHECK: $ymm16 = VFNMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2860 $ymm16 = VFNMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2861 ; CHECK: $ymm16 = VFNMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2862 $ymm16 = VFNMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2863 ; CHECK: $ymm16 = VFNMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2864 $ymm16 = VFNMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2865 ; CHECK: $ymm16 = VFNMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2866 $ymm16 = VFNMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2867 ; CHECK: $ymm16 = VFNMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2868 $ymm16 = VFNMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2869 ; CHECK: $ymm16 = VFNMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2870 $ymm16 = VFNMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2871 ; CHECK: $ymm16 = VFNMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2872 $ymm16 = VFNMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2873 ; CHECK: $ymm16 = VFNMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2874 $ymm16 = VFNMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2875 ; CHECK: $ymm16 = VFNMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2876 $ymm16 = VFNMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2877 ; CHECK: $ymm16 = VFNMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2878 $ymm16 = VFNMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2879 ; CHECK: $ymm16 = VFNMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2880 $ymm16 = VFNMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2881 ; CHECK: $ymm16 = VFNMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2882 $ymm16 = VFNMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2883 ; CHECK: $ymm16 = VFNMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2884 $ymm16 = VFNMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2885 ; CHECK: $ymm16 = VFNMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2886 $ymm16 = VFNMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2887 ; CHECK: $ymm16 = VFNMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2888 $ymm16 = VFNMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2889 ; CHECK: $ymm16 = VFNMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2890 $ymm16 = VFNMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2891 ; CHECK: $ymm16 = VFNMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2892 $ymm16 = VFNMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2893 ; CHECK: $ymm16 = VFNMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2894 $ymm16 = VFNMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2895 ; CHECK: $ymm16 = VFNMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2896 $ymm16 = VFNMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2897 ; CHECK: $ymm16 = VFNMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2898 $ymm16 = VFNMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2899 ; CHECK: $ymm16 = VFNMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2900 $ymm16 = VFNMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2901 ; CHECK: $ymm16 = VFNMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2902 $ymm16 = VFNMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr2903 ; CHECK: $ymm16 = VFNMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2904 $ymm16 = VFNMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr2905 ; CHECK: $ymm16 = VPSRADZ256ri $ymm16, 72906 $ymm16 = VPSRADZ256ri $ymm16, 72907 ; CHECK: $ymm16 = VPSRADZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2908 $ymm16 = VPSRADZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2909 ; CHECK: $ymm16 = VPSRADZ256rr $ymm16, $xmm12910 $ymm16 = VPSRADZ256rr $ymm16, $xmm12911 ; CHECK: $ymm16 = VPSRAVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2912 $ymm16 = VPSRAVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2913 ; CHECK: $ymm16 = VPSRAVDZ256rr $ymm16, $ymm12914 $ymm16 = VPSRAVDZ256rr $ymm16, $ymm12915 ; CHECK: $ymm16 = VPSRAWZ256ri $ymm16, 72916 $ymm16 = VPSRAWZ256ri $ymm16, 72917 ; CHECK: $ymm16 = VPSRAWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2918 $ymm16 = VPSRAWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2919 ; CHECK: $ymm16 = VPSRAWZ256rr $ymm16, $xmm12920 $ymm16 = VPSRAWZ256rr $ymm16, $xmm12921 ; CHECK: $ymm16 = VPSRLDQZ256ri $ymm16, 72922 $ymm16 = VPSRLDQZ256ri $ymm16, 72923 ; CHECK: $ymm16 = VPSRLDZ256ri $ymm16, 72924 $ymm16 = VPSRLDZ256ri $ymm16, 72925 ; CHECK: $ymm16 = VPSRLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2926 $ymm16 = VPSRLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2927 ; CHECK: $ymm16 = VPSRLDZ256rr $ymm16, $xmm12928 $ymm16 = VPSRLDZ256rr $ymm16, $xmm12929 ; CHECK: $ymm16 = VPSRLQZ256ri $ymm16, 72930 $ymm16 = VPSRLQZ256ri $ymm16, 72931 ; CHECK: $ymm16 = VPSRLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2932 $ymm16 = VPSRLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2933 ; CHECK: $ymm16 = VPSRLQZ256rr $ymm16, $xmm12934 $ymm16 = VPSRLQZ256rr $ymm16, $xmm12935 ; CHECK: $ymm16 = VPSRLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2936 $ymm16 = VPSRLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2937 ; CHECK: $ymm16 = VPSRLVDZ256rr $ymm16, $ymm12938 $ymm16 = VPSRLVDZ256rr $ymm16, $ymm12939 ; CHECK: $ymm16 = VPSRLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2940 $ymm16 = VPSRLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2941 ; CHECK: $ymm16 = VPSRLVQZ256rr $ymm16, $ymm12942 $ymm16 = VPSRLVQZ256rr $ymm16, $ymm12943 ; CHECK: $ymm16 = VPSRLWZ256ri $ymm16, 72944 $ymm16 = VPSRLWZ256ri $ymm16, 72945 ; CHECK: $ymm16 = VPSRLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2946 $ymm16 = VPSRLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg2947 ; CHECK: $ymm16 = VPSRLWZ256rr $ymm16, $xmm12948 $ymm16 = VPSRLWZ256rr $ymm16, $xmm12949 ; CHECK: $ymm16 = VPMOVSXBDZ256rm $rip, 1, $noreg, 0, $noreg2950 $ymm16 = VPMOVSXBDZ256rm $rip, 1, $noreg, 0, $noreg2951 ; CHECK: $ymm16 = VPMOVSXBDZ256rr $xmm02952 $ymm16 = VPMOVSXBDZ256rr $xmm02953 ; CHECK: $ymm16 = VPMOVSXBQZ256rm $rip, 1, $noreg, 0, $noreg2954 $ymm16 = VPMOVSXBQZ256rm $rip, 1, $noreg, 0, $noreg2955 ; CHECK: $ymm16 = VPMOVSXBQZ256rr $xmm02956 $ymm16 = VPMOVSXBQZ256rr $xmm02957 ; CHECK: $ymm16 = VPMOVSXBWZ256rm $rip, 1, $noreg, 0, $noreg2958 $ymm16 = VPMOVSXBWZ256rm $rip, 1, $noreg, 0, $noreg2959 ; CHECK: $ymm16 = VPMOVSXBWZ256rr $xmm02960 $ymm16 = VPMOVSXBWZ256rr $xmm02961 ; CHECK: $ymm16 = VPMOVSXDQZ256rm $rip, 1, $noreg, 0, $noreg2962 $ymm16 = VPMOVSXDQZ256rm $rip, 1, $noreg, 0, $noreg2963 ; CHECK: $ymm16 = VPMOVSXDQZ256rr $xmm02964 $ymm16 = VPMOVSXDQZ256rr $xmm02965 ; CHECK: $ymm16 = VPMOVSXWDZ256rm $rip, 1, $noreg, 0, $noreg2966 $ymm16 = VPMOVSXWDZ256rm $rip, 1, $noreg, 0, $noreg2967 ; CHECK: $ymm16 = VPMOVSXWDZ256rr $xmm02968 $ymm16 = VPMOVSXWDZ256rr $xmm02969 ; CHECK: $ymm16 = VPMOVSXWQZ256rm $rip, 1, $noreg, 0, $noreg2970 $ymm16 = VPMOVSXWQZ256rm $rip, 1, $noreg, 0, $noreg2971 ; CHECK: $ymm16 = VPMOVSXWQZ256rr $xmm02972 $ymm16 = VPMOVSXWQZ256rr $xmm02973 ; CHECK: $ymm16 = VPMOVZXBDZ256rm $rip, 1, $noreg, 0, $noreg2974 $ymm16 = VPMOVZXBDZ256rm $rip, 1, $noreg, 0, $noreg2975 ; CHECK: $ymm16 = VPMOVZXBDZ256rr $xmm02976 $ymm16 = VPMOVZXBDZ256rr $xmm02977 ; CHECK: $ymm16 = VPMOVZXBQZ256rm $rip, 1, $noreg, 0, $noreg2978 $ymm16 = VPMOVZXBQZ256rm $rip, 1, $noreg, 0, $noreg2979 ; CHECK: $ymm16 = VPMOVZXBQZ256rr $xmm02980 $ymm16 = VPMOVZXBQZ256rr $xmm02981 ; CHECK: $ymm16 = VPMOVZXBWZ256rm $rip, 1, $noreg, 0, $noreg2982 $ymm16 = VPMOVZXBWZ256rm $rip, 1, $noreg, 0, $noreg2983 ; CHECK: $ymm16 = VPMOVZXBWZ256rr $xmm02984 $ymm16 = VPMOVZXBWZ256rr $xmm02985 ; CHECK: $ymm16 = VPMOVZXDQZ256rm $rip, 1, $noreg, 0, $noreg2986 $ymm16 = VPMOVZXDQZ256rm $rip, 1, $noreg, 0, $noreg2987 ; CHECK: $ymm16 = VPMOVZXDQZ256rr $xmm02988 $ymm16 = VPMOVZXDQZ256rr $xmm02989 ; CHECK: $ymm16 = VPMOVZXWDZ256rm $rip, 1, $noreg, 0, $noreg2990 $ymm16 = VPMOVZXWDZ256rm $rip, 1, $noreg, 0, $noreg2991 ; CHECK: $ymm16 = VPMOVZXWDZ256rr $xmm02992 $ymm16 = VPMOVZXWDZ256rr $xmm02993 ; CHECK: $ymm16 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg2994 $ymm16 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg2995 ; CHECK: $ymm16 = VPMOVZXWQZ256rr $xmm02996 $ymm16 = VPMOVZXWQZ256rr $xmm02997 ; CHECK: $ymm16 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg2998 $ymm16 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg2999 ; CHECK: $ymm16 = VBROADCASTF32X2Z256rr $xmm163000 $ymm16 = VBROADCASTF32X2Z256rr $xmm163001 ; CHECK: $ymm16 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg3002 $ymm16 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg3003 ; CHECK: $ymm16 = VBROADCASTSDZ256rm $rip, 1, $noreg, 0, $noreg3004 $ymm16 = VBROADCASTSDZ256rm $rip, 1, $noreg, 0, $noreg3005 ; CHECK: $ymm16 = VBROADCASTSDZ256rr $xmm03006 $ymm16 = VBROADCASTSDZ256rr $xmm03007 ; CHECK: $ymm16 = VBROADCASTSSZ256rm $rip, 1, $noreg, 0, $noreg3008 $ymm16 = VBROADCASTSSZ256rm $rip, 1, $noreg, 0, $noreg3009 ; CHECK: $ymm16 = VBROADCASTSSZ256rr $xmm03010 $ymm16 = VBROADCASTSSZ256rr $xmm03011 ; CHECK: $ymm16 = VPBROADCASTBZ256rm $rip, 1, $noreg, 0, $noreg3012 $ymm16 = VPBROADCASTBZ256rm $rip, 1, $noreg, 0, $noreg3013 ; CHECK: $ymm16 = VPBROADCASTBZ256rr $xmm03014 $ymm16 = VPBROADCASTBZ256rr $xmm03015 ; CHECK: $ymm16 = VPBROADCASTDZ256rm $rip, 1, $noreg, 0, $noreg3016 $ymm16 = VPBROADCASTDZ256rm $rip, 1, $noreg, 0, $noreg3017 ; CHECK: $ymm16 = VPBROADCASTDZ256rr $xmm03018 $ymm16 = VPBROADCASTDZ256rr $xmm03019 ; CHECK: $ymm16 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg3020 $ymm16 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg3021 ; CHECK: $ymm16 = VPBROADCASTWZ256rr $xmm03022 $ymm16 = VPBROADCASTWZ256rr $xmm03023 ; CHECK: $ymm16 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg3024 $ymm16 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg3025 ; CHECK: $ymm16 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg3026 $ymm16 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg3027 ; CHECK: $ymm16 = VBROADCASTI32X2Z256rr $xmm163028 $ymm16 = VBROADCASTI32X2Z256rr $xmm163029 ; CHECK: $ymm16 = VPBROADCASTQZ256rm $rip, 1, $noreg, 0, $noreg3030 $ymm16 = VPBROADCASTQZ256rm $rip, 1, $noreg, 0, $noreg3031 ; CHECK: $ymm16 = VPBROADCASTQZ256rr $xmm03032 $ymm16 = VPBROADCASTQZ256rr $xmm03033 ; CHECK: $ymm16 = VPABSBZ256rm $rip, 1, $noreg, 0, $noreg3034 $ymm16 = VPABSBZ256rm $rip, 1, $noreg, 0, $noreg3035 ; CHECK: $ymm16 = VPABSBZ256rr $ymm163036 $ymm16 = VPABSBZ256rr $ymm163037 ; CHECK: $ymm16 = VPABSDZ256rm $rip, 1, $noreg, 0, $noreg3038 $ymm16 = VPABSDZ256rm $rip, 1, $noreg, 0, $noreg3039 ; CHECK: $ymm16 = VPABSDZ256rr $ymm163040 $ymm16 = VPABSDZ256rr $ymm163041 ; CHECK: $ymm16 = VPABSWZ256rm $rip, 1, $noreg, 0, $noreg3042 $ymm16 = VPABSWZ256rm $rip, 1, $noreg, 0, $noreg3043 ; CHECK: $ymm16 = VPABSWZ256rr $ymm163044 $ymm16 = VPABSWZ256rr $ymm163045 ; CHECK: $ymm16 = VPSADBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3046 $ymm16 = VPSADBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3047 ; CHECK: $ymm16 = VPSADBWZ256rr $ymm16, $ymm13048 $ymm16 = VPSADBWZ256rr $ymm16, $ymm13049 ; CHECK: $ymm16 = VPERMDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3050 $ymm16 = VPERMDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3051 ; CHECK: $ymm16 = VPERMDZ256rr $ymm1, $ymm163052 $ymm16 = VPERMDZ256rr $ymm1, $ymm163053 ; CHECK: $ymm16 = VPERMILPDZ256mi $rdi, 1, $noreg, 0, $noreg, 73054 $ymm16 = VPERMILPDZ256mi $rdi, 1, $noreg, 0, $noreg, 73055 ; CHECK: $ymm16 = VPERMILPDZ256ri $ymm16, 73056 $ymm16 = VPERMILPDZ256ri $ymm16, 73057 ; CHECK: $ymm16 = VPERMILPDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3058 $ymm16 = VPERMILPDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3059 ; CHECK: $ymm16 = VPERMILPDZ256rr $ymm1, $ymm163060 $ymm16 = VPERMILPDZ256rr $ymm1, $ymm163061 ; CHECK: $ymm16 = VPERMILPSZ256mi $rdi, 1, $noreg, 0, $noreg, 73062 $ymm16 = VPERMILPSZ256mi $rdi, 1, $noreg, 0, $noreg, 73063 ; CHECK: $ymm16 = VPERMILPSZ256ri $ymm16, 73064 $ymm16 = VPERMILPSZ256ri $ymm16, 73065 ; CHECK: $ymm16 = VPERMILPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3066 $ymm16 = VPERMILPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3067 ; CHECK: $ymm16 = VPERMILPSZ256rr $ymm1, $ymm163068 $ymm16 = VPERMILPSZ256rr $ymm1, $ymm163069 ; CHECK: $ymm16 = VPERMPDZ256mi $rdi, 1, $noreg, 0, $noreg, 73070 $ymm16 = VPERMPDZ256mi $rdi, 1, $noreg, 0, $noreg, 73071 ; CHECK: $ymm16 = VPERMPDZ256ri $ymm16, 73072 $ymm16 = VPERMPDZ256ri $ymm16, 73073 ; CHECK: $ymm16 = VPERMPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3074 $ymm16 = VPERMPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3075 ; CHECK: $ymm16 = VPERMPSZ256rr $ymm1, $ymm163076 $ymm16 = VPERMPSZ256rr $ymm1, $ymm163077 ; CHECK: $ymm16 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 73078 $ymm16 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 73079 ; CHECK: $ymm16 = VPERMQZ256ri $ymm16, 73080 $ymm16 = VPERMQZ256ri $ymm16, 73081 ; CHECK: $ymm16 = VPSLLDQZ256ri $ymm16, 143082 $ymm16 = VPSLLDQZ256ri $ymm16, 143083 ; CHECK: $ymm16 = VPSLLDZ256ri $ymm16, 73084 $ymm16 = VPSLLDZ256ri $ymm16, 73085 ; CHECK: $ymm16 = VPSLLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3086 $ymm16 = VPSLLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3087 ; CHECK: $ymm16 = VPSLLDZ256rr $ymm16, $xmm163088 $ymm16 = VPSLLDZ256rr $ymm16, $xmm163089 ; CHECK: $ymm16 = VPSLLQZ256ri $ymm16, 73090 $ymm16 = VPSLLQZ256ri $ymm16, 73091 ; CHECK: $ymm16 = VPSLLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3092 $ymm16 = VPSLLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3093 ; CHECK: $ymm16 = VPSLLQZ256rr $ymm16, $xmm163094 $ymm16 = VPSLLQZ256rr $ymm16, $xmm163095 ; CHECK: $ymm16 = VPSLLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3096 $ymm16 = VPSLLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3097 ; CHECK: $ymm16 = VPSLLVDZ256rr $ymm16, $ymm163098 $ymm16 = VPSLLVDZ256rr $ymm16, $ymm163099 ; CHECK: $ymm16 = VPSLLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3100 $ymm16 = VPSLLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3101 ; CHECK: $ymm16 = VPSLLVQZ256rr $ymm16, $ymm163102 $ymm16 = VPSLLVQZ256rr $ymm16, $ymm163103 ; CHECK: $ymm16 = VPSLLWZ256ri $ymm16, 73104 $ymm16 = VPSLLWZ256ri $ymm16, 73105 ; CHECK: $ymm16 = VPSLLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3106 $ymm16 = VPSLLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg3107 ; CHECK: $ymm16 = VPSLLWZ256rr $ymm16, $xmm163108 $ymm16 = VPSLLWZ256rr $ymm16, $xmm163109 ; CHECK: $ymm16 = VCVTDQ2PDZ256rm $rdi, 1, $noreg, 0, $noreg3110 $ymm16 = VCVTDQ2PDZ256rm $rdi, 1, $noreg, 0, $noreg3111 ; CHECK: $ymm16 = VCVTDQ2PDZ256rr $xmm03112 $ymm16 = VCVTDQ2PDZ256rr $xmm0, implicit $mxcsr3113 ; CHECK: $ymm16 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3114 $ymm16 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3115 ; CHECK: $ymm16 = VCVTDQ2PSZ256rr $ymm16, implicit $mxcsr3116 $ymm16 = VCVTDQ2PSZ256rr $ymm16, implicit $mxcsr3117 ; CHECK: $xmm16 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3118 $xmm16 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3119 ; CHECK: $xmm16 = VCVTPD2DQZ256rr $ymm16, implicit $mxcsr3120 $xmm16 = VCVTPD2DQZ256rr $ymm16, implicit $mxcsr3121 ; CHECK: $xmm16 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3122 $xmm16 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3123 ; CHECK: $xmm16 = VCVTPD2PSZ256rr $ymm16, implicit $mxcsr3124 $xmm16 = VCVTPD2PSZ256rr $ymm16, implicit $mxcsr3125 ; CHECK: $ymm16 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3126 $ymm16 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3127 ; CHECK: $ymm16 = VCVTPS2DQZ256rr $ymm16, implicit $mxcsr3128 $ymm16 = VCVTPS2DQZ256rr $ymm16, implicit $mxcsr3129 ; CHECK: $ymm16 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3130 $ymm16 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3131 ; CHECK: $ymm16 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr3132 $ymm16 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr3133 ; CHECK: VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16, 0, implicit $mxcsr3134 VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16, 0, implicit $mxcsr3135 ; CHECK: $xmm0 = VCVTPS2PHZ256rr $ymm16, 0, implicit $mxcsr3136 $xmm0 = VCVTPS2PHZ256rr $ymm16, 0, implicit $mxcsr3137 ; CHECK: $ymm16 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3138 $ymm16 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3139 ; CHECK: $ymm16 = VCVTPH2PSZ256rr $xmm16, implicit $mxcsr3140 $ymm16 = VCVTPH2PSZ256rr $xmm16, implicit $mxcsr3141 ; CHECK: $xmm16 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3142 $xmm16 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3143 ; CHECK: $xmm16 = VCVTTPD2DQZ256rr $ymm16, implicit $mxcsr3144 $xmm16 = VCVTTPD2DQZ256rr $ymm16, implicit $mxcsr3145 ; CHECK: $ymm16 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3146 $ymm16 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3147 ; CHECK: $ymm16 = VCVTTPS2DQZ256rr $ymm16, implicit $mxcsr3148 $ymm16 = VCVTTPS2DQZ256rr $ymm16, implicit $mxcsr3149 ; CHECK: $ymm16 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3150 $ymm16 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3151 ; CHECK: $ymm16 = VSQRTPDZ256r $ymm16, implicit $mxcsr3152 $ymm16 = VSQRTPDZ256r $ymm16, implicit $mxcsr3153 ; CHECK: $ymm16 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3154 $ymm16 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3155 ; CHECK: $ymm16 = VSQRTPSZ256r $ymm16, implicit $mxcsr3156 $ymm16 = VSQRTPSZ256r $ymm16, implicit $mxcsr3157 ; CHECK: $ymm16 = VPALIGNRZ256rmi $ymm16, $rdi, 1, $noreg, 0, $noreg, 13158 $ymm16 = VPALIGNRZ256rmi $ymm16, $rdi, 1, $noreg, 0, $noreg, 13159 ; CHECK: $ymm16 = VPALIGNRZ256rri $ymm16, $ymm1, 13160 $ymm16 = VPALIGNRZ256rri $ymm16, $ymm1, 13161 ; CHECK: $ymm16 = VMOVUPSZ256rm $rdi, 1, $noreg, 0, $noreg3162 $ymm16 = VMOVUPSZ256rm $rdi, 1, $noreg, 0, $noreg3163 ; CHECK: $ymm16 = VMOVUPSZ256rr $ymm163164 $ymm16 = VMOVUPSZ256rr $ymm163165 ; CHECK: $ymm16 = VPSHUFBZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3166 $ymm16 = VPSHUFBZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg3167 ; CHECK: $ymm16 = VPSHUFBZ256rr $ymm16, $ymm13168 $ymm16 = VPSHUFBZ256rr $ymm16, $ymm13169 ; CHECK: $ymm16 = VPSHUFDZ256mi $rdi, 1, $noreg, 0, $noreg, -243170 $ymm16 = VPSHUFDZ256mi $rdi, 1, $noreg, 0, $noreg, -243171 ; CHECK: $ymm16 = VPSHUFDZ256ri $ymm16, -243172 $ymm16 = VPSHUFDZ256ri $ymm16, -243173 ; CHECK: $ymm16 = VPSHUFHWZ256mi $rdi, 1, $noreg, 0, $noreg, -243174 $ymm16 = VPSHUFHWZ256mi $rdi, 1, $noreg, 0, $noreg, -243175 ; CHECK: $ymm16 = VPSHUFHWZ256ri $ymm16, -243176 $ymm16 = VPSHUFHWZ256ri $ymm16, -243177 ; CHECK: $ymm16 = VPSHUFLWZ256mi $rdi, 1, $noreg, 0, $noreg, -243178 $ymm16 = VPSHUFLWZ256mi $rdi, 1, $noreg, 0, $noreg, -243179 ; CHECK: $ymm16 = VPSHUFLWZ256ri $ymm16, -243180 $ymm16 = VPSHUFLWZ256ri $ymm16, -243181 ; CHECK: $ymm16 = VSHUFPDZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -243182 $ymm16 = VSHUFPDZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -243183 ; CHECK: $ymm16 = VSHUFPDZ256rri $ymm16, $ymm1, -243184 $ymm16 = VSHUFPDZ256rri $ymm16, $ymm1, -243185 ; CHECK: $ymm16 = VSHUFPSZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -243186 $ymm16 = VSHUFPSZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -243187 ; CHECK: $ymm16 = VSHUFPSZ256rri $ymm16, $ymm1, -243188 $ymm16 = VSHUFPSZ256rri $ymm16, $ymm1, -243189 ; CHECK: $ymm16 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr3190 $ymm16 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr3191 ; CHECK: $ymm16 = VRNDSCALEPDZ256rri $ymm16, 15, implicit $mxcsr3192 $ymm16 = VRNDSCALEPDZ256rri $ymm16, 15, implicit $mxcsr3193 ; CHECK: $ymm16 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr3194 $ymm16 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr3195 ; CHECK: $ymm16 = VRNDSCALEPSZ256rri $ymm16, 15, implicit $mxcsr3196 $ymm16 = VRNDSCALEPSZ256rri $ymm16, 15, implicit $mxcsr3197 ; CHECK: $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr3198 $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr3199 ; CHECK: $ymm0 = VRNDSCALEPDZ256rri $ymm0, 31, implicit $mxcsr3200 $ymm0 = VRNDSCALEPDZ256rri $ymm0, 31, implicit $mxcsr3201 ; CHECK: $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr3202 $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr3203 ; CHECK: $ymm0 = VRNDSCALEPSZ256rri $ymm0, 31, implicit $mxcsr3204 $ymm0 = VRNDSCALEPSZ256rri $ymm0, 31, implicit $mxcsr3205 ; CHECK: $ymm16 = VSHUFF32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283206 $ymm16 = VSHUFF32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283207 ; CHECK: $ymm16 = VSHUFF32X4Z256rri $ymm16, $ymm1, 2283208 $ymm16 = VSHUFF32X4Z256rri $ymm16, $ymm1, 2283209 ; CHECK: $ymm16 = VSHUFF64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283210 $ymm16 = VSHUFF64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283211 ; CHECK: $ymm16 = VSHUFF64X2Z256rri $ymm16, $ymm1, 2283212 $ymm16 = VSHUFF64X2Z256rri $ymm16, $ymm1, 2283213 ; CHECK: $ymm16 = VSHUFI32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283214 $ymm16 = VSHUFI32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283215 ; CHECK: $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 2283216 $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 2283217 ; CHECK: $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283218 $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 2283219 ; CHECK: $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 2283220 $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 2283221 3222 RET643223...3224---3225 # CHECK-LABEL: name: evex_z128_to_evex_test3226 # CHECK: bb.0:3227 3228name: evex_z128_to_evex_test3229body: |3230 bb.0:3231 ; CHECK: VMOVAPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163232 VMOVAPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163233 ; CHECK: $xmm16 = VMOVAPDZ128rm $rip, 1, $noreg, 0, $noreg3234 $xmm16 = VMOVAPDZ128rm $rip, 1, $noreg, 0, $noreg3235 ; CHECK: $xmm16 = VMOVAPDZ128rr $xmm163236 $xmm16 = VMOVAPDZ128rr $xmm163237 ; CHECK: VMOVAPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163238 VMOVAPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163239 ; CHECK: $xmm16 = VMOVAPSZ128rm $rip, 1, $noreg, 0, $noreg3240 $xmm16 = VMOVAPSZ128rm $rip, 1, $noreg, 0, $noreg3241 ; CHECK: $xmm16 = VMOVAPSZ128rr $xmm163242 $xmm16 = VMOVAPSZ128rr $xmm163243 ; CHECK: VMOVDQA32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163244 VMOVDQA32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163245 ; CHECK: $xmm16 = VMOVDQA32Z128rm $rip, 1, $noreg, 0, $noreg3246 $xmm16 = VMOVDQA32Z128rm $rip, 1, $noreg, 0, $noreg3247 ; CHECK: $xmm16 = VMOVDQA32Z128rr $xmm163248 $xmm16 = VMOVDQA32Z128rr $xmm163249 ; CHECK: VMOVDQA64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163250 VMOVDQA64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163251 ; CHECK: $xmm16 = VMOVDQA64Z128rm $rip, 1, $noreg, 0, $noreg3252 $xmm16 = VMOVDQA64Z128rm $rip, 1, $noreg, 0, $noreg3253 ; CHECK: $xmm16 = VMOVDQA64Z128rr $xmm163254 $xmm16 = VMOVDQA64Z128rr $xmm163255 ; CHECK: VMOVDQU16Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163256 VMOVDQU16Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163257 ; CHECK: $xmm16 = VMOVDQU16Z128rm $rip, 1, $noreg, 0, $noreg3258 $xmm16 = VMOVDQU16Z128rm $rip, 1, $noreg, 0, $noreg3259 ; CHECK: $xmm16 = VMOVDQU16Z128rr $xmm163260 $xmm16 = VMOVDQU16Z128rr $xmm163261 ; CHECK: VMOVDQU32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163262 VMOVDQU32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163263 ; CHECK: $xmm16 = VMOVDQU32Z128rm $rip, 1, $noreg, 0, $noreg3264 $xmm16 = VMOVDQU32Z128rm $rip, 1, $noreg, 0, $noreg3265 ; CHECK: $xmm16 = VMOVDQU32Z128rr $xmm163266 $xmm16 = VMOVDQU32Z128rr $xmm163267 ; CHECK: VMOVDQU64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163268 VMOVDQU64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163269 ; CHECK: $xmm16 = VMOVDQU64Z128rm $rip, 1, $noreg, 0, $noreg3270 $xmm16 = VMOVDQU64Z128rm $rip, 1, $noreg, 0, $noreg3271 ; CHECK: $xmm16 = VMOVDQU64Z128rr $xmm163272 $xmm16 = VMOVDQU64Z128rr $xmm163273 ; CHECK: VMOVDQU8Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163274 VMOVDQU8Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm163275 ; CHECK: $xmm16 = VMOVDQU8Z128rm $rip, 1, $noreg, 0, $noreg3276 $xmm16 = VMOVDQU8Z128rm $rip, 1, $noreg, 0, $noreg3277 ; CHECK: $xmm16 = VMOVDQU8Z128rr $xmm163278 $xmm16 = VMOVDQU8Z128rr $xmm163279 ; CHECK: $xmm16 = VMOVNTDQAZ128rm $rip, 1, $noreg, 0, $noreg3280 $xmm16 = VMOVNTDQAZ128rm $rip, 1, $noreg, 0, $noreg3281 ; CHECK: VMOVUPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163282 VMOVUPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163283 ; CHECK: $xmm16 = VMOVUPDZ128rm $rip, 1, $noreg, 0, $noreg3284 $xmm16 = VMOVUPDZ128rm $rip, 1, $noreg, 0, $noreg3285 ; CHECK: $xmm16 = VMOVUPDZ128rr $xmm163286 $xmm16 = VMOVUPDZ128rr $xmm163287 ; CHECK: VMOVUPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163288 VMOVUPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163289 ; CHECK: $xmm16 = VMOVUPSZ128rm $rip, 1, $noreg, 0, $noreg3290 $xmm16 = VMOVUPSZ128rm $rip, 1, $noreg, 0, $noreg3291 ; CHECK: $xmm16 = VMOVUPSZ128rr $xmm163292 $xmm16 = VMOVUPSZ128rr $xmm163293 ; CHECK: VMOVNTDQZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163294 VMOVNTDQZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163295 ; CHECK: VMOVNTPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163296 VMOVNTPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163297 ; CHECK: VMOVNTPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163298 VMOVNTPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163299 ; CHECK: $xmm16 = VPMOVSXBDZ128rm $rip, 1, $noreg, 0, $noreg3300 $xmm16 = VPMOVSXBDZ128rm $rip, 1, $noreg, 0, $noreg3301 ; CHECK: $xmm16 = VPMOVSXBDZ128rr $xmm163302 $xmm16 = VPMOVSXBDZ128rr $xmm163303 ; CHECK: $xmm16 = VPMOVSXBQZ128rm $rip, 1, $noreg, 0, $noreg3304 $xmm16 = VPMOVSXBQZ128rm $rip, 1, $noreg, 0, $noreg3305 ; CHECK: $xmm16 = VPMOVSXBQZ128rr $xmm163306 $xmm16 = VPMOVSXBQZ128rr $xmm163307 ; CHECK: $xmm16 = VPMOVSXBWZ128rm $rip, 1, $noreg, 0, $noreg3308 $xmm16 = VPMOVSXBWZ128rm $rip, 1, $noreg, 0, $noreg3309 ; CHECK: $xmm16 = VPMOVSXBWZ128rr $xmm163310 $xmm16 = VPMOVSXBWZ128rr $xmm163311 ; CHECK: $xmm16 = VPMOVSXDQZ128rm $rip, 1, $noreg, 0, $noreg3312 $xmm16 = VPMOVSXDQZ128rm $rip, 1, $noreg, 0, $noreg3313 ; CHECK: $xmm16 = VPMOVSXDQZ128rr $xmm163314 $xmm16 = VPMOVSXDQZ128rr $xmm163315 ; CHECK: $xmm16 = VPMOVSXWDZ128rm $rip, 1, $noreg, 0, $noreg3316 $xmm16 = VPMOVSXWDZ128rm $rip, 1, $noreg, 0, $noreg3317 ; CHECK: $xmm16 = VPMOVSXWDZ128rr $xmm163318 $xmm16 = VPMOVSXWDZ128rr $xmm163319 ; CHECK: $xmm16 = VPMOVSXWQZ128rm $rip, 1, $noreg, 0, $noreg3320 $xmm16 = VPMOVSXWQZ128rm $rip, 1, $noreg, 0, $noreg3321 ; CHECK: $xmm16 = VPMOVSXWQZ128rr $xmm163322 $xmm16 = VPMOVSXWQZ128rr $xmm163323 ; CHECK: $xmm16 = VPMOVZXBDZ128rm $rip, 1, $noreg, 0, $noreg3324 $xmm16 = VPMOVZXBDZ128rm $rip, 1, $noreg, 0, $noreg3325 ; CHECK: $xmm16 = VPMOVZXBDZ128rr $xmm163326 $xmm16 = VPMOVZXBDZ128rr $xmm163327 ; CHECK: $xmm16 = VPMOVZXBQZ128rm $rip, 1, $noreg, 0, $noreg3328 $xmm16 = VPMOVZXBQZ128rm $rip, 1, $noreg, 0, $noreg3329 ; CHECK: $xmm16 = VPMOVZXBQZ128rr $xmm163330 $xmm16 = VPMOVZXBQZ128rr $xmm163331 ; CHECK: $xmm16 = VPMOVZXBWZ128rm $rip, 1, $noreg, 0, $noreg3332 $xmm16 = VPMOVZXBWZ128rm $rip, 1, $noreg, 0, $noreg3333 ; CHECK: $xmm16 = VPMOVZXBWZ128rr $xmm163334 $xmm16 = VPMOVZXBWZ128rr $xmm163335 ; CHECK: $xmm16 = VPMOVZXDQZ128rm $rip, 1, $noreg, 0, $noreg3336 $xmm16 = VPMOVZXDQZ128rm $rip, 1, $noreg, 0, $noreg3337 ; CHECK: $xmm16 = VPMOVZXDQZ128rr $xmm163338 $xmm16 = VPMOVZXDQZ128rr $xmm163339 ; CHECK: $xmm16 = VPMOVZXWDZ128rm $rip, 1, $noreg, 0, $noreg3340 $xmm16 = VPMOVZXWDZ128rm $rip, 1, $noreg, 0, $noreg3341 ; CHECK: $xmm16 = VPMOVZXWDZ128rr $xmm163342 $xmm16 = VPMOVZXWDZ128rr $xmm163343 ; CHECK: $xmm16 = VPMOVZXWQZ128rm $rip, 1, $noreg, 0, $noreg3344 $xmm16 = VPMOVZXWQZ128rm $rip, 1, $noreg, 0, $noreg3345 ; CHECK: $xmm16 = VPMOVZXWQZ128rr $xmm163346 $xmm16 = VPMOVZXWQZ128rr $xmm163347 ; CHECK: VMOVHPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163348 VMOVHPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163349 ; CHECK: $xmm16 = VMOVHPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3350 $xmm16 = VMOVHPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3351 ; CHECK: VMOVHPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163352 VMOVHPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163353 ; CHECK: $xmm16 = VMOVHPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3354 $xmm16 = VMOVHPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3355 ; CHECK: VMOVLPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163356 VMOVLPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163357 ; CHECK: $xmm16 = VMOVLPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3358 $xmm16 = VMOVLPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3359 ; CHECK: VMOVLPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163360 VMOVLPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm163361 ; CHECK: $xmm16 = VMOVLPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3362 $xmm16 = VMOVLPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3363 ; CHECK: $xmm16 = VMAXCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3364 $xmm16 = VMAXCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3365 ; CHECK: $xmm16 = VMAXCPDZ128rr $xmm16, $xmm1, implicit $mxcsr3366 $xmm16 = VMAXCPDZ128rr $xmm16, $xmm1, implicit $mxcsr3367 ; CHECK: $xmm16 = VMAXCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3368 $xmm16 = VMAXCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3369 ; CHECK: $xmm16 = VMAXCPSZ128rr $xmm16, $xmm1, implicit $mxcsr3370 $xmm16 = VMAXCPSZ128rr $xmm16, $xmm1, implicit $mxcsr3371 ; CHECK: $xmm16 = VMAXPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3372 $xmm16 = VMAXPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3373 ; CHECK: $xmm16 = VMAXPDZ128rr $xmm16, $xmm1, implicit $mxcsr3374 $xmm16 = VMAXPDZ128rr $xmm16, $xmm1, implicit $mxcsr3375 ; CHECK: $xmm16 = VMAXPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3376 $xmm16 = VMAXPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3377 ; CHECK: $xmm16 = VMAXPSZ128rr $xmm16, $xmm1, implicit $mxcsr3378 $xmm16 = VMAXPSZ128rr $xmm16, $xmm1, implicit $mxcsr3379 ; CHECK: $xmm16 = VMINCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3380 $xmm16 = VMINCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3381 ; CHECK: $xmm16 = VMINCPDZ128rr $xmm16, $xmm1, implicit $mxcsr3382 $xmm16 = VMINCPDZ128rr $xmm16, $xmm1, implicit $mxcsr3383 ; CHECK: $xmm16 = VMINCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3384 $xmm16 = VMINCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3385 ; CHECK: $xmm16 = VMINCPSZ128rr $xmm16, $xmm1, implicit $mxcsr3386 $xmm16 = VMINCPSZ128rr $xmm16, $xmm1, implicit $mxcsr3387 ; CHECK: $xmm16 = VMINPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3388 $xmm16 = VMINPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3389 ; CHECK: $xmm16 = VMINPDZ128rr $xmm16, $xmm1, implicit $mxcsr3390 $xmm16 = VMINPDZ128rr $xmm16, $xmm1, implicit $mxcsr3391 ; CHECK: $xmm16 = VMINPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3392 $xmm16 = VMINPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3393 ; CHECK: $xmm16 = VMINPSZ128rr $xmm16, $xmm1, implicit $mxcsr3394 $xmm16 = VMINPSZ128rr $xmm16, $xmm1, implicit $mxcsr3395 ; CHECK: $xmm16 = VMULPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3396 $xmm16 = VMULPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3397 ; CHECK: $xmm16 = VMULPDZ128rr $xmm16, $xmm1, implicit $mxcsr3398 $xmm16 = VMULPDZ128rr $xmm16, $xmm1, implicit $mxcsr3399 ; CHECK: $xmm16 = VMULPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3400 $xmm16 = VMULPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3401 ; CHECK: $xmm16 = VMULPSZ128rr $xmm16, $xmm1, implicit $mxcsr3402 $xmm16 = VMULPSZ128rr $xmm16, $xmm1, implicit $mxcsr3403 ; CHECK: $xmm16 = VORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3404 $xmm16 = VORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3405 ; CHECK: $xmm16 = VORPDZ128rr $xmm16, $xmm13406 $xmm16 = VORPDZ128rr $xmm16, $xmm13407 ; CHECK: $xmm16 = VORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3408 $xmm16 = VORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3409 ; CHECK: $xmm16 = VORPSZ128rr $xmm16, $xmm13410 $xmm16 = VORPSZ128rr $xmm16, $xmm13411 ; CHECK: $xmm16 = VPADDBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3412 $xmm16 = VPADDBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3413 ; CHECK: $xmm16 = VPADDBZ128rr $xmm16, $xmm13414 $xmm16 = VPADDBZ128rr $xmm16, $xmm13415 ; CHECK: $xmm16 = VPADDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3416 $xmm16 = VPADDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3417 ; CHECK: $xmm16 = VPADDDZ128rr $xmm16, $xmm13418 $xmm16 = VPADDDZ128rr $xmm16, $xmm13419 ; CHECK: $xmm16 = VPADDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3420 $xmm16 = VPADDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3421 ; CHECK: $xmm16 = VPADDQZ128rr $xmm16, $xmm13422 $xmm16 = VPADDQZ128rr $xmm16, $xmm13423 ; CHECK: $xmm16 = VPADDSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3424 $xmm16 = VPADDSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3425 ; CHECK: $xmm16 = VPADDSBZ128rr $xmm16, $xmm13426 $xmm16 = VPADDSBZ128rr $xmm16, $xmm13427 ; CHECK: $xmm16 = VPADDSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3428 $xmm16 = VPADDSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3429 ; CHECK: $xmm16 = VPADDSWZ128rr $xmm16, $xmm13430 $xmm16 = VPADDSWZ128rr $xmm16, $xmm13431 ; CHECK: $xmm16 = VPADDUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3432 $xmm16 = VPADDUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3433 ; CHECK: $xmm16 = VPADDUSBZ128rr $xmm16, $xmm13434 $xmm16 = VPADDUSBZ128rr $xmm16, $xmm13435 ; CHECK: $xmm16 = VPADDUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3436 $xmm16 = VPADDUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3437 ; CHECK: $xmm16 = VPADDUSWZ128rr $xmm16, $xmm13438 $xmm16 = VPADDUSWZ128rr $xmm16, $xmm13439 ; CHECK: $xmm16 = VPADDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3440 $xmm16 = VPADDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3441 ; CHECK: $xmm16 = VPADDWZ128rr $xmm16, $xmm13442 $xmm16 = VPADDWZ128rr $xmm16, $xmm13443 ; CHECK: $xmm16 = VPANDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3444 $xmm16 = VPANDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3445 ; CHECK: $xmm16 = VPANDDZ128rr $xmm16, $xmm13446 $xmm16 = VPANDDZ128rr $xmm16, $xmm13447 ; CHECK: $xmm16 = VPANDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3448 $xmm16 = VPANDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3449 ; CHECK: $xmm16 = VPANDQZ128rr $xmm16, $xmm13450 $xmm16 = VPANDQZ128rr $xmm16, $xmm13451 ; CHECK: $xmm16 = VPANDNDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3452 $xmm16 = VPANDNDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3453 ; CHECK: $xmm16 = VPANDNDZ128rr $xmm16, $xmm13454 $xmm16 = VPANDNDZ128rr $xmm16, $xmm13455 ; CHECK: $xmm16 = VPANDNQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3456 $xmm16 = VPANDNQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3457 ; CHECK: $xmm16 = VPANDNQZ128rr $xmm16, $xmm13458 $xmm16 = VPANDNQZ128rr $xmm16, $xmm13459 ; CHECK: $xmm16 = VPAVGBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3460 $xmm16 = VPAVGBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3461 ; CHECK: $xmm16 = VPAVGBZ128rr $xmm16, $xmm13462 $xmm16 = VPAVGBZ128rr $xmm16, $xmm13463 ; CHECK: $xmm16 = VPAVGWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3464 $xmm16 = VPAVGWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3465 ; CHECK: $xmm16 = VPAVGWZ128rr $xmm16, $xmm13466 $xmm16 = VPAVGWZ128rr $xmm16, $xmm13467 ; CHECK: $xmm16 = VPMAXSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3468 $xmm16 = VPMAXSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3469 ; CHECK: $xmm16 = VPMAXSBZ128rr $xmm16, $xmm13470 $xmm16 = VPMAXSBZ128rr $xmm16, $xmm13471 ; CHECK: $xmm16 = VPMAXSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3472 $xmm16 = VPMAXSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3473 ; CHECK: $xmm16 = VPMAXSDZ128rr $xmm16, $xmm13474 $xmm16 = VPMAXSDZ128rr $xmm16, $xmm13475 ; CHECK: $xmm16 = VPMAXSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3476 $xmm16 = VPMAXSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3477 ; CHECK: $xmm16 = VPMAXSWZ128rr $xmm16, $xmm13478 $xmm16 = VPMAXSWZ128rr $xmm16, $xmm13479 ; CHECK: $xmm16 = VPMAXUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3480 $xmm16 = VPMAXUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3481 ; CHECK: $xmm16 = VPMAXUBZ128rr $xmm16, $xmm13482 $xmm16 = VPMAXUBZ128rr $xmm16, $xmm13483 ; CHECK: $xmm16 = VPMAXUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3484 $xmm16 = VPMAXUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3485 ; CHECK: $xmm16 = VPMAXUDZ128rr $xmm16, $xmm13486 $xmm16 = VPMAXUDZ128rr $xmm16, $xmm13487 ; CHECK: $xmm16 = VPMAXUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3488 $xmm16 = VPMAXUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3489 ; CHECK: $xmm16 = VPMAXUWZ128rr $xmm16, $xmm13490 $xmm16 = VPMAXUWZ128rr $xmm16, $xmm13491 ; CHECK: $xmm16 = VPMINSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3492 $xmm16 = VPMINSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3493 ; CHECK: $xmm16 = VPMINSBZ128rr $xmm16, $xmm13494 $xmm16 = VPMINSBZ128rr $xmm16, $xmm13495 ; CHECK: $xmm16 = VPMINSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3496 $xmm16 = VPMINSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3497 ; CHECK: $xmm16 = VPMINSDZ128rr $xmm16, $xmm13498 $xmm16 = VPMINSDZ128rr $xmm16, $xmm13499 ; CHECK: $xmm16 = VPMINSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3500 $xmm16 = VPMINSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3501 ; CHECK: $xmm16 = VPMINSWZ128rr $xmm16, $xmm13502 $xmm16 = VPMINSWZ128rr $xmm16, $xmm13503 ; CHECK: $xmm16 = VPMINUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3504 $xmm16 = VPMINUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3505 ; CHECK: $xmm16 = VPMINUBZ128rr $xmm16, $xmm13506 $xmm16 = VPMINUBZ128rr $xmm16, $xmm13507 ; CHECK: $xmm16 = VPMINUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3508 $xmm16 = VPMINUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3509 ; CHECK: $xmm16 = VPMINUDZ128rr $xmm16, $xmm13510 $xmm16 = VPMINUDZ128rr $xmm16, $xmm13511 ; CHECK: $xmm16 = VPMINUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3512 $xmm16 = VPMINUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3513 ; CHECK: $xmm16 = VPMINUWZ128rr $xmm16, $xmm13514 $xmm16 = VPMINUWZ128rr $xmm16, $xmm13515 ; CHECK: $xmm16 = VPMULDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3516 $xmm16 = VPMULDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3517 ; CHECK: $xmm16 = VPMULDQZ128rr $xmm16, $xmm13518 $xmm16 = VPMULDQZ128rr $xmm16, $xmm13519 ; CHECK: $xmm16 = VPMULHRSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3520 $xmm16 = VPMULHRSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3521 ; CHECK: $xmm16 = VPMULHRSWZ128rr $xmm16, $xmm13522 $xmm16 = VPMULHRSWZ128rr $xmm16, $xmm13523 ; CHECK: $xmm16 = VPMULHUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3524 $xmm16 = VPMULHUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3525 ; CHECK: $xmm16 = VPMULHUWZ128rr $xmm16, $xmm13526 $xmm16 = VPMULHUWZ128rr $xmm16, $xmm13527 ; CHECK: $xmm16 = VPMULHWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3528 $xmm16 = VPMULHWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3529 ; CHECK: $xmm16 = VPMULHWZ128rr $xmm16, $xmm13530 $xmm16 = VPMULHWZ128rr $xmm16, $xmm13531 ; CHECK: $xmm16 = VPMULLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3532 $xmm16 = VPMULLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3533 ; CHECK: $xmm16 = VPMULLDZ128rr $xmm16, $xmm13534 $xmm16 = VPMULLDZ128rr $xmm16, $xmm13535 ; CHECK: $xmm16 = VPMULLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3536 $xmm16 = VPMULLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3537 ; CHECK: $xmm16 = VPMULLWZ128rr $xmm16, $xmm13538 $xmm16 = VPMULLWZ128rr $xmm16, $xmm13539 ; CHECK: $xmm16 = VPMULUDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3540 $xmm16 = VPMULUDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3541 ; CHECK: $xmm16 = VPMULUDQZ128rr $xmm16, $xmm13542 $xmm16 = VPMULUDQZ128rr $xmm16, $xmm13543 ; CHECK: $xmm16 = VPORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3544 $xmm16 = VPORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3545 ; CHECK: $xmm16 = VPORDZ128rr $xmm16, $xmm13546 $xmm16 = VPORDZ128rr $xmm16, $xmm13547 ; CHECK: $xmm16 = VPORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3548 $xmm16 = VPORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3549 ; CHECK: $xmm16 = VPORQZ128rr $xmm16, $xmm13550 $xmm16 = VPORQZ128rr $xmm16, $xmm13551 ; CHECK: $xmm16 = VPSUBBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3552 $xmm16 = VPSUBBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3553 ; CHECK: $xmm16 = VPSUBBZ128rr $xmm16, $xmm13554 $xmm16 = VPSUBBZ128rr $xmm16, $xmm13555 ; CHECK: $xmm16 = VPSUBDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3556 $xmm16 = VPSUBDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3557 ; CHECK: $xmm16 = VPSUBDZ128rr $xmm16, $xmm13558 $xmm16 = VPSUBDZ128rr $xmm16, $xmm13559 ; CHECK: $xmm16 = VPSUBQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3560 $xmm16 = VPSUBQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3561 ; CHECK: $xmm16 = VPSUBQZ128rr $xmm16, $xmm13562 $xmm16 = VPSUBQZ128rr $xmm16, $xmm13563 ; CHECK: $xmm16 = VPSUBSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3564 $xmm16 = VPSUBSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3565 ; CHECK: $xmm16 = VPSUBSBZ128rr $xmm16, $xmm13566 $xmm16 = VPSUBSBZ128rr $xmm16, $xmm13567 ; CHECK: $xmm16 = VPSUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3568 $xmm16 = VPSUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3569 ; CHECK: $xmm16 = VPSUBSWZ128rr $xmm16, $xmm13570 $xmm16 = VPSUBSWZ128rr $xmm16, $xmm13571 ; CHECK: $xmm16 = VPSUBUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3572 $xmm16 = VPSUBUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3573 ; CHECK: $xmm16 = VPSUBUSBZ128rr $xmm16, $xmm13574 $xmm16 = VPSUBUSBZ128rr $xmm16, $xmm13575 ; CHECK: $xmm16 = VPSUBUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3576 $xmm16 = VPSUBUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3577 ; CHECK: $xmm16 = VPSUBUSWZ128rr $xmm16, $xmm13578 $xmm16 = VPSUBUSWZ128rr $xmm16, $xmm13579 ; CHECK: $xmm16 = VPSUBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3580 $xmm16 = VPSUBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3581 ; CHECK: $xmm16 = VPSUBWZ128rr $xmm16, $xmm13582 $xmm16 = VPSUBWZ128rr $xmm16, $xmm13583 ; CHECK: $xmm16 = VADDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3584 $xmm16 = VADDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3585 ; CHECK: $xmm16 = VADDPDZ128rr $xmm16, $xmm1, implicit $mxcsr3586 $xmm16 = VADDPDZ128rr $xmm16, $xmm1, implicit $mxcsr3587 ; CHECK: $xmm16 = VADDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3588 $xmm16 = VADDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3589 ; CHECK: $xmm16 = VADDPSZ128rr $xmm16, $xmm1, implicit $mxcsr3590 $xmm16 = VADDPSZ128rr $xmm16, $xmm1, implicit $mxcsr3591 ; CHECK: $xmm16 = VANDNPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3592 $xmm16 = VANDNPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3593 ; CHECK: $xmm16 = VANDNPDZ128rr $xmm16, $xmm13594 $xmm16 = VANDNPDZ128rr $xmm16, $xmm13595 ; CHECK: $xmm16 = VANDNPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3596 $xmm16 = VANDNPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3597 ; CHECK: $xmm16 = VANDNPSZ128rr $xmm16, $xmm13598 $xmm16 = VANDNPSZ128rr $xmm16, $xmm13599 ; CHECK: $xmm16 = VANDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3600 $xmm16 = VANDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3601 ; CHECK: $xmm16 = VANDPDZ128rr $xmm16, $xmm13602 $xmm16 = VANDPDZ128rr $xmm16, $xmm13603 ; CHECK: $xmm16 = VANDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3604 $xmm16 = VANDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3605 ; CHECK: $xmm16 = VANDPSZ128rr $xmm16, $xmm13606 $xmm16 = VANDPSZ128rr $xmm16, $xmm13607 ; CHECK: $xmm16 = VDIVPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3608 $xmm16 = VDIVPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3609 ; CHECK: $xmm16 = VDIVPDZ128rr $xmm16, $xmm1, implicit $mxcsr3610 $xmm16 = VDIVPDZ128rr $xmm16, $xmm1, implicit $mxcsr3611 ; CHECK: $xmm16 = VDIVPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3612 $xmm16 = VDIVPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3613 ; CHECK: $xmm16 = VDIVPSZ128rr $xmm16, $xmm1, implicit $mxcsr3614 $xmm16 = VDIVPSZ128rr $xmm16, $xmm1, implicit $mxcsr3615 ; CHECK: $xmm16 = VPXORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3616 $xmm16 = VPXORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3617 ; CHECK: $xmm16 = VPXORDZ128rr $xmm16, $xmm13618 $xmm16 = VPXORDZ128rr $xmm16, $xmm13619 ; CHECK: $xmm16 = VPXORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3620 $xmm16 = VPXORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3621 ; CHECK: $xmm16 = VPXORQZ128rr $xmm16, $xmm13622 $xmm16 = VPXORQZ128rr $xmm16, $xmm13623 ; CHECK: $xmm16 = VSUBPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3624 $xmm16 = VSUBPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3625 ; CHECK: $xmm16 = VSUBPDZ128rr $xmm16, $xmm1, implicit $mxcsr3626 $xmm16 = VSUBPDZ128rr $xmm16, $xmm1, implicit $mxcsr3627 ; CHECK: $xmm16 = VSUBPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3628 $xmm16 = VSUBPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr3629 ; CHECK: $xmm16 = VSUBPSZ128rr $xmm16, $xmm1, implicit $mxcsr3630 $xmm16 = VSUBPSZ128rr $xmm16, $xmm1, implicit $mxcsr3631 ; CHECK: $xmm16 = VXORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3632 $xmm16 = VXORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3633 ; CHECK: $xmm16 = VXORPDZ128rr $xmm16, $xmm13634 $xmm16 = VXORPDZ128rr $xmm16, $xmm13635 ; CHECK: $xmm16 = VXORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3636 $xmm16 = VXORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3637 ; CHECK: $xmm16 = VXORPSZ128rr $xmm16, $xmm13638 $xmm16 = VXORPSZ128rr $xmm16, $xmm13639 ; CHECK: $xmm16 = VPMADDUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3640 $xmm16 = VPMADDUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3641 ; CHECK: $xmm16 = VPMADDUBSWZ128rr $xmm16, $xmm13642 $xmm16 = VPMADDUBSWZ128rr $xmm16, $xmm13643 ; CHECK: $xmm16 = VPMADDWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3644 $xmm16 = VPMADDWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3645 ; CHECK: $xmm16 = VPMADDWDZ128rr $xmm16, $xmm13646 $xmm16 = VPMADDWDZ128rr $xmm16, $xmm13647 ; CHECK: $xmm16 = VPACKSSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3648 $xmm16 = VPACKSSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3649 ; CHECK: $xmm16 = VPACKSSDWZ128rr $xmm16, $xmm13650 $xmm16 = VPACKSSDWZ128rr $xmm16, $xmm13651 ; CHECK: $xmm16 = VPACKSSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3652 $xmm16 = VPACKSSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3653 ; CHECK: $xmm16 = VPACKSSWBZ128rr $xmm16, $xmm13654 $xmm16 = VPACKSSWBZ128rr $xmm16, $xmm13655 ; CHECK: $xmm16 = VPACKUSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3656 $xmm16 = VPACKUSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3657 ; CHECK: $xmm16 = VPACKUSDWZ128rr $xmm16, $xmm13658 $xmm16 = VPACKUSDWZ128rr $xmm16, $xmm13659 ; CHECK: $xmm16 = VPACKUSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3660 $xmm16 = VPACKUSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3661 ; CHECK: $xmm16 = VPACKUSWBZ128rr $xmm16, $xmm13662 $xmm16 = VPACKUSWBZ128rr $xmm16, $xmm13663 ; CHECK: $xmm16 = VPUNPCKHBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3664 $xmm16 = VPUNPCKHBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3665 ; CHECK: $xmm16 = VPUNPCKHBWZ128rr $xmm16, $xmm13666 $xmm16 = VPUNPCKHBWZ128rr $xmm16, $xmm13667 ; CHECK: $xmm16 = VPUNPCKHDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3668 $xmm16 = VPUNPCKHDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3669 ; CHECK: $xmm16 = VPUNPCKHDQZ128rr $xmm16, $xmm13670 $xmm16 = VPUNPCKHDQZ128rr $xmm16, $xmm13671 ; CHECK: $xmm16 = VPUNPCKHQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3672 $xmm16 = VPUNPCKHQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3673 ; CHECK: $xmm16 = VPUNPCKHQDQZ128rr $xmm16, $xmm13674 $xmm16 = VPUNPCKHQDQZ128rr $xmm16, $xmm13675 ; CHECK: $xmm16 = VPUNPCKHWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3676 $xmm16 = VPUNPCKHWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3677 ; CHECK: $xmm16 = VPUNPCKHWDZ128rr $xmm16, $xmm13678 $xmm16 = VPUNPCKHWDZ128rr $xmm16, $xmm13679 ; CHECK: $xmm16 = VPUNPCKLBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3680 $xmm16 = VPUNPCKLBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3681 ; CHECK: $xmm16 = VPUNPCKLBWZ128rr $xmm16, $xmm13682 $xmm16 = VPUNPCKLBWZ128rr $xmm16, $xmm13683 ; CHECK: $xmm16 = VPUNPCKLDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3684 $xmm16 = VPUNPCKLDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3685 ; CHECK: $xmm16 = VPUNPCKLDQZ128rr $xmm16, $xmm13686 $xmm16 = VPUNPCKLDQZ128rr $xmm16, $xmm13687 ; CHECK: $xmm16 = VPUNPCKLQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3688 $xmm16 = VPUNPCKLQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3689 ; CHECK: $xmm16 = VPUNPCKLQDQZ128rr $xmm16, $xmm13690 $xmm16 = VPUNPCKLQDQZ128rr $xmm16, $xmm13691 ; CHECK: $xmm16 = VPUNPCKLWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3692 $xmm16 = VPUNPCKLWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3693 ; CHECK: $xmm16 = VPUNPCKLWDZ128rr $xmm16, $xmm13694 $xmm16 = VPUNPCKLWDZ128rr $xmm16, $xmm13695 ; CHECK: $xmm16 = VUNPCKHPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3696 $xmm16 = VUNPCKHPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3697 ; CHECK: $xmm16 = VUNPCKHPDZ128rr $xmm16, $xmm13698 $xmm16 = VUNPCKHPDZ128rr $xmm16, $xmm13699 ; CHECK: $xmm16 = VUNPCKHPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3700 $xmm16 = VUNPCKHPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3701 ; CHECK: $xmm16 = VUNPCKHPSZ128rr $xmm16, $xmm13702 $xmm16 = VUNPCKHPSZ128rr $xmm16, $xmm13703 ; CHECK: $xmm16 = VUNPCKLPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3704 $xmm16 = VUNPCKLPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3705 ; CHECK: $xmm16 = VUNPCKLPDZ128rr $xmm16, $xmm13706 $xmm16 = VUNPCKLPDZ128rr $xmm16, $xmm13707 ; CHECK: $xmm16 = VUNPCKLPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3708 $xmm16 = VUNPCKLPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3709 ; CHECK: $xmm16 = VUNPCKLPSZ128rr $xmm16, $xmm13710 $xmm16 = VUNPCKLPSZ128rr $xmm16, $xmm13711 ; CHECK: $xmm16 = VFMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3712 $xmm16 = VFMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3713 ; CHECK: $xmm16 = VFMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3714 $xmm16 = VFMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3715 ; CHECK: $xmm16 = VFMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3716 $xmm16 = VFMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3717 ; CHECK: $xmm16 = VFMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3718 $xmm16 = VFMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3719 ; CHECK: $xmm16 = VFMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3720 $xmm16 = VFMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3721 ; CHECK: $xmm16 = VFMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3722 $xmm16 = VFMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3723 ; CHECK: $xmm16 = VFMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3724 $xmm16 = VFMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3725 ; CHECK: $xmm16 = VFMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3726 $xmm16 = VFMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3727 ; CHECK: $xmm16 = VFMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3728 $xmm16 = VFMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3729 ; CHECK: $xmm16 = VFMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3730 $xmm16 = VFMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3731 ; CHECK: $xmm16 = VFMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3732 $xmm16 = VFMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3733 ; CHECK: $xmm16 = VFMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3734 $xmm16 = VFMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3735 ; CHECK: $xmm16 = VFMADDSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3736 $xmm16 = VFMADDSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3737 ; CHECK: $xmm16 = VFMADDSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3738 $xmm16 = VFMADDSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3739 ; CHECK: $xmm16 = VFMADDSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3740 $xmm16 = VFMADDSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3741 ; CHECK: $xmm16 = VFMADDSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3742 $xmm16 = VFMADDSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3743 ; CHECK: $xmm16 = VFMADDSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3744 $xmm16 = VFMADDSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3745 ; CHECK: $xmm16 = VFMADDSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3746 $xmm16 = VFMADDSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3747 ; CHECK: $xmm16 = VFMADDSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3748 $xmm16 = VFMADDSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3749 ; CHECK: $xmm16 = VFMADDSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3750 $xmm16 = VFMADDSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3751 ; CHECK: $xmm16 = VFMADDSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3752 $xmm16 = VFMADDSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3753 ; CHECK: $xmm16 = VFMADDSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3754 $xmm16 = VFMADDSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3755 ; CHECK: $xmm16 = VFMADDSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3756 $xmm16 = VFMADDSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3757 ; CHECK: $xmm16 = VFMADDSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3758 $xmm16 = VFMADDSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3759 ; CHECK: $xmm16 = VFMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3760 $xmm16 = VFMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3761 ; CHECK: $xmm16 = VFMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3762 $xmm16 = VFMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3763 ; CHECK: $xmm16 = VFMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3764 $xmm16 = VFMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3765 ; CHECK: $xmm16 = VFMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3766 $xmm16 = VFMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3767 ; CHECK: $xmm16 = VFMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3768 $xmm16 = VFMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3769 ; CHECK: $xmm16 = VFMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3770 $xmm16 = VFMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3771 ; CHECK: $xmm16 = VFMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3772 $xmm16 = VFMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3773 ; CHECK: $xmm16 = VFMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3774 $xmm16 = VFMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3775 ; CHECK: $xmm16 = VFMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3776 $xmm16 = VFMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3777 ; CHECK: $xmm16 = VFMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3778 $xmm16 = VFMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3779 ; CHECK: $xmm16 = VFMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3780 $xmm16 = VFMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3781 ; CHECK: $xmm16 = VFMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3782 $xmm16 = VFMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3783 ; CHECK: $xmm16 = VFMSUBADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3784 $xmm16 = VFMSUBADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3785 ; CHECK: $xmm16 = VFMSUBADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3786 $xmm16 = VFMSUBADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3787 ; CHECK: $xmm16 = VFMSUBADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3788 $xmm16 = VFMSUBADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3789 ; CHECK: $xmm16 = VFMSUBADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3790 $xmm16 = VFMSUBADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3791 ; CHECK: $xmm16 = VFMSUBADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3792 $xmm16 = VFMSUBADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3793 ; CHECK: $xmm16 = VFMSUBADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3794 $xmm16 = VFMSUBADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3795 ; CHECK: $xmm16 = VFMSUBADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3796 $xmm16 = VFMSUBADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3797 ; CHECK: $xmm16 = VFMSUBADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3798 $xmm16 = VFMSUBADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3799 ; CHECK: $xmm16 = VFMSUBADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3800 $xmm16 = VFMSUBADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3801 ; CHECK: $xmm16 = VFMSUBADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3802 $xmm16 = VFMSUBADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3803 ; CHECK: $xmm16 = VFMSUBADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3804 $xmm16 = VFMSUBADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3805 ; CHECK: $xmm16 = VFMSUBADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3806 $xmm16 = VFMSUBADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3807 ; CHECK: $xmm16 = VFNMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3808 $xmm16 = VFNMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3809 ; CHECK: $xmm16 = VFNMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3810 $xmm16 = VFNMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3811 ; CHECK: $xmm16 = VFNMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3812 $xmm16 = VFNMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3813 ; CHECK: $xmm16 = VFNMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3814 $xmm16 = VFNMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3815 ; CHECK: $xmm16 = VFNMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3816 $xmm16 = VFNMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3817 ; CHECK: $xmm16 = VFNMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3818 $xmm16 = VFNMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3819 ; CHECK: $xmm16 = VFNMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3820 $xmm16 = VFNMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3821 ; CHECK: $xmm16 = VFNMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3822 $xmm16 = VFNMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3823 ; CHECK: $xmm16 = VFNMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3824 $xmm16 = VFNMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3825 ; CHECK: $xmm16 = VFNMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3826 $xmm16 = VFNMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3827 ; CHECK: $xmm16 = VFNMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3828 $xmm16 = VFNMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3829 ; CHECK: $xmm16 = VFNMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3830 $xmm16 = VFNMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3831 ; CHECK: $xmm16 = VFNMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3832 $xmm16 = VFNMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3833 ; CHECK: $xmm16 = VFNMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3834 $xmm16 = VFNMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3835 ; CHECK: $xmm16 = VFNMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3836 $xmm16 = VFNMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3837 ; CHECK: $xmm16 = VFNMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3838 $xmm16 = VFNMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3839 ; CHECK: $xmm16 = VFNMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3840 $xmm16 = VFNMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3841 ; CHECK: $xmm16 = VFNMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3842 $xmm16 = VFNMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3843 ; CHECK: $xmm16 = VFNMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3844 $xmm16 = VFNMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3845 ; CHECK: $xmm16 = VFNMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3846 $xmm16 = VFNMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3847 ; CHECK: $xmm16 = VFNMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3848 $xmm16 = VFNMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3849 ; CHECK: $xmm16 = VFNMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3850 $xmm16 = VFNMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3851 ; CHECK: $xmm16 = VFNMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3852 $xmm16 = VFNMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr3853 ; CHECK: $xmm16 = VFNMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3854 $xmm16 = VFNMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr3855 ; CHECK: $xmm16 = VPSLLDZ128ri $xmm16, 73856 $xmm16 = VPSLLDZ128ri $xmm16, 73857 ; CHECK: $xmm16 = VPSLLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3858 $xmm16 = VPSLLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3859 ; CHECK: $xmm16 = VPSLLDZ128rr $xmm16, $xmm163860 $xmm16 = VPSLLDZ128rr $xmm16, $xmm163861 ; CHECK: $xmm16 = VPSLLQZ128ri $xmm16, 73862 $xmm16 = VPSLLQZ128ri $xmm16, 73863 ; CHECK: $xmm16 = VPSLLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3864 $xmm16 = VPSLLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3865 ; CHECK: $xmm16 = VPSLLQZ128rr $xmm16, $xmm163866 $xmm16 = VPSLLQZ128rr $xmm16, $xmm163867 ; CHECK: $xmm16 = VPSLLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3868 $xmm16 = VPSLLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3869 ; CHECK: $xmm16 = VPSLLVDZ128rr $xmm16, $xmm163870 $xmm16 = VPSLLVDZ128rr $xmm16, $xmm163871 ; CHECK: $xmm16 = VPSLLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3872 $xmm16 = VPSLLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3873 ; CHECK: $xmm16 = VPSLLVQZ128rr $xmm16, $xmm163874 $xmm16 = VPSLLVQZ128rr $xmm16, $xmm163875 ; CHECK: $xmm16 = VPSLLWZ128ri $xmm16, 73876 $xmm16 = VPSLLWZ128ri $xmm16, 73877 ; CHECK: $xmm16 = VPSLLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3878 $xmm16 = VPSLLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3879 ; CHECK: $xmm16 = VPSLLWZ128rr $xmm16, $xmm163880 $xmm16 = VPSLLWZ128rr $xmm16, $xmm163881 ; CHECK: $xmm16 = VPSRADZ128ri $xmm16, 73882 $xmm16 = VPSRADZ128ri $xmm16, 73883 ; CHECK: $xmm16 = VPSRADZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3884 $xmm16 = VPSRADZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3885 ; CHECK: $xmm16 = VPSRADZ128rr $xmm16, $xmm163886 $xmm16 = VPSRADZ128rr $xmm16, $xmm163887 ; CHECK: $xmm16 = VPSRAVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3888 $xmm16 = VPSRAVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3889 ; CHECK: $xmm16 = VPSRAVDZ128rr $xmm16, $xmm163890 $xmm16 = VPSRAVDZ128rr $xmm16, $xmm163891 ; CHECK: $xmm16 = VPSRAWZ128ri $xmm16, 73892 $xmm16 = VPSRAWZ128ri $xmm16, 73893 ; CHECK: $xmm16 = VPSRAWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3894 $xmm16 = VPSRAWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3895 ; CHECK: $xmm16 = VPSRAWZ128rr $xmm16, $xmm163896 $xmm16 = VPSRAWZ128rr $xmm16, $xmm163897 ; CHECK: $xmm16 = VPSRLDQZ128ri $xmm16, 143898 $xmm16 = VPSRLDQZ128ri $xmm16, 143899 ; CHECK: $xmm16 = VPSRLDZ128ri $xmm16, 73900 $xmm16 = VPSRLDZ128ri $xmm16, 73901 ; CHECK: $xmm16 = VPSRLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3902 $xmm16 = VPSRLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3903 ; CHECK: $xmm16 = VPSRLDZ128rr $xmm16, $xmm163904 $xmm16 = VPSRLDZ128rr $xmm16, $xmm163905 ; CHECK: $xmm16 = VPSRLQZ128ri $xmm16, 73906 $xmm16 = VPSRLQZ128ri $xmm16, 73907 ; CHECK: $xmm16 = VPSRLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3908 $xmm16 = VPSRLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3909 ; CHECK: $xmm16 = VPSRLQZ128rr $xmm16, $xmm163910 $xmm16 = VPSRLQZ128rr $xmm16, $xmm163911 ; CHECK: $xmm16 = VPSRLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3912 $xmm16 = VPSRLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3913 ; CHECK: $xmm16 = VPSRLVDZ128rr $xmm16, $xmm163914 $xmm16 = VPSRLVDZ128rr $xmm16, $xmm163915 ; CHECK: $xmm16 = VPSRLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3916 $xmm16 = VPSRLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3917 ; CHECK: $xmm16 = VPSRLVQZ128rr $xmm16, $xmm163918 $xmm16 = VPSRLVQZ128rr $xmm16, $xmm163919 ; CHECK: $xmm16 = VPSRLWZ128ri $xmm16, 73920 $xmm16 = VPSRLWZ128ri $xmm16, 73921 ; CHECK: $xmm16 = VPSRLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3922 $xmm16 = VPSRLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg3923 ; CHECK: $xmm16 = VPSRLWZ128rr $xmm16, $xmm163924 $xmm16 = VPSRLWZ128rr $xmm16, $xmm163925 ; CHECK: $xmm16 = VPERMILPDZ128mi $rdi, 1, $noreg, 0, $noreg, 93926 $xmm16 = VPERMILPDZ128mi $rdi, 1, $noreg, 0, $noreg, 93927 ; CHECK: $xmm16 = VPERMILPDZ128ri $xmm16, 93928 $xmm16 = VPERMILPDZ128ri $xmm16, 93929 ; CHECK: $xmm16 = VPERMILPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3930 $xmm16 = VPERMILPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3931 ; CHECK: $xmm16 = VPERMILPDZ128rr $xmm16, $xmm13932 $xmm16 = VPERMILPDZ128rr $xmm16, $xmm13933 ; CHECK: $xmm16 = VPERMILPSZ128mi $rdi, 1, $noreg, 0, $noreg, 93934 $xmm16 = VPERMILPSZ128mi $rdi, 1, $noreg, 0, $noreg, 93935 ; CHECK: $xmm16 = VPERMILPSZ128ri $xmm16, 93936 $xmm16 = VPERMILPSZ128ri $xmm16, 93937 ; CHECK: $xmm16 = VPERMILPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3938 $xmm16 = VPERMILPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3939 ; CHECK: $xmm16 = VPERMILPSZ128rr $xmm16, $xmm13940 $xmm16 = VPERMILPSZ128rr $xmm16, $xmm13941 ; CHECK: $xmm16 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3942 $xmm16 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3943 ; CHECK: $xmm16 = VCVTPH2PSZ128rr $xmm16, implicit $mxcsr3944 $xmm16 = VCVTPH2PSZ128rr $xmm16, implicit $mxcsr3945 ; CHECK: $xmm16 = VCVTDQ2PDZ128rm $rdi, 1, $noreg, 0, $noreg3946 $xmm16 = VCVTDQ2PDZ128rm $rdi, 1, $noreg, 0, $noreg3947 ; CHECK: $xmm16 = VCVTDQ2PDZ128rr $xmm163948 $xmm16 = VCVTDQ2PDZ128rr $xmm163949 ; CHECK: $xmm16 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3950 $xmm16 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3951 ; CHECK: $xmm16 = VCVTDQ2PSZ128rr $xmm16, implicit $mxcsr3952 $xmm16 = VCVTDQ2PSZ128rr $xmm16, implicit $mxcsr3953 ; CHECK: $xmm16 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3954 $xmm16 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3955 ; CHECK: $xmm16 = VCVTPD2DQZ128rr $xmm16, implicit $mxcsr3956 $xmm16 = VCVTPD2DQZ128rr $xmm16, implicit $mxcsr3957 ; CHECK: $xmm16 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3958 $xmm16 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3959 ; CHECK: $xmm16 = VCVTPD2PSZ128rr $xmm16, implicit $mxcsr3960 $xmm16 = VCVTPD2PSZ128rr $xmm16, implicit $mxcsr3961 ; CHECK: $xmm16 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3962 $xmm16 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3963 ; CHECK: $xmm16 = VCVTPS2DQZ128rr $xmm16, implicit $mxcsr3964 $xmm16 = VCVTPS2DQZ128rr $xmm16, implicit $mxcsr3965 ; CHECK: $xmm16 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3966 $xmm16 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3967 ; CHECK: $xmm16 = VCVTPS2PDZ128rr $xmm16, implicit $mxcsr3968 $xmm16 = VCVTPS2PDZ128rr $xmm16, implicit $mxcsr3969 ; CHECK: $xmm16 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3970 $xmm16 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3971 ; CHECK: $xmm16 = VCVTTPD2DQZ128rr $xmm16, implicit $mxcsr3972 $xmm16 = VCVTTPD2DQZ128rr $xmm16, implicit $mxcsr3973 ; CHECK: $xmm16 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3974 $xmm16 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3975 ; CHECK: $xmm16 = VCVTTPS2DQZ128rr $xmm16, implicit $mxcsr3976 $xmm16 = VCVTTPS2DQZ128rr $xmm16, implicit $mxcsr3977 ; CHECK: $xmm16 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3978 $xmm16 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3979 ; CHECK: $xmm16 = VSQRTPDZ128r $xmm16, implicit $mxcsr3980 $xmm16 = VSQRTPDZ128r $xmm16, implicit $mxcsr3981 ; CHECK: $xmm16 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3982 $xmm16 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr3983 ; CHECK: $xmm16 = VSQRTPSZ128r $xmm16, implicit $mxcsr3984 $xmm16 = VSQRTPSZ128r $xmm16, implicit $mxcsr3985 ; CHECK: $xmm16 = VMOVDDUPZ128rm $rdi, 1, $noreg, 0, $noreg3986 $xmm16 = VMOVDDUPZ128rm $rdi, 1, $noreg, 0, $noreg3987 ; CHECK: $xmm16 = VMOVDDUPZ128rr $xmm163988 $xmm16 = VMOVDDUPZ128rr $xmm163989 ; CHECK: $xmm16 = VMOVSHDUPZ128rm $rdi, 1, $noreg, 0, $noreg3990 $xmm16 = VMOVSHDUPZ128rm $rdi, 1, $noreg, 0, $noreg3991 ; CHECK: $xmm16 = VMOVSHDUPZ128rr $xmm163992 $xmm16 = VMOVSHDUPZ128rr $xmm163993 ; CHECK: $xmm16 = VMOVSLDUPZ128rm $rdi, 1, $noreg, 0, $noreg3994 $xmm16 = VMOVSLDUPZ128rm $rdi, 1, $noreg, 0, $noreg3995 ; CHECK: $xmm16 = VMOVSLDUPZ128rr $xmm163996 $xmm16 = VMOVSLDUPZ128rr $xmm163997 ; CHECK: $xmm16 = VPSHUFBZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3998 $xmm16 = VPSHUFBZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg3999 ; CHECK: $xmm16 = VPSHUFBZ128rr $xmm16, $xmm14000 $xmm16 = VPSHUFBZ128rr $xmm16, $xmm14001 ; CHECK: $xmm16 = VPSHUFDZ128mi $rdi, 1, $noreg, 0, $noreg, -244002 $xmm16 = VPSHUFDZ128mi $rdi, 1, $noreg, 0, $noreg, -244003 ; CHECK: $xmm16 = VPSHUFDZ128ri $xmm16, -244004 $xmm16 = VPSHUFDZ128ri $xmm16, -244005 ; CHECK: $xmm16 = VPSHUFHWZ128mi $rdi, 1, $noreg, 0, $noreg, -244006 $xmm16 = VPSHUFHWZ128mi $rdi, 1, $noreg, 0, $noreg, -244007 ; CHECK: $xmm16 = VPSHUFHWZ128ri $xmm16, -244008 $xmm16 = VPSHUFHWZ128ri $xmm16, -244009 ; CHECK: $xmm16 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -244010 $xmm16 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -244011 ; CHECK: $xmm16 = VPSHUFLWZ128ri $xmm16, -244012 $xmm16 = VPSHUFLWZ128ri $xmm16, -244013 ; CHECK: $xmm16 = VPSLLDQZ128ri $xmm16, 14014 $xmm16 = VPSLLDQZ128ri $xmm16, 14015 ; CHECK: $xmm16 = VSHUFPDZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -244016 $xmm16 = VSHUFPDZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -244017 ; CHECK: $xmm16 = VSHUFPDZ128rri $xmm16, $xmm1, -244018 $xmm16 = VSHUFPDZ128rri $xmm16, $xmm1, -244019 ; CHECK: $xmm16 = VSHUFPSZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -244020 $xmm16 = VSHUFPSZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -244021 ; CHECK: $xmm16 = VSHUFPSZ128rri $xmm16, $xmm1, -244022 $xmm16 = VSHUFPSZ128rri $xmm16, $xmm1, -244023 ; CHECK: $xmm16 = VPSADBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg4024 $xmm16 = VPSADBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg4025 ; CHECK: $xmm16 = VPSADBWZ128rr $xmm16, $xmm14026 $xmm16 = VPSADBWZ128rr $xmm16, $xmm14027 ; CHECK: $xmm16 = VBROADCASTSSZ128rm $rip, 1, $noreg, 0, $noreg4028 $xmm16 = VBROADCASTSSZ128rm $rip, 1, $noreg, 0, $noreg4029 ; CHECK: $xmm16 = VBROADCASTSSZ128rr $xmm164030 $xmm16 = VBROADCASTSSZ128rr $xmm164031 ; CHECK: $xmm16 = VPBROADCASTBZ128rm $rip, 1, $noreg, 0, $noreg4032 $xmm16 = VPBROADCASTBZ128rm $rip, 1, $noreg, 0, $noreg4033 ; CHECK: $xmm16 = VPBROADCASTBZ128rr $xmm164034 $xmm16 = VPBROADCASTBZ128rr $xmm164035 ; CHECK: $xmm16 = VPBROADCASTDZ128rm $rip, 1, $noreg, 0, $noreg4036 $xmm16 = VPBROADCASTDZ128rm $rip, 1, $noreg, 0, $noreg4037 ; CHECK: $xmm16 = VPBROADCASTDZ128rr $xmm164038 $xmm16 = VPBROADCASTDZ128rr $xmm164039 ; CHECK: $xmm16 = VPBROADCASTQZ128rm $rip, 1, $noreg, 0, $noreg4040 $xmm16 = VPBROADCASTQZ128rm $rip, 1, $noreg, 0, $noreg4041 ; CHECK: $xmm16 = VPBROADCASTQZ128rr $xmm164042 $xmm16 = VPBROADCASTQZ128rr $xmm164043 ; CHECK: $xmm16 = VPBROADCASTWZ128rm $rip, 1, $noreg, 0, $noreg4044 $xmm16 = VPBROADCASTWZ128rm $rip, 1, $noreg, 0, $noreg4045 ; CHECK: $xmm16 = VPBROADCASTWZ128rr $xmm164046 $xmm16 = VPBROADCASTWZ128rr $xmm164047 ; CHECK: $xmm16 = VBROADCASTI32X2Z128rm $rip, 1, $noreg, 0, $noreg4048 $xmm16 = VBROADCASTI32X2Z128rm $rip, 1, $noreg, 0, $noreg4049 ; CHECK: $xmm16 = VBROADCASTI32X2Z128rr $xmm04050 $xmm16 = VBROADCASTI32X2Z128rr $xmm04051 ; CHECK: $xmm16 = VCVTPS2PHZ128rr $xmm16, 2, implicit $mxcsr4052 $xmm16 = VCVTPS2PHZ128rr $xmm16, 2, implicit $mxcsr4053 ; CHECK: VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16, 2, implicit $mxcsr4054 VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16, 2, implicit $mxcsr4055 ; CHECK: $xmm16 = VPABSBZ128rm $rip, 1, $noreg, 0, $noreg4056 $xmm16 = VPABSBZ128rm $rip, 1, $noreg, 0, $noreg4057 ; CHECK: $xmm16 = VPABSBZ128rr $xmm164058 $xmm16 = VPABSBZ128rr $xmm164059 ; CHECK: $xmm16 = VPABSDZ128rm $rip, 1, $noreg, 0, $noreg4060 $xmm16 = VPABSDZ128rm $rip, 1, $noreg, 0, $noreg4061 ; CHECK: $xmm16 = VPABSDZ128rr $xmm164062 $xmm16 = VPABSDZ128rr $xmm164063 ; CHECK: $xmm16 = VPABSWZ128rm $rip, 1, $noreg, 0, $noreg4064 $xmm16 = VPABSWZ128rm $rip, 1, $noreg, 0, $noreg4065 ; CHECK: $xmm16 = VPABSWZ128rr $xmm164066 $xmm16 = VPABSWZ128rr $xmm164067 ; CHECK: $xmm16 = VPALIGNRZ128rmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 154068 $xmm16 = VPALIGNRZ128rmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 154069 ; CHECK: $xmm16 = VPALIGNRZ128rri $xmm16, $xmm1, 154070 $xmm16 = VPALIGNRZ128rri $xmm16, $xmm1, 154071 ; CHECK: VEXTRACTPSZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 14072 VEXTRACTPSZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 14073 ; CHECK: $eax = VEXTRACTPSZrri $xmm16, 14074 $eax = VEXTRACTPSZrri $xmm16, 14075 ; CHECK: $xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 14076 $xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 14077 ; CHECK: $xmm16 = VINSERTPSZrri $xmm16, $xmm16, 14078 $xmm16 = VINSERTPSZrri $xmm16, $xmm16, 14079 ; CHECK: $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4080 $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4081 ; CHECK: $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr4082 $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr4083 ; CHECK: $xmm16 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4084 $xmm16 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4085 ; CHECK: $xmm16 = VRNDSCALEPSZ128rri $xmm16, 15, implicit $mxcsr4086 $xmm16 = VRNDSCALEPSZ128rri $xmm16, 15, implicit $mxcsr4087 ; CHECK: $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4088 $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4089 ; CHECK: $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr4090 $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr4091 ; CHECK: $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4092 $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4093 ; CHECK: $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr4094 $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr4095 4096 RET644097...4098---4099 # CHECK-LABEL: name: evex_scalar_to_evex_test4100 # CHECK: bb.0:4101 4102name: evex_scalar_to_evex_test4103body: |4104 bb.0:4105 ; CHECK: $xmm16 = VADDSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4106 $xmm16 = VADDSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4107 ; CHECK: $xmm16 = VADDSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4108 $xmm16 = VADDSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4109 ; CHECK: $xmm16 = VADDSDZrr $xmm16, $xmm1, implicit $mxcsr4110 $xmm16 = VADDSDZrr $xmm16, $xmm1, implicit $mxcsr4111 ; CHECK: $xmm16 = VADDSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4112 $xmm16 = VADDSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4113 ; CHECK: $xmm16 = VADDSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4114 $xmm16 = VADDSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4115 ; CHECK: $xmm16 = VADDSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4116 $xmm16 = VADDSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4117 ; CHECK: $xmm16 = VADDSSZrr $xmm16, $xmm1, implicit $mxcsr4118 $xmm16 = VADDSSZrr $xmm16, $xmm1, implicit $mxcsr4119 ; CHECK: $xmm16 = VADDSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4120 $xmm16 = VADDSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4121 ; CHECK: $xmm16 = VDIVSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4122 $xmm16 = VDIVSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4123 ; CHECK: $xmm16 = VDIVSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4124 $xmm16 = VDIVSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4125 ; CHECK: $xmm16 = VDIVSDZrr $xmm16, $xmm1, implicit $mxcsr4126 $xmm16 = VDIVSDZrr $xmm16, $xmm1, implicit $mxcsr4127 ; CHECK: $xmm16 = VDIVSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4128 $xmm16 = VDIVSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4129 ; CHECK: $xmm16 = VDIVSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4130 $xmm16 = VDIVSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4131 ; CHECK: $xmm16 = VDIVSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4132 $xmm16 = VDIVSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4133 ; CHECK: $xmm16 = VDIVSSZrr $xmm16, $xmm1, implicit $mxcsr4134 $xmm16 = VDIVSSZrr $xmm16, $xmm1, implicit $mxcsr4135 ; CHECK: $xmm16 = VDIVSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4136 $xmm16 = VDIVSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4137 ; CHECK: $xmm16 = VMAXCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4138 $xmm16 = VMAXCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4139 ; CHECK: $xmm16 = VMAXCSDZrr $xmm16, $xmm1, implicit $mxcsr4140 $xmm16 = VMAXCSDZrr $xmm16, $xmm1, implicit $mxcsr4141 ; CHECK: $xmm16 = VMAXCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4142 $xmm16 = VMAXCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4143 ; CHECK: $xmm16 = VMAXCSSZrr $xmm16, $xmm1, implicit $mxcsr4144 $xmm16 = VMAXCSSZrr $xmm16, $xmm1, implicit $mxcsr4145 ; CHECK: $xmm16 = VMAXSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4146 $xmm16 = VMAXSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4147 ; CHECK: $xmm16 = VMAXSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4148 $xmm16 = VMAXSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4149 ; CHECK: $xmm16 = VMAXSDZrr $xmm16, $xmm1, implicit $mxcsr4150 $xmm16 = VMAXSDZrr $xmm16, $xmm1, implicit $mxcsr4151 ; CHECK: $xmm16 = VMAXSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4152 $xmm16 = VMAXSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4153 ; CHECK: $xmm16 = VMAXSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4154 $xmm16 = VMAXSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4155 ; CHECK: $xmm16 = VMAXSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4156 $xmm16 = VMAXSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4157 ; CHECK: $xmm16 = VMAXSSZrr $xmm16, $xmm1, implicit $mxcsr4158 $xmm16 = VMAXSSZrr $xmm16, $xmm1, implicit $mxcsr4159 ; CHECK: $xmm16 = VMAXSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4160 $xmm16 = VMAXSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4161 ; CHECK: $xmm16 = VMINCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4162 $xmm16 = VMINCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4163 ; CHECK: $xmm16 = VMINCSDZrr $xmm16, $xmm1, implicit $mxcsr4164 $xmm16 = VMINCSDZrr $xmm16, $xmm1, implicit $mxcsr4165 ; CHECK: $xmm16 = VMINCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4166 $xmm16 = VMINCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4167 ; CHECK: $xmm16 = VMINCSSZrr $xmm16, $xmm1, implicit $mxcsr4168 $xmm16 = VMINCSSZrr $xmm16, $xmm1, implicit $mxcsr4169 ; CHECK: $xmm16 = VMINSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4170 $xmm16 = VMINSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4171 ; CHECK: $xmm16 = VMINSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4172 $xmm16 = VMINSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4173 ; CHECK: $xmm16 = VMINSDZrr $xmm16, $xmm1, implicit $mxcsr4174 $xmm16 = VMINSDZrr $xmm16, $xmm1, implicit $mxcsr4175 ; CHECK: $xmm16 = VMINSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4176 $xmm16 = VMINSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4177 ; CHECK: $xmm16 = VMINSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4178 $xmm16 = VMINSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4179 ; CHECK: $xmm16 = VMINSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4180 $xmm16 = VMINSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4181 ; CHECK: $xmm16 = VMINSSZrr $xmm16, $xmm1, implicit $mxcsr4182 $xmm16 = VMINSSZrr $xmm16, $xmm1, implicit $mxcsr4183 ; CHECK: $xmm16 = VMINSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4184 $xmm16 = VMINSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4185 ; CHECK: $xmm16 = VMULSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4186 $xmm16 = VMULSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4187 ; CHECK: $xmm16 = VMULSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4188 $xmm16 = VMULSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4189 ; CHECK: $xmm16 = VMULSDZrr $xmm16, $xmm1, implicit $mxcsr4190 $xmm16 = VMULSDZrr $xmm16, $xmm1, implicit $mxcsr4191 ; CHECK: $xmm16 = VMULSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4192 $xmm16 = VMULSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4193 ; CHECK: $xmm16 = VMULSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4194 $xmm16 = VMULSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4195 ; CHECK: $xmm16 = VMULSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4196 $xmm16 = VMULSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4197 ; CHECK: $xmm16 = VMULSSZrr $xmm16, $xmm1, implicit $mxcsr4198 $xmm16 = VMULSSZrr $xmm16, $xmm1, implicit $mxcsr4199 ; CHECK: $xmm16 = VMULSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4200 $xmm16 = VMULSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4201 ; CHECK: $xmm16 = VSUBSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4202 $xmm16 = VSUBSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4203 ; CHECK: $xmm16 = VSUBSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4204 $xmm16 = VSUBSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4205 ; CHECK: $xmm16 = VSUBSDZrr $xmm16, $xmm1, implicit $mxcsr4206 $xmm16 = VSUBSDZrr $xmm16, $xmm1, implicit $mxcsr4207 ; CHECK: $xmm16 = VSUBSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4208 $xmm16 = VSUBSDZrr_Int $xmm16, $xmm1, implicit $mxcsr4209 ; CHECK: $xmm16 = VSUBSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4210 $xmm16 = VSUBSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4211 ; CHECK: $xmm16 = VSUBSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4212 $xmm16 = VSUBSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr4213 ; CHECK: $xmm16 = VSUBSSZrr $xmm16, $xmm1, implicit $mxcsr4214 $xmm16 = VSUBSSZrr $xmm16, $xmm1, implicit $mxcsr4215 ; CHECK: $xmm16 = VSUBSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4216 $xmm16 = VSUBSSZrr_Int $xmm16, $xmm1, implicit $mxcsr4217 ; CHECK: $xmm16 = VFMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4218 $xmm16 = VFMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4219 ; CHECK: $xmm16 = VFMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4220 $xmm16 = VFMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4221 ; CHECK: $xmm16 = VFMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4222 $xmm16 = VFMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4223 ; CHECK: $xmm16 = VFMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4224 $xmm16 = VFMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4225 ; CHECK: $xmm16 = VFMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4226 $xmm16 = VFMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4227 ; CHECK: $xmm16 = VFMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4228 $xmm16 = VFMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4229 ; CHECK: $xmm16 = VFMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4230 $xmm16 = VFMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4231 ; CHECK: $xmm16 = VFMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4232 $xmm16 = VFMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4233 ; CHECK: $xmm16 = VFMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4234 $xmm16 = VFMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4235 ; CHECK: $xmm16 = VFMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4236 $xmm16 = VFMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4237 ; CHECK: $xmm16 = VFMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4238 $xmm16 = VFMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4239 ; CHECK: $xmm16 = VFMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4240 $xmm16 = VFMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4241 ; CHECK: $xmm16 = VFMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4242 $xmm16 = VFMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4243 ; CHECK: $xmm16 = VFMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4244 $xmm16 = VFMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4245 ; CHECK: $xmm16 = VFMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4246 $xmm16 = VFMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4247 ; CHECK: $xmm16 = VFMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4248 $xmm16 = VFMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4249 ; CHECK: $xmm16 = VFMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4250 $xmm16 = VFMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4251 ; CHECK: $xmm16 = VFMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4252 $xmm16 = VFMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4253 ; CHECK: $xmm16 = VFMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4254 $xmm16 = VFMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4255 ; CHECK: $xmm16 = VFMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4256 $xmm16 = VFMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4257 ; CHECK: $xmm16 = VFMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4258 $xmm16 = VFMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4259 ; CHECK: $xmm16 = VFMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4260 $xmm16 = VFMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4261 ; CHECK: $xmm16 = VFMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4262 $xmm16 = VFMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4263 ; CHECK: $xmm16 = VFMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4264 $xmm16 = VFMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4265 ; CHECK: $xmm16 = VFMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4266 $xmm16 = VFMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4267 ; CHECK: $xmm16 = VFMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4268 $xmm16 = VFMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4269 ; CHECK: $xmm16 = VFMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4270 $xmm16 = VFMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4271 ; CHECK: $xmm16 = VFMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4272 $xmm16 = VFMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4273 ; CHECK: $xmm16 = VFMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4274 $xmm16 = VFMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4275 ; CHECK: $xmm16 = VFMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4276 $xmm16 = VFMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4277 ; CHECK: $xmm16 = VFMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4278 $xmm16 = VFMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4279 ; CHECK: $xmm16 = VFMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4280 $xmm16 = VFMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4281 ; CHECK: $xmm16 = VFMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4282 $xmm16 = VFMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4283 ; CHECK: $xmm16 = VFMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4284 $xmm16 = VFMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4285 ; CHECK: $xmm16 = VFMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4286 $xmm16 = VFMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4287 ; CHECK: $xmm16 = VFMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4288 $xmm16 = VFMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4289 ; CHECK: $xmm16 = VFMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4290 $xmm16 = VFMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4291 ; CHECK: $xmm16 = VFMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4292 $xmm16 = VFMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4293 ; CHECK: $xmm16 = VFMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4294 $xmm16 = VFMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4295 ; CHECK: $xmm16 = VFMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4296 $xmm16 = VFMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4297 ; CHECK: $xmm16 = VFMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4298 $xmm16 = VFMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4299 ; CHECK: $xmm16 = VFMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4300 $xmm16 = VFMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4301 ; CHECK: $xmm16 = VFMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4302 $xmm16 = VFMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4303 ; CHECK: $xmm16 = VFMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4304 $xmm16 = VFMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4305 ; CHECK: $xmm16 = VFMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4306 $xmm16 = VFMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4307 ; CHECK: $xmm16 = VFMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4308 $xmm16 = VFMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4309 ; CHECK: $xmm16 = VFMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4310 $xmm16 = VFMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4311 ; CHECK: $xmm16 = VFMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4312 $xmm16 = VFMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4313 ; CHECK: $xmm16 = VFNMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4314 $xmm16 = VFNMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4315 ; CHECK: $xmm16 = VFNMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4316 $xmm16 = VFNMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4317 ; CHECK: $xmm16 = VFNMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4318 $xmm16 = VFNMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4319 ; CHECK: $xmm16 = VFNMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4320 $xmm16 = VFNMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4321 ; CHECK: $xmm16 = VFNMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4322 $xmm16 = VFNMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4323 ; CHECK: $xmm16 = VFNMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4324 $xmm16 = VFNMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4325 ; CHECK: $xmm16 = VFNMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4326 $xmm16 = VFNMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4327 ; CHECK: $xmm16 = VFNMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4328 $xmm16 = VFNMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4329 ; CHECK: $xmm16 = VFNMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4330 $xmm16 = VFNMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4331 ; CHECK: $xmm16 = VFNMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4332 $xmm16 = VFNMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4333 ; CHECK: $xmm16 = VFNMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4334 $xmm16 = VFNMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4335 ; CHECK: $xmm16 = VFNMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4336 $xmm16 = VFNMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4337 ; CHECK: $xmm16 = VFNMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4338 $xmm16 = VFNMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4339 ; CHECK: $xmm16 = VFNMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4340 $xmm16 = VFNMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4341 ; CHECK: $xmm16 = VFNMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4342 $xmm16 = VFNMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4343 ; CHECK: $xmm16 = VFNMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4344 $xmm16 = VFNMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4345 ; CHECK: $xmm16 = VFNMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4346 $xmm16 = VFNMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4347 ; CHECK: $xmm16 = VFNMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4348 $xmm16 = VFNMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4349 ; CHECK: $xmm16 = VFNMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4350 $xmm16 = VFNMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4351 ; CHECK: $xmm16 = VFNMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4352 $xmm16 = VFNMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4353 ; CHECK: $xmm16 = VFNMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4354 $xmm16 = VFNMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4355 ; CHECK: $xmm16 = VFNMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4356 $xmm16 = VFNMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4357 ; CHECK: $xmm16 = VFNMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4358 $xmm16 = VFNMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4359 ; CHECK: $xmm16 = VFNMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4360 $xmm16 = VFNMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4361 ; CHECK: $xmm16 = VFNMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4362 $xmm16 = VFNMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4363 ; CHECK: $xmm16 = VFNMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4364 $xmm16 = VFNMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4365 ; CHECK: $xmm16 = VFNMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4366 $xmm16 = VFNMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4367 ; CHECK: $xmm16 = VFNMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4368 $xmm16 = VFNMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4369 ; CHECK: $xmm16 = VFNMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4370 $xmm16 = VFNMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4371 ; CHECK: $xmm16 = VFNMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4372 $xmm16 = VFNMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4373 ; CHECK: $xmm16 = VFNMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4374 $xmm16 = VFNMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4375 ; CHECK: $xmm16 = VFNMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4376 $xmm16 = VFNMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4377 ; CHECK: $xmm16 = VFNMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4378 $xmm16 = VFNMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4379 ; CHECK: $xmm16 = VFNMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4380 $xmm16 = VFNMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4381 ; CHECK: $xmm16 = VFNMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4382 $xmm16 = VFNMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4383 ; CHECK: $xmm16 = VFNMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4384 $xmm16 = VFNMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4385 ; CHECK: $xmm16 = VFNMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4386 $xmm16 = VFNMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4387 ; CHECK: $xmm16 = VFNMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4388 $xmm16 = VFNMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4389 ; CHECK: $xmm16 = VFNMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4390 $xmm16 = VFNMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4391 ; CHECK: $xmm16 = VFNMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4392 $xmm16 = VFNMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4393 ; CHECK: $xmm16 = VFNMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4394 $xmm16 = VFNMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4395 ; CHECK: $xmm16 = VFNMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4396 $xmm16 = VFNMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4397 ; CHECK: $xmm16 = VFNMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4398 $xmm16 = VFNMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4399 ; CHECK: $xmm16 = VFNMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4400 $xmm16 = VFNMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4401 ; CHECK: $xmm16 = VFNMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4402 $xmm16 = VFNMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4403 ; CHECK: $xmm16 = VFNMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4404 $xmm16 = VFNMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr4405 ; CHECK: $xmm16 = VFNMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4406 $xmm16 = VFNMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr4407 ; CHECK: $xmm16 = VFNMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4408 $xmm16 = VFNMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr4409 ; CHECK: VPEXTRBZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34410 VPEXTRBZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34411 ; CHECK: $eax = VPEXTRBZrri $xmm16, 14412 $eax = VPEXTRBZrri $xmm16, 14413 ; CHECK: VPEXTRDZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34414 VPEXTRDZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34415 ; CHECK: $eax = VPEXTRDZrri $xmm16, 14416 $eax = VPEXTRDZrri $xmm16, 14417 ; CHECK: VPEXTRQZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34418 VPEXTRQZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34419 ; CHECK: $rax = VPEXTRQZrri $xmm16, 14420 $rax = VPEXTRQZrri $xmm16, 14421 ; CHECK: VPEXTRWZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34422 VPEXTRWZmri $rdi, 1, $noreg, 0, $noreg, $xmm16, 34423 ; CHECK: $eax = VPEXTRWZrri $xmm16, 14424 $eax = VPEXTRWZrri $xmm16, 14425 ; CHECK: $xmm16 = VPINSRBZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34426 $xmm16 = VPINSRBZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34427 ; CHECK: $xmm16 = VPINSRBZrri $xmm16, $edi, 54428 $xmm16 = VPINSRBZrri $xmm16, $edi, 54429 ; CHECK: $xmm16 = VPINSRDZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34430 $xmm16 = VPINSRDZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34431 ; CHECK: $xmm16 = VPINSRDZrri $xmm16, $edi, 54432 $xmm16 = VPINSRDZrri $xmm16, $edi, 54433 ; CHECK: $xmm16 = VPINSRQZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34434 $xmm16 = VPINSRQZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34435 ; CHECK: $xmm16 = VPINSRQZrri $xmm16, $rdi, 54436 $xmm16 = VPINSRQZrri $xmm16, $rdi, 54437 ; CHECK: $xmm16 = VPINSRWZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34438 $xmm16 = VPINSRWZrmi $xmm16, $rsi, 1, $noreg, 0, $noreg, 34439 ; CHECK: $xmm16 = VPINSRWZrri $xmm16, $edi, 54440 $xmm16 = VPINSRWZrri $xmm16, $edi, 54441 ; CHECK: $xmm16 = VSQRTSDZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4442 $xmm16 = VSQRTSDZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4443 ; CHECK: $xmm16 = VSQRTSDZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4444 $xmm16 = VSQRTSDZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4445 ; CHECK: $xmm16 = VSQRTSDZr $xmm16, $xmm1, implicit $mxcsr4446 $xmm16 = VSQRTSDZr $xmm16, $xmm1, implicit $mxcsr4447 ; CHECK: $xmm16 = VSQRTSDZr_Int $xmm16, $xmm1, implicit $mxcsr4448 $xmm16 = VSQRTSDZr_Int $xmm16, $xmm1, implicit $mxcsr4449 ; CHECK: $xmm16 = VSQRTSSZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4450 $xmm16 = VSQRTSSZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4451 ; CHECK: $xmm16 = VSQRTSSZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4452 $xmm16 = VSQRTSSZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4453 ; CHECK: $xmm16 = VSQRTSSZr $xmm16, $xmm1, implicit $mxcsr4454 $xmm16 = VSQRTSSZr $xmm16, $xmm1, implicit $mxcsr4455 ; CHECK: $xmm16 = VSQRTSSZr_Int $xmm16, $xmm1, implicit $mxcsr4456 $xmm16 = VSQRTSSZr_Int $xmm16, $xmm1, implicit $mxcsr4457 ; CHECK: $rdi = VCVTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4458 $rdi = VCVTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4459 ; CHECK: $rdi = VCVTSD2SI64Zrr_Int $xmm16, implicit $mxcsr4460 $rdi = VCVTSD2SI64Zrr_Int $xmm16, implicit $mxcsr4461 ; CHECK: $edi = VCVTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4462 $edi = VCVTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4463 ; CHECK: $edi = VCVTSD2SIZrr_Int $xmm16, implicit $mxcsr4464 $edi = VCVTSD2SIZrr_Int $xmm16, implicit $mxcsr4465 ; CHECK: $xmm16 = VCVTSD2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4466 $xmm16 = VCVTSD2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4467 ; CHECK: $xmm16 = VCVTSD2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4468 $xmm16 = VCVTSD2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4469 ; CHECK: $xmm16 = VCVTSD2SSZrr $xmm16, $xmm16, implicit $mxcsr4470 $xmm16 = VCVTSD2SSZrr $xmm16, $xmm16, implicit $mxcsr4471 ; CHECK: $xmm16 = VCVTSD2SSZrr_Int $xmm16, $xmm16, implicit $mxcsr4472 $xmm16 = VCVTSD2SSZrr_Int $xmm16, $xmm16, implicit $mxcsr4473 ; CHECK: $xmm16 = VCVTSI2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg4474 $xmm16 = VCVTSI2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg4475 ; CHECK: $xmm16 = VCVTSI2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg4476 $xmm16 = VCVTSI2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg4477 ; CHECK: $xmm16 = VCVTSI2SDZrr $xmm16, $edi4478 $xmm16 = VCVTSI2SDZrr $xmm16, $edi4479 ; CHECK: $xmm16 = VCVTSI2SDZrr_Int $xmm16, $edi4480 $xmm16 = VCVTSI2SDZrr_Int $xmm16, $edi4481 ; CHECK: $xmm16 = VCVTSI2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4482 $xmm16 = VCVTSI2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4483 ; CHECK: $xmm16 = VCVTSI2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4484 $xmm16 = VCVTSI2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4485 ; CHECK: $xmm16 = VCVTSI2SSZrr $xmm16, $edi, implicit $mxcsr4486 $xmm16 = VCVTSI2SSZrr $xmm16, $edi, implicit $mxcsr4487 ; CHECK: $xmm16 = VCVTSI2SSZrr_Int $xmm16, $edi, implicit $mxcsr4488 $xmm16 = VCVTSI2SSZrr_Int $xmm16, $edi, implicit $mxcsr4489 ; CHECK: $xmm16 = VCVTSI642SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4490 $xmm16 = VCVTSI642SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4491 ; CHECK: $xmm16 = VCVTSI642SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4492 $xmm16 = VCVTSI642SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4493 ; CHECK: $xmm16 = VCVTSI642SDZrr $xmm16, $rdi, implicit $mxcsr4494 $xmm16 = VCVTSI642SDZrr $xmm16, $rdi, implicit $mxcsr4495 ; CHECK: $xmm16 = VCVTSI642SDZrr_Int $xmm16, $rdi, implicit $mxcsr4496 $xmm16 = VCVTSI642SDZrr_Int $xmm16, $rdi, implicit $mxcsr4497 ; CHECK: $xmm16 = VCVTSI642SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4498 $xmm16 = VCVTSI642SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4499 ; CHECK: $xmm16 = VCVTSI642SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4500 $xmm16 = VCVTSI642SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4501 ; CHECK: $xmm16 = VCVTSI642SSZrr $xmm16, $rdi, implicit $mxcsr4502 $xmm16 = VCVTSI642SSZrr $xmm16, $rdi, implicit $mxcsr4503 ; CHECK: $xmm16 = VCVTSI642SSZrr_Int $xmm16, $rdi, implicit $mxcsr4504 $xmm16 = VCVTSI642SSZrr_Int $xmm16, $rdi, implicit $mxcsr4505 ; CHECK: $xmm16 = VCVTSS2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4506 $xmm16 = VCVTSS2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4507 ; CHECK: $xmm16 = VCVTSS2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4508 $xmm16 = VCVTSS2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4509 ; CHECK: $xmm16 = VCVTSS2SDZrr $xmm16, $xmm16, implicit $mxcsr4510 $xmm16 = VCVTSS2SDZrr $xmm16, $xmm16, implicit $mxcsr4511 ; CHECK: $xmm16 = VCVTSS2SDZrr_Int $xmm16, $xmm16, implicit $mxcsr4512 $xmm16 = VCVTSS2SDZrr_Int $xmm16, $xmm16, implicit $mxcsr4513 ; CHECK: $rdi = VCVTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4514 $rdi = VCVTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4515 ; CHECK: $rdi = VCVTSS2SI64Zrr_Int $xmm16, implicit $mxcsr4516 $rdi = VCVTSS2SI64Zrr_Int $xmm16, implicit $mxcsr4517 ; CHECK: $edi = VCVTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4518 $edi = VCVTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4519 ; CHECK: $edi = VCVTSS2SIZrr_Int $xmm16, implicit $mxcsr4520 $edi = VCVTSS2SIZrr_Int $xmm16, implicit $mxcsr4521 ; CHECK: $rdi = VCVTTSD2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4522 $rdi = VCVTTSD2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4523 ; CHECK: $rdi = VCVTTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4524 $rdi = VCVTTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4525 ; CHECK: $rdi = VCVTTSD2SI64Zrr $xmm16, implicit $mxcsr4526 $rdi = VCVTTSD2SI64Zrr $xmm16, implicit $mxcsr4527 ; CHECK: $rdi = VCVTTSD2SI64Zrr_Int $xmm16, implicit $mxcsr4528 $rdi = VCVTTSD2SI64Zrr_Int $xmm16, implicit $mxcsr4529 ; CHECK: $edi = VCVTTSD2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4530 $edi = VCVTTSD2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4531 ; CHECK: $edi = VCVTTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4532 $edi = VCVTTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4533 ; CHECK: $edi = VCVTTSD2SIZrr $xmm16, implicit $mxcsr4534 $edi = VCVTTSD2SIZrr $xmm16, implicit $mxcsr4535 ; CHECK: $edi = VCVTTSD2SIZrr_Int $xmm16, implicit $mxcsr4536 $edi = VCVTTSD2SIZrr_Int $xmm16, implicit $mxcsr4537 ; CHECK: $rdi = VCVTTSS2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4538 $rdi = VCVTTSS2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4539 ; CHECK: $rdi = VCVTTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4540 $rdi = VCVTTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4541 ; CHECK: $rdi = VCVTTSS2SI64Zrr $xmm16, implicit $mxcsr4542 $rdi = VCVTTSS2SI64Zrr $xmm16, implicit $mxcsr4543 ; CHECK: $rdi = VCVTTSS2SI64Zrr_Int $xmm16, implicit $mxcsr4544 $rdi = VCVTTSS2SI64Zrr_Int $xmm16, implicit $mxcsr4545 ; CHECK: $edi = VCVTTSS2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4546 $edi = VCVTTSS2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4547 ; CHECK: $edi = VCVTTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4548 $edi = VCVTTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr4549 ; CHECK: $edi = VCVTTSS2SIZrr $xmm16, implicit $mxcsr4550 $edi = VCVTTSS2SIZrr $xmm16, implicit $mxcsr4551 ; CHECK: $edi = VCVTTSS2SIZrr_Int $xmm16, implicit $mxcsr4552 $edi = VCVTTSS2SIZrr_Int $xmm16, implicit $mxcsr4553 ; CHECK: $xmm16 = VMOV64toSDZrr $rdi4554 $xmm16 = VMOV64toSDZrr $rdi4555 ; CHECK: $xmm16 = VMOVDI2SSZrr $eax4556 $xmm16 = VMOVDI2SSZrr $eax4557 ; CHECK: VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm164558 VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm164559 ; CHECK: $xmm16 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg4560 $xmm16 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg4561 ; CHECK: $xmm16 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg4562 $xmm16 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg4563 ; CHECK: $xmm16 = VMOVSDZrr $xmm16, $xmm14564 $xmm16 = VMOVSDZrr $xmm16, $xmm14565 ; CHECK: $rax = VMOVSDto64Zrr $xmm164566 $rax = VMOVSDto64Zrr $xmm164567 ; CHECK: VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm164568 VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm164569 ; CHECK: $xmm16 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg4570 $xmm16 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg4571 ; CHECK: $xmm16 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg4572 $xmm16 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg4573 ; CHECK: $xmm16 = VMOVSSZrr $xmm16, $xmm14574 $xmm16 = VMOVSSZrr $xmm16, $xmm14575 ; CHECK: $eax = VMOVSS2DIZrr $xmm164576 $eax = VMOVSS2DIZrr $xmm164577 ; CHECK: $xmm16 = VMOV64toPQIZrr $rdi4578 $xmm16 = VMOV64toPQIZrr $rdi4579 ; CHECK: $xmm16 = VMOV64toPQIZrm $rdi, 1, $noreg, 0, $noreg4580 $xmm16 = VMOV64toPQIZrm $rdi, 1, $noreg, 0, $noreg4581 ; CHECK: $xmm16 = VMOV64toSDZrr $rdi4582 $xmm16 = VMOV64toSDZrr $rdi4583 ; CHECK: $xmm16 = VMOVDI2PDIZrm $rip, 1, $noreg, 0, $noreg4584 $xmm16 = VMOVDI2PDIZrm $rip, 1, $noreg, 0, $noreg4585 ; CHECK: $xmm16 = VMOVDI2PDIZrr $edi4586 $xmm16 = VMOVDI2PDIZrr $edi4587 ; CHECK: $xmm16 = VMOVLHPSZrr $xmm16, $xmm14588 $xmm16 = VMOVLHPSZrr $xmm16, $xmm14589 ; CHECK: $xmm16 = VMOVHLPSZrr $xmm16, $xmm14590 $xmm16 = VMOVHLPSZrr $xmm16, $xmm14591 ; CHECK: VMOVPDI2DIZmr $rdi, 1, $noreg, 0, $noreg, $xmm164592 VMOVPDI2DIZmr $rdi, 1, $noreg, 0, $noreg, $xmm164593 ; CHECK: $edi = VMOVPDI2DIZrr $xmm164594 $edi = VMOVPDI2DIZrr $xmm164595 ; CHECK: $xmm16 = VMOVPQI2QIZrr $xmm164596 $xmm16 = VMOVPQI2QIZrr $xmm164597 ; CHECK: VMOVPQI2QIZmr $rdi, 1, $noreg, 0, $noreg, $xmm164598 VMOVPQI2QIZmr $rdi, 1, $noreg, 0, $noreg, $xmm164599 ; CHECK: $rdi = VMOVPQIto64Zrr $xmm164600 $rdi = VMOVPQIto64Zrr $xmm164601 ; CHECK: VMOVPQIto64Zmr $rdi, 1, $noreg, 0, $noreg, $xmm164602 VMOVPQIto64Zmr $rdi, 1, $noreg, 0, $noreg, $xmm164603 ; CHECK: $xmm16 = VMOVQI2PQIZrm $rip, 1, $noreg, 0, $noreg4604 $xmm16 = VMOVQI2PQIZrm $rip, 1, $noreg, 0, $noreg4605 ; CHECK: $xmm16 = VMOVZPQILo2PQIZrr $xmm164606 $xmm16 = VMOVZPQILo2PQIZrr $xmm164607 ; CHECK: VCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4608 VCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4609 ; CHECK: VCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4610 VCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4611 ; CHECK: VCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4612 VCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4613 ; CHECK: VCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4614 VCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4615 ; CHECK: VUCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4616 VUCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4617 ; CHECK: VUCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4618 VUCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4619 ; CHECK: VUCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4620 VUCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4621 ; CHECK: VUCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4622 VUCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4623 ; CHECK: VCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4624 VCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4625 ; CHECK: VCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4626 VCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4627 ; CHECK: VCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4628 VCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4629 ; CHECK: VCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4630 VCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4631 ; CHECK: VUCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4632 VUCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4633 ; CHECK: VUCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4634 VUCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4635 ; CHECK: VUCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4636 VUCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr4637 ; CHECK: VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4638 VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr4639 ; CHECK: $xmm16 = VRNDSCALESDZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4640 $xmm16 = VRNDSCALESDZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4641 ; CHECK: $xmm16 = VRNDSCALESDZrri $xmm16, $xmm1, 15, implicit $mxcsr4642 $xmm16 = VRNDSCALESDZrri $xmm16, $xmm1, 15, implicit $mxcsr4643 ; CHECK: $xmm16 = VRNDSCALESSZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4644 $xmm16 = VRNDSCALESSZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4645 ; CHECK: $xmm16 = VRNDSCALESSZrri $xmm16, $xmm1, 15, implicit $mxcsr4646 $xmm16 = VRNDSCALESSZrri $xmm16, $xmm1, 15, implicit $mxcsr4647 ; CHECK: $xmm16 = VRNDSCALESDZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4648 $xmm16 = VRNDSCALESDZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4649 ; CHECK: $xmm16 = VRNDSCALESDZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr4650 $xmm16 = VRNDSCALESDZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr4651 ; CHECK: $xmm16 = VRNDSCALESSZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4652 $xmm16 = VRNDSCALESSZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr4653 ; CHECK: $xmm16 = VRNDSCALESSZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr4654 $xmm16 = VRNDSCALESSZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr4655 ; CHECK: $xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4656 $xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4657 ; CHECK: $xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 31, implicit $mxcsr4658 $xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 31, implicit $mxcsr4659 ; CHECK: $xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4660 $xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4661 ; CHECK: $xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 31, implicit $mxcsr4662 $xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 31, implicit $mxcsr4663 ; CHECK: $xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4664 $xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4665 ; CHECK: $xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr4666 $xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr4667 ; CHECK: $xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4668 $xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr4669 ; CHECK: $xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr4670 $xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr4671 4672 RET644673...4674