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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX4 5; Verify that we select the correct version of the instruction that stores the low 64-bits6; of a 128-bit vector. We want to avoid int/fp domain crossing penalties, so ignore the7; bitcast ops and choose:8;9; movlps for floats10; movlpd for doubles11; movq for integers12 13define void @store_floats(<4 x float> %x, ptr %p) {14; SSE-LABEL: store_floats:15; SSE:       # %bb.0:16; SSE-NEXT:    addps %xmm0, %xmm017; SSE-NEXT:    movlps %xmm0, (%rdi)18; SSE-NEXT:    retq19;20; AVX-LABEL: store_floats:21; AVX:       # %bb.0:22; AVX-NEXT:    vaddps %xmm0, %xmm0, %xmm023; AVX-NEXT:    vmovlps %xmm0, (%rdi)24; AVX-NEXT:    retq25  %a = fadd <4 x float> %x, %x26  %b = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>27  %c = bitcast <2 x float> %b to i6428  store i64 %c, ptr %p29  ret void30}31 32define void @store_double(<2 x double> %x, ptr %p) {33; SSE-LABEL: store_double:34; SSE:       # %bb.0:35; SSE-NEXT:    addsd %xmm0, %xmm036; SSE-NEXT:    movsd %xmm0, (%rdi)37; SSE-NEXT:    retq38;39; AVX-LABEL: store_double:40; AVX:       # %bb.0:41; AVX-NEXT:    vaddsd %xmm0, %xmm0, %xmm042; AVX-NEXT:    vmovsd %xmm0, (%rdi)43; AVX-NEXT:    retq44  %a = fadd <2 x double> %x, %x45  %b = extractelement <2 x double> %a, i32 046  %c = bitcast double %b to i6447  store i64 %c, ptr %p48  ret void49}50 51define void @store_int(<4 x i32> %x, ptr %p) {52; SSE-LABEL: store_int:53; SSE:       # %bb.0:54; SSE-NEXT:    paddd %xmm0, %xmm055; SSE-NEXT:    movq %xmm0, (%rdi)56; SSE-NEXT:    retq57;58; AVX-LABEL: store_int:59; AVX:       # %bb.0:60; AVX-NEXT:    vpaddd %xmm0, %xmm0, %xmm061; AVX-NEXT:    vmovq %xmm0, (%rdi)62; AVX-NEXT:    retq63  %a = add <4 x i32> %x, %x64  %b = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>65  %c = bitcast <2 x i32> %b to <2 x float>66  store <2 x float> %c, ptr %p67  ret void68}69 70define void @store_h_double(<2 x double> %x, ptr %p) {71; SSE-LABEL: store_h_double:72; SSE:       # %bb.0:73; SSE-NEXT:    addpd %xmm0, %xmm074; SSE-NEXT:    movhpd %xmm0, (%rdi)75; SSE-NEXT:    retq76;77; AVX-LABEL: store_h_double:78; AVX:       # %bb.0:79; AVX-NEXT:    vaddpd %xmm0, %xmm0, %xmm080; AVX-NEXT:    vmovhpd %xmm0, (%rdi)81; AVX-NEXT:    retq82  %a = fadd <2 x double> %x, %x83  %b = extractelement <2 x double> %a, i32 184  %c = bitcast double %b to i6485  store i64 %c, ptr %p86  ret void87}88