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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=x86_64 | FileCheck %s3 4define void @PR117684(i1 %cond, <8 x float> %vec, ptr %ptr1, ptr %ptr2) #0 {5; CHECK-LABEL: PR117684:6; CHECK: # %bb.0:7; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm18; CHECK-NEXT: vcmpnltss %xmm1, %xmm0, %k19; CHECK-NEXT: vbroadcastss {{.*#+}} xmm0 = [NaN,NaN,NaN,NaN]10; CHECK-NEXT: vinsertf32x4 $0, %xmm0, %ymm0, %ymm0 {%k1} {z}11; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm012; CHECK-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm213; CHECK-NEXT: vbroadcastss %xmm2, %ymm214; CHECK-NEXT: testb $1, %dil15; CHECK-NEXT: cmoveq %rdx, %rsi16; CHECK-NEXT: vmovups %ymm2, (%rsi)17; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm018; CHECK-NEXT: vbroadcastss %xmm0, %ymm019; CHECK-NEXT: vmovups %ymm0, (%rdx)20; CHECK-NEXT: vzeroupper21; CHECK-NEXT: retq22 %cmp = fcmp olt <8 x float> %vec, zeroinitializer23 %sel1 = select <8 x i1> %cmp, <8 x float> zeroinitializer, <8 x float>24 <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000,25 float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>26 %fmul1 = fmul <8 x float> zeroinitializer, %sel127 %shuffle = shufflevector <8 x float> %fmul1, <8 x float> zeroinitializer, <8 x i32> zeroinitializer28 %fmul2 = fmul <8 x float> %shuffle,29 <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000,30 float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>31 %sel2 = select i1 %cond, ptr %ptr1, ptr %ptr232 store <8 x float> %fmul2, ptr %sel2, align 433 %fmul3 = fmul <8 x float> %shuffle, zeroinitializer34 store <8 x float> %fmul3, ptr %ptr2, align 435 ret void36}37 38attributes #0 = { "target-cpu"="skylake-avx512" }39