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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefixes=CHECK,X863; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefixes=CHECK,X644 5; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/f16c-builtins.c6 7define float @test_cvtsh_ss(i16 %a0) nounwind {8; X86-LABEL: test_cvtsh_ss:9; X86: # %bb.0:10; X86-NEXT: pushl %eax11; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax12; X86-NEXT: vmovd %eax, %xmm013; X86-NEXT: vcvtph2ps %xmm0, %xmm014; X86-NEXT: vmovss %xmm0, (%esp)15; X86-NEXT: flds (%esp)16; X86-NEXT: popl %eax17; X86-NEXT: retl18;19; X64-LABEL: test_cvtsh_ss:20; X64: # %bb.0:21; X64-NEXT: vmovd %edi, %xmm022; X64-NEXT: vcvtph2ps %xmm0, %xmm023; X64-NEXT: retq24 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 025 %ins1 = insertelement <8 x i16> %ins0, i16 0, i32 126 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 227 %ins3 = insertelement <8 x i16> %ins2, i16 0, i32 328 %ins4 = insertelement <8 x i16> %ins3, i16 0, i32 429 %ins5 = insertelement <8 x i16> %ins4, i16 0, i32 530 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 631 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 732 %shuffle = shufflevector <8 x i16> %ins7, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>33 %bc = bitcast <4 x i16> %shuffle to <4 x half>34 %cvt = fpext <4 x half> %bc to <4 x float>35 %res = extractelement <4 x float> %cvt, i32 036 ret float %res37}38 39define i16 @test_cvtss_sh(float %a0) nounwind {40; X86-LABEL: test_cvtss_sh:41; X86: # %bb.0:42; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero43; X86-NEXT: vcvtps2ph $0, %xmm0, %xmm044; X86-NEXT: vmovd %xmm0, %eax45; X86-NEXT: # kill: def $ax killed $ax killed $eax46; X86-NEXT: retl47;48; X64-LABEL: test_cvtss_sh:49; X64: # %bb.0:50; X64-NEXT: vcvtps2ph $0, %xmm0, %xmm051; X64-NEXT: vmovd %xmm0, %eax52; X64-NEXT: # kill: def $ax killed $ax killed $eax53; X64-NEXT: retq54 %ins0 = insertelement <4 x float> undef, float %a0, i32 055 %ins1 = insertelement <4 x float> %ins0, float 0.000000e+00, i32 156 %ins2 = insertelement <4 x float> %ins1, float 0.000000e+00, i32 257 %ins3 = insertelement <4 x float> %ins2, float 0.000000e+00, i32 358 %cvt = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %ins3, i32 0)59 %res = extractelement <8 x i16> %cvt, i32 060 ret i16 %res61}62 63define <4 x float> @test_mm_cvtph_ps(<2 x i64> %a0) nounwind {64; CHECK-LABEL: test_mm_cvtph_ps:65; CHECK: # %bb.0:66; CHECK-NEXT: vcvtph2ps %xmm0, %xmm067; CHECK-NEXT: ret{{[l|q]}}68 %arg0 = bitcast <2 x i64> %a0 to <8 x i16>69 %shuffle = shufflevector <8 x i16> %arg0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>70 %bc = bitcast <4 x i16> %shuffle to <4 x half>71 %res = fpext <4 x half> %bc to <4 x float>72 ret <4 x float> %res73}74 75define <8 x float> @test_mm256_cvtph_ps(<2 x i64> %a0) nounwind {76; CHECK-LABEL: test_mm256_cvtph_ps:77; CHECK: # %bb.0:78; CHECK-NEXT: vcvtph2ps %xmm0, %ymm079; CHECK-NEXT: ret{{[l|q]}}80 %arg0 = bitcast <2 x i64> %a0 to <8 x i16>81 %bc = bitcast <8 x i16> %arg0 to <8 x half>82 %res = fpext <8 x half> %bc to <8 x float>83 ret <8 x float> %res84}85 86define <2 x i64> @test_mm_cvtps_ph(<4 x float> %a0) nounwind {87; CHECK-LABEL: test_mm_cvtps_ph:88; CHECK: # %bb.0:89; CHECK-NEXT: vcvtps2ph $0, %xmm0, %xmm090; CHECK-NEXT: ret{{[l|q]}}91 %cvt = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)92 %res = bitcast <8 x i16> %cvt to <2 x i64>93 ret <2 x i64> %res94}95 96define <2 x i64> @test_mm256_cvtps_ph(<8 x float> %a0) nounwind {97; CHECK-LABEL: test_mm256_cvtps_ph:98; CHECK: # %bb.0:99; CHECK-NEXT: vcvtps2ph $0, %ymm0, %xmm0100; CHECK-NEXT: vzeroupper101; CHECK-NEXT: ret{{[l|q]}}102 %cvt = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)103 %res = bitcast <8 x i16> %cvt to <2 x i64>104 ret <2 x i64> %res105}106 107declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly108declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly109 110declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly111declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly112