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1; assert in DAGlegalizer with fake use of 1-element vectors.2; RUN: llc -stop-after=finalize-isel -mtriple=x86_64-unknown-linux -filetype=asm -o - %s | FileCheck %s3;4; ModuleID = 't2.cpp'5; source_filename = "t2.cpp"6; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"7;8; Check that we get past ISel and generate FAKE_USE machine instructions for9; one-element vectors.10;11; CHECK: bb.0.entry:12; CHECK-DAG: %1:gr64 = COPY $rdi13; CHECK-DAG: %0:vr128 = COPY $xmm014; CHECK: %2:vr64 =15; CHECK-DAG: FAKE_USE %116; CHECK-DAG: FAKE_USE %017; CHECK: RET18 19 20target triple = "x86_64-unknown-unknown"21 22; Function Attrs: nounwind sspstrong uwtable23define <4 x float> @_Z3runDv4_fDv1_x(<4 x float> %r, i64 %b.coerce) local_unnamed_addr #0 {24entry:25 %0 = insertelement <1 x i64> undef, i64 %b.coerce, i32 026 %1 = bitcast i64 %b.coerce to <1 x i64>27 %2 = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %r, <1 x i64> %1)28 tail call void (...) @llvm.fake.use(<1 x i64> %0)29 tail call void (...) @llvm.fake.use(<4 x float> %r)30 ret <4 x float> %231}32 33; Function Attrs: nounwind readnone34declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, <1 x i64>)35 36; Function Attrs: nounwind37declare void @llvm.fake.use(...)38 39attributes #0 = { "target-cpu"="btver2" optdebug }40