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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE3; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefixes=AVX,AVXONLY4; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx512f < %s | FileCheck %s --check-prefixes=AVX,AVX5125; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512bw,+avx512vl < %s | FileCheck %s --check-prefixes=AVX,AVX5126 7; Verify that fast-isel knows how to select aligned/unaligned vector loads.8; Also verify that the selected load instruction is in the correct domain.9 10define <16 x i8> @test_v16i8(ptr %V) {11; SSE-LABEL: test_v16i8:12; SSE: # %bb.0: # %entry13; SSE-NEXT: movdqa (%rdi), %xmm014; SSE-NEXT: retq15;16; AVX-LABEL: test_v16i8:17; AVX: # %bb.0: # %entry18; AVX-NEXT: vmovdqa (%rdi), %xmm019; AVX-NEXT: retq20entry:21 %0 = load <16 x i8>, ptr %V, align 1622 ret <16 x i8> %023}24 25define <8 x i16> @test_v8i16(ptr %V) {26; SSE-LABEL: test_v8i16:27; SSE: # %bb.0: # %entry28; SSE-NEXT: movdqa (%rdi), %xmm029; SSE-NEXT: retq30;31; AVX-LABEL: test_v8i16:32; AVX: # %bb.0: # %entry33; AVX-NEXT: vmovdqa (%rdi), %xmm034; AVX-NEXT: retq35entry:36 %0 = load <8 x i16>, ptr %V, align 1637 ret <8 x i16> %038}39 40define <4 x i32> @test_v4i32(ptr %V) {41; SSE-LABEL: test_v4i32:42; SSE: # %bb.0: # %entry43; SSE-NEXT: movdqa (%rdi), %xmm044; SSE-NEXT: retq45;46; AVX-LABEL: test_v4i32:47; AVX: # %bb.0: # %entry48; AVX-NEXT: vmovdqa (%rdi), %xmm049; AVX-NEXT: retq50entry:51 %0 = load <4 x i32>, ptr %V, align 1652 ret <4 x i32> %053}54 55define <2 x i64> @test_v2i64(ptr %V) {56; SSE-LABEL: test_v2i64:57; SSE: # %bb.0: # %entry58; SSE-NEXT: movdqa (%rdi), %xmm059; SSE-NEXT: retq60;61; AVX-LABEL: test_v2i64:62; AVX: # %bb.0: # %entry63; AVX-NEXT: vmovdqa (%rdi), %xmm064; AVX-NEXT: retq65entry:66 %0 = load <2 x i64>, ptr %V, align 1667 ret <2 x i64> %068}69 70define <16 x i8> @test_v16i8_unaligned(ptr %V) {71; SSE-LABEL: test_v16i8_unaligned:72; SSE: # %bb.0: # %entry73; SSE-NEXT: movdqu (%rdi), %xmm074; SSE-NEXT: retq75;76; AVX-LABEL: test_v16i8_unaligned:77; AVX: # %bb.0: # %entry78; AVX-NEXT: vmovdqu (%rdi), %xmm079; AVX-NEXT: retq80entry:81 %0 = load <16 x i8>, ptr %V, align 482 ret <16 x i8> %083}84 85define <8 x i16> @test_v8i16_unaligned(ptr %V) {86; SSE-LABEL: test_v8i16_unaligned:87; SSE: # %bb.0: # %entry88; SSE-NEXT: movdqu (%rdi), %xmm089; SSE-NEXT: retq90;91; AVX-LABEL: test_v8i16_unaligned:92; AVX: # %bb.0: # %entry93; AVX-NEXT: vmovdqu (%rdi), %xmm094; AVX-NEXT: retq95entry:96 %0 = load <8 x i16>, ptr %V, align 497 ret <8 x i16> %098}99 100define <4 x i32> @test_v4i32_unaligned(ptr %V) {101; SSE-LABEL: test_v4i32_unaligned:102; SSE: # %bb.0: # %entry103; SSE-NEXT: movdqu (%rdi), %xmm0104; SSE-NEXT: retq105;106; AVX-LABEL: test_v4i32_unaligned:107; AVX: # %bb.0: # %entry108; AVX-NEXT: vmovdqu (%rdi), %xmm0109; AVX-NEXT: retq110entry:111 %0 = load <4 x i32>, ptr %V, align 4112 ret <4 x i32> %0113}114 115define <2 x i64> @test_v2i64_unaligned(ptr %V) {116; SSE-LABEL: test_v2i64_unaligned:117; SSE: # %bb.0: # %entry118; SSE-NEXT: movdqu (%rdi), %xmm0119; SSE-NEXT: retq120;121; AVX-LABEL: test_v2i64_unaligned:122; AVX: # %bb.0: # %entry123; AVX-NEXT: vmovdqu (%rdi), %xmm0124; AVX-NEXT: retq125entry:126 %0 = load <2 x i64>, ptr %V, align 4127 ret <2 x i64> %0128}129 130define <4 x float> @test_v4f32(ptr %V) {131; SSE-LABEL: test_v4f32:132; SSE: # %bb.0: # %entry133; SSE-NEXT: movaps (%rdi), %xmm0134; SSE-NEXT: retq135;136; AVX-LABEL: test_v4f32:137; AVX: # %bb.0: # %entry138; AVX-NEXT: vmovaps (%rdi), %xmm0139; AVX-NEXT: retq140entry:141 %0 = load <4 x float>, ptr %V, align 16142 ret <4 x float> %0143}144 145define <2 x double> @test_v2f64(ptr %V) {146; SSE-LABEL: test_v2f64:147; SSE: # %bb.0: # %entry148; SSE-NEXT: movapd (%rdi), %xmm0149; SSE-NEXT: retq150;151; AVX-LABEL: test_v2f64:152; AVX: # %bb.0: # %entry153; AVX-NEXT: vmovapd (%rdi), %xmm0154; AVX-NEXT: retq155entry:156 %0 = load <2 x double>, ptr %V, align 16157 ret <2 x double> %0158}159 160define <4 x float> @test_v4f32_unaligned(ptr %V) {161; SSE-LABEL: test_v4f32_unaligned:162; SSE: # %bb.0: # %entry163; SSE-NEXT: movups (%rdi), %xmm0164; SSE-NEXT: retq165;166; AVX-LABEL: test_v4f32_unaligned:167; AVX: # %bb.0: # %entry168; AVX-NEXT: vmovups (%rdi), %xmm0169; AVX-NEXT: retq170entry:171 %0 = load <4 x float>, ptr %V, align 4172 ret <4 x float> %0173}174 175define <2 x double> @test_v2f64_unaligned(ptr %V) {176; SSE-LABEL: test_v2f64_unaligned:177; SSE: # %bb.0: # %entry178; SSE-NEXT: movupd (%rdi), %xmm0179; SSE-NEXT: retq180;181; AVX-LABEL: test_v2f64_unaligned:182; AVX: # %bb.0: # %entry183; AVX-NEXT: vmovupd (%rdi), %xmm0184; AVX-NEXT: retq185entry:186 %0 = load <2 x double>, ptr %V, align 4187 ret <2 x double> %0188}189 190define <16 x i8> @test_v16i8_abi_alignment(ptr %V) {191; SSE-LABEL: test_v16i8_abi_alignment:192; SSE: # %bb.0: # %entry193; SSE-NEXT: movdqa (%rdi), %xmm0194; SSE-NEXT: retq195;196; AVX-LABEL: test_v16i8_abi_alignment:197; AVX: # %bb.0: # %entry198; AVX-NEXT: vmovdqa (%rdi), %xmm0199; AVX-NEXT: retq200entry:201 %0 = load <16 x i8>, ptr %V202 ret <16 x i8> %0203}204 205define <8 x i16> @test_v8i16_abi_alignment(ptr %V) {206; SSE-LABEL: test_v8i16_abi_alignment:207; SSE: # %bb.0: # %entry208; SSE-NEXT: movdqa (%rdi), %xmm0209; SSE-NEXT: retq210;211; AVX-LABEL: test_v8i16_abi_alignment:212; AVX: # %bb.0: # %entry213; AVX-NEXT: vmovdqa (%rdi), %xmm0214; AVX-NEXT: retq215entry:216 %0 = load <8 x i16>, ptr %V217 ret <8 x i16> %0218}219 220define <4 x i32> @test_v4i32_abi_alignment(ptr %V) {221; SSE-LABEL: test_v4i32_abi_alignment:222; SSE: # %bb.0: # %entry223; SSE-NEXT: movdqa (%rdi), %xmm0224; SSE-NEXT: retq225;226; AVX-LABEL: test_v4i32_abi_alignment:227; AVX: # %bb.0: # %entry228; AVX-NEXT: vmovdqa (%rdi), %xmm0229; AVX-NEXT: retq230entry:231 %0 = load <4 x i32>, ptr %V232 ret <4 x i32> %0233}234 235define <2 x i64> @test_v2i64_abi_alignment(ptr %V) {236; SSE-LABEL: test_v2i64_abi_alignment:237; SSE: # %bb.0: # %entry238; SSE-NEXT: movdqa (%rdi), %xmm0239; SSE-NEXT: retq240;241; AVX-LABEL: test_v2i64_abi_alignment:242; AVX: # %bb.0: # %entry243; AVX-NEXT: vmovdqa (%rdi), %xmm0244; AVX-NEXT: retq245entry:246 %0 = load <2 x i64>, ptr %V247 ret <2 x i64> %0248}249 250define <4 x float> @test_v4f32_abi_alignment(ptr %V) {251; SSE-LABEL: test_v4f32_abi_alignment:252; SSE: # %bb.0: # %entry253; SSE-NEXT: movaps (%rdi), %xmm0254; SSE-NEXT: retq255;256; AVX-LABEL: test_v4f32_abi_alignment:257; AVX: # %bb.0: # %entry258; AVX-NEXT: vmovaps (%rdi), %xmm0259; AVX-NEXT: retq260entry:261 %0 = load <4 x float>, ptr %V262 ret <4 x float> %0263}264 265define <2 x double> @test_v2f64_abi_alignment(ptr %V) {266; SSE-LABEL: test_v2f64_abi_alignment:267; SSE: # %bb.0: # %entry268; SSE-NEXT: movapd (%rdi), %xmm0269; SSE-NEXT: retq270;271; AVX-LABEL: test_v2f64_abi_alignment:272; AVX: # %bb.0: # %entry273; AVX-NEXT: vmovapd (%rdi), %xmm0274; AVX-NEXT: retq275entry:276 %0 = load <2 x double>, ptr %V277 ret <2 x double> %0278}279 280define <32 x i8> @test_v32i8(ptr %V) {281; SSE-LABEL: test_v32i8:282; SSE: # %bb.0: # %entry283; SSE-NEXT: movaps (%rdi), %xmm0284; SSE-NEXT: movaps 16(%rdi), %xmm1285; SSE-NEXT: retq286;287; AVX-LABEL: test_v32i8:288; AVX: # %bb.0: # %entry289; AVX-NEXT: vmovdqa (%rdi), %ymm0290; AVX-NEXT: retq291entry:292 %0 = load <32 x i8>, ptr %V, align 32293 ret <32 x i8> %0294}295 296define <16 x i16> @test_v16i16(ptr %V) {297; SSE-LABEL: test_v16i16:298; SSE: # %bb.0: # %entry299; SSE-NEXT: movaps (%rdi), %xmm0300; SSE-NEXT: movaps 16(%rdi), %xmm1301; SSE-NEXT: retq302;303; AVX-LABEL: test_v16i16:304; AVX: # %bb.0: # %entry305; AVX-NEXT: vmovdqa (%rdi), %ymm0306; AVX-NEXT: retq307entry:308 %0 = load <16 x i16>, ptr %V, align 32309 ret <16 x i16> %0310}311 312define <8 x i32> @test_v8i32(ptr %V) {313; SSE-LABEL: test_v8i32:314; SSE: # %bb.0: # %entry315; SSE-NEXT: movaps (%rdi), %xmm0316; SSE-NEXT: movaps 16(%rdi), %xmm1317; SSE-NEXT: retq318;319; AVX-LABEL: test_v8i32:320; AVX: # %bb.0: # %entry321; AVX-NEXT: vmovdqa (%rdi), %ymm0322; AVX-NEXT: retq323entry:324 %0 = load <8 x i32>, ptr %V, align 32325 ret <8 x i32> %0326}327 328define <4 x i64> @test_v4i64(ptr %V) {329; SSE-LABEL: test_v4i64:330; SSE: # %bb.0: # %entry331; SSE-NEXT: movaps (%rdi), %xmm0332; SSE-NEXT: movaps 16(%rdi), %xmm1333; SSE-NEXT: retq334;335; AVX-LABEL: test_v4i64:336; AVX: # %bb.0: # %entry337; AVX-NEXT: vmovdqa (%rdi), %ymm0338; AVX-NEXT: retq339entry:340 %0 = load <4 x i64>, ptr %V, align 32341 ret <4 x i64> %0342}343 344define <32 x i8> @test_v32i8_unaligned(ptr %V) {345; SSE-LABEL: test_v32i8_unaligned:346; SSE: # %bb.0: # %entry347; SSE-NEXT: movups (%rdi), %xmm0348; SSE-NEXT: movups 16(%rdi), %xmm1349; SSE-NEXT: retq350;351; AVX-LABEL: test_v32i8_unaligned:352; AVX: # %bb.0: # %entry353; AVX-NEXT: vmovdqu (%rdi), %ymm0354; AVX-NEXT: retq355entry:356 %0 = load <32 x i8>, ptr %V, align 4357 ret <32 x i8> %0358}359 360define <16 x i16> @test_v16i16_unaligned(ptr %V) {361; SSE-LABEL: test_v16i16_unaligned:362; SSE: # %bb.0: # %entry363; SSE-NEXT: movups (%rdi), %xmm0364; SSE-NEXT: movups 16(%rdi), %xmm1365; SSE-NEXT: retq366;367; AVX-LABEL: test_v16i16_unaligned:368; AVX: # %bb.0: # %entry369; AVX-NEXT: vmovdqu (%rdi), %ymm0370; AVX-NEXT: retq371entry:372 %0 = load <16 x i16>, ptr %V, align 4373 ret <16 x i16> %0374}375 376define <8 x i32> @test_v8i32_unaligned(ptr %V) {377; SSE-LABEL: test_v8i32_unaligned:378; SSE: # %bb.0: # %entry379; SSE-NEXT: movups (%rdi), %xmm0380; SSE-NEXT: movups 16(%rdi), %xmm1381; SSE-NEXT: retq382;383; AVX-LABEL: test_v8i32_unaligned:384; AVX: # %bb.0: # %entry385; AVX-NEXT: vmovdqu (%rdi), %ymm0386; AVX-NEXT: retq387entry:388 %0 = load <8 x i32>, ptr %V, align 4389 ret <8 x i32> %0390}391 392define <4 x i64> @test_v4i64_unaligned(ptr %V) {393; SSE-LABEL: test_v4i64_unaligned:394; SSE: # %bb.0: # %entry395; SSE-NEXT: movups (%rdi), %xmm0396; SSE-NEXT: movups 16(%rdi), %xmm1397; SSE-NEXT: retq398;399; AVX-LABEL: test_v4i64_unaligned:400; AVX: # %bb.0: # %entry401; AVX-NEXT: vmovdqu (%rdi), %ymm0402; AVX-NEXT: retq403entry:404 %0 = load <4 x i64>, ptr %V, align 4405 ret <4 x i64> %0406}407 408define <8 x float> @test_v8f32(ptr %V) {409; SSE-LABEL: test_v8f32:410; SSE: # %bb.0: # %entry411; SSE-NEXT: movaps (%rdi), %xmm0412; SSE-NEXT: movaps 16(%rdi), %xmm1413; SSE-NEXT: retq414;415; AVX-LABEL: test_v8f32:416; AVX: # %bb.0: # %entry417; AVX-NEXT: vmovaps (%rdi), %ymm0418; AVX-NEXT: retq419entry:420 %0 = load <8 x float>, ptr %V, align 32421 ret <8 x float> %0422}423 424define <4 x double> @test_v4f64(ptr %V) {425; SSE-LABEL: test_v4f64:426; SSE: # %bb.0: # %entry427; SSE-NEXT: movapd (%rdi), %xmm0428; SSE-NEXT: movapd 16(%rdi), %xmm1429; SSE-NEXT: retq430;431; AVX-LABEL: test_v4f64:432; AVX: # %bb.0: # %entry433; AVX-NEXT: vmovapd (%rdi), %ymm0434; AVX-NEXT: retq435entry:436 %0 = load <4 x double>, ptr %V, align 32437 ret <4 x double> %0438}439 440define <8 x float> @test_v8f32_unaligned(ptr %V) {441; SSE-LABEL: test_v8f32_unaligned:442; SSE: # %bb.0: # %entry443; SSE-NEXT: movups (%rdi), %xmm0444; SSE-NEXT: movups 16(%rdi), %xmm1445; SSE-NEXT: retq446;447; AVX-LABEL: test_v8f32_unaligned:448; AVX: # %bb.0: # %entry449; AVX-NEXT: vmovups (%rdi), %ymm0450; AVX-NEXT: retq451entry:452 %0 = load <8 x float>, ptr %V, align 4453 ret <8 x float> %0454}455 456define <4 x double> @test_v4f64_unaligned(ptr %V) {457; SSE-LABEL: test_v4f64_unaligned:458; SSE: # %bb.0: # %entry459; SSE-NEXT: movupd (%rdi), %xmm0460; SSE-NEXT: movupd 16(%rdi), %xmm1461; SSE-NEXT: retq462;463; AVX-LABEL: test_v4f64_unaligned:464; AVX: # %bb.0: # %entry465; AVX-NEXT: vmovupd (%rdi), %ymm0466; AVX-NEXT: retq467entry:468 %0 = load <4 x double>, ptr %V, align 4469 ret <4 x double> %0470}471 472define <64 x i8> @test_v64i8(ptr %V) {473; SSE-LABEL: test_v64i8:474; SSE: # %bb.0: # %entry475; SSE-NEXT: movaps (%rdi), %xmm0476; SSE-NEXT: movaps 16(%rdi), %xmm1477; SSE-NEXT: movaps 32(%rdi), %xmm2478; SSE-NEXT: movaps 48(%rdi), %xmm3479; SSE-NEXT: retq480;481; AVXONLY-LABEL: test_v64i8:482; AVXONLY: # %bb.0: # %entry483; AVXONLY-NEXT: vmovaps (%rdi), %ymm0484; AVXONLY-NEXT: vmovaps 32(%rdi), %ymm1485; AVXONLY-NEXT: retq486;487; AVX512-LABEL: test_v64i8:488; AVX512: # %bb.0: # %entry489; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0490; AVX512-NEXT: retq491entry:492 %0 = load <64 x i8>, ptr %V, align 64493 ret <64 x i8> %0494}495 496define <32 x i16> @test_v32i16(ptr %V) {497; SSE-LABEL: test_v32i16:498; SSE: # %bb.0: # %entry499; SSE-NEXT: movaps (%rdi), %xmm0500; SSE-NEXT: movaps 16(%rdi), %xmm1501; SSE-NEXT: movaps 32(%rdi), %xmm2502; SSE-NEXT: movaps 48(%rdi), %xmm3503; SSE-NEXT: retq504;505; AVXONLY-LABEL: test_v32i16:506; AVXONLY: # %bb.0: # %entry507; AVXONLY-NEXT: vmovaps (%rdi), %ymm0508; AVXONLY-NEXT: vmovaps 32(%rdi), %ymm1509; AVXONLY-NEXT: retq510;511; AVX512-LABEL: test_v32i16:512; AVX512: # %bb.0: # %entry513; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0514; AVX512-NEXT: retq515entry:516 %0 = load <32 x i16>, ptr %V, align 64517 ret <32 x i16> %0518}519 520define <16 x i32> @test_v16i32(ptr %V) {521; SSE-LABEL: test_v16i32:522; SSE: # %bb.0: # %entry523; SSE-NEXT: movaps (%rdi), %xmm0524; SSE-NEXT: movaps 16(%rdi), %xmm1525; SSE-NEXT: movaps 32(%rdi), %xmm2526; SSE-NEXT: movaps 48(%rdi), %xmm3527; SSE-NEXT: retq528;529; AVXONLY-LABEL: test_v16i32:530; AVXONLY: # %bb.0: # %entry531; AVXONLY-NEXT: vmovaps (%rdi), %ymm0532; AVXONLY-NEXT: vmovaps 32(%rdi), %ymm1533; AVXONLY-NEXT: retq534;535; AVX512-LABEL: test_v16i32:536; AVX512: # %bb.0: # %entry537; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0538; AVX512-NEXT: retq539entry:540 %0 = load <16 x i32>, ptr %V, align 64541 ret <16 x i32> %0542}543 544define <8 x i64> @test_v8i64(ptr %V) {545; SSE-LABEL: test_v8i64:546; SSE: # %bb.0: # %entry547; SSE-NEXT: movaps (%rdi), %xmm0548; SSE-NEXT: movaps 16(%rdi), %xmm1549; SSE-NEXT: movaps 32(%rdi), %xmm2550; SSE-NEXT: movaps 48(%rdi), %xmm3551; SSE-NEXT: retq552;553; AVXONLY-LABEL: test_v8i64:554; AVXONLY: # %bb.0: # %entry555; AVXONLY-NEXT: vmovaps (%rdi), %ymm0556; AVXONLY-NEXT: vmovaps 32(%rdi), %ymm1557; AVXONLY-NEXT: retq558;559; AVX512-LABEL: test_v8i64:560; AVX512: # %bb.0: # %entry561; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0562; AVX512-NEXT: retq563entry:564 %0 = load <8 x i64>, ptr %V, align 64565 ret <8 x i64> %0566}567 568define <64 x i8> @test_v64i8_unaligned(ptr %V) {569; SSE-LABEL: test_v64i8_unaligned:570; SSE: # %bb.0: # %entry571; SSE-NEXT: movups (%rdi), %xmm0572; SSE-NEXT: movups 16(%rdi), %xmm1573; SSE-NEXT: movups 32(%rdi), %xmm2574; SSE-NEXT: movups 48(%rdi), %xmm3575; SSE-NEXT: retq576;577; AVXONLY-LABEL: test_v64i8_unaligned:578; AVXONLY: # %bb.0: # %entry579; AVXONLY-NEXT: vmovups (%rdi), %ymm0580; AVXONLY-NEXT: vmovups 32(%rdi), %ymm1581; AVXONLY-NEXT: retq582;583; AVX512-LABEL: test_v64i8_unaligned:584; AVX512: # %bb.0: # %entry585; AVX512-NEXT: vmovdqu64 (%rdi), %zmm0586; AVX512-NEXT: retq587entry:588 %0 = load <64 x i8>, ptr %V, align 4589 ret <64 x i8> %0590}591 592define <32 x i16> @test_v32i16_unaligned(ptr %V) {593; SSE-LABEL: test_v32i16_unaligned:594; SSE: # %bb.0: # %entry595; SSE-NEXT: movups (%rdi), %xmm0596; SSE-NEXT: movups 16(%rdi), %xmm1597; SSE-NEXT: movups 32(%rdi), %xmm2598; SSE-NEXT: movups 48(%rdi), %xmm3599; SSE-NEXT: retq600;601; AVXONLY-LABEL: test_v32i16_unaligned:602; AVXONLY: # %bb.0: # %entry603; AVXONLY-NEXT: vmovups (%rdi), %ymm0604; AVXONLY-NEXT: vmovups 32(%rdi), %ymm1605; AVXONLY-NEXT: retq606;607; AVX512-LABEL: test_v32i16_unaligned:608; AVX512: # %bb.0: # %entry609; AVX512-NEXT: vmovdqu64 (%rdi), %zmm0610; AVX512-NEXT: retq611entry:612 %0 = load <32 x i16>, ptr %V, align 4613 ret <32 x i16> %0614}615 616define <16 x i32> @test_v16i32_unaligned(ptr %V) {617; SSE-LABEL: test_v16i32_unaligned:618; SSE: # %bb.0: # %entry619; SSE-NEXT: movups (%rdi), %xmm0620; SSE-NEXT: movups 16(%rdi), %xmm1621; SSE-NEXT: movups 32(%rdi), %xmm2622; SSE-NEXT: movups 48(%rdi), %xmm3623; SSE-NEXT: retq624;625; AVXONLY-LABEL: test_v16i32_unaligned:626; AVXONLY: # %bb.0: # %entry627; AVXONLY-NEXT: vmovups (%rdi), %ymm0628; AVXONLY-NEXT: vmovups 32(%rdi), %ymm1629; AVXONLY-NEXT: retq630;631; AVX512-LABEL: test_v16i32_unaligned:632; AVX512: # %bb.0: # %entry633; AVX512-NEXT: vmovdqu64 (%rdi), %zmm0634; AVX512-NEXT: retq635entry:636 %0 = load <16 x i32>, ptr %V, align 4637 ret <16 x i32> %0638}639 640define <8 x i64> @test_v8i64_unaligned(ptr %V) {641; SSE-LABEL: test_v8i64_unaligned:642; SSE: # %bb.0: # %entry643; SSE-NEXT: movups (%rdi), %xmm0644; SSE-NEXT: movups 16(%rdi), %xmm1645; SSE-NEXT: movups 32(%rdi), %xmm2646; SSE-NEXT: movups 48(%rdi), %xmm3647; SSE-NEXT: retq648;649; AVXONLY-LABEL: test_v8i64_unaligned:650; AVXONLY: # %bb.0: # %entry651; AVXONLY-NEXT: vmovups (%rdi), %ymm0652; AVXONLY-NEXT: vmovups 32(%rdi), %ymm1653; AVXONLY-NEXT: retq654;655; AVX512-LABEL: test_v8i64_unaligned:656; AVX512: # %bb.0: # %entry657; AVX512-NEXT: vmovdqu64 (%rdi), %zmm0658; AVX512-NEXT: retq659entry:660 %0 = load <8 x i64>, ptr %V, align 4661 ret <8 x i64> %0662}663 664define <8 x float> @test_v16f32(ptr %V) {665; SSE-LABEL: test_v16f32:666; SSE: # %bb.0: # %entry667; SSE-NEXT: movaps (%rdi), %xmm0668; SSE-NEXT: movaps 16(%rdi), %xmm1669; SSE-NEXT: retq670;671; AVX-LABEL: test_v16f32:672; AVX: # %bb.0: # %entry673; AVX-NEXT: vmovaps (%rdi), %ymm0674; AVX-NEXT: retq675entry:676 %0 = load <8 x float>, ptr %V, align 64677 ret <8 x float> %0678}679 680define <8 x double> @test_v8f64(ptr %V) {681; SSE-LABEL: test_v8f64:682; SSE: # %bb.0: # %entry683; SSE-NEXT: movapd (%rdi), %xmm0684; SSE-NEXT: movapd 16(%rdi), %xmm1685; SSE-NEXT: movapd 32(%rdi), %xmm2686; SSE-NEXT: movapd 48(%rdi), %xmm3687; SSE-NEXT: retq688;689; AVXONLY-LABEL: test_v8f64:690; AVXONLY: # %bb.0: # %entry691; AVXONLY-NEXT: vmovapd (%rdi), %ymm0692; AVXONLY-NEXT: vmovapd 32(%rdi), %ymm1693; AVXONLY-NEXT: retq694;695; AVX512-LABEL: test_v8f64:696; AVX512: # %bb.0: # %entry697; AVX512-NEXT: vmovapd (%rdi), %zmm0698; AVX512-NEXT: retq699entry:700 %0 = load <8 x double>, ptr %V, align 64701 ret <8 x double> %0702}703 704define <16 x float> @test_v16f32_unaligned(ptr %V) {705; SSE-LABEL: test_v16f32_unaligned:706; SSE: # %bb.0: # %entry707; SSE-NEXT: movups (%rdi), %xmm0708; SSE-NEXT: movups 16(%rdi), %xmm1709; SSE-NEXT: movups 32(%rdi), %xmm2710; SSE-NEXT: movups 48(%rdi), %xmm3711; SSE-NEXT: retq712;713; AVXONLY-LABEL: test_v16f32_unaligned:714; AVXONLY: # %bb.0: # %entry715; AVXONLY-NEXT: vmovups (%rdi), %ymm0716; AVXONLY-NEXT: vmovups 32(%rdi), %ymm1717; AVXONLY-NEXT: retq718;719; AVX512-LABEL: test_v16f32_unaligned:720; AVX512: # %bb.0: # %entry721; AVX512-NEXT: vmovups (%rdi), %zmm0722; AVX512-NEXT: retq723entry:724 %0 = load <16 x float>, ptr %V, align 4725 ret <16 x float> %0726}727 728define <8 x double> @test_v8f64_unaligned(ptr %V) {729; SSE-LABEL: test_v8f64_unaligned:730; SSE: # %bb.0: # %entry731; SSE-NEXT: movupd (%rdi), %xmm0732; SSE-NEXT: movupd 16(%rdi), %xmm1733; SSE-NEXT: movupd 32(%rdi), %xmm2734; SSE-NEXT: movupd 48(%rdi), %xmm3735; SSE-NEXT: retq736;737; AVXONLY-LABEL: test_v8f64_unaligned:738; AVXONLY: # %bb.0: # %entry739; AVXONLY-NEXT: vmovupd (%rdi), %ymm0740; AVXONLY-NEXT: vmovupd 32(%rdi), %ymm1741; AVXONLY-NEXT: retq742;743; AVX512-LABEL: test_v8f64_unaligned:744; AVX512: # %bb.0: # %entry745; AVX512-NEXT: vmovupd (%rdi), %zmm0746; AVX512-NEXT: retq747entry:748 %0 = load <8 x double>, ptr %V, align 4749 ret <8 x double> %0750}751 752