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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s -check-prefixes=SSE,SSE-MOV,SSE23; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s -check-prefixes=SSE,SSE4,SSE4-BLEND4; RUN: llc < %s -mtriple=x86_64-- -mcpu=slm | FileCheck %s -check-prefixes=SSE,SSE-MOV,SSE4,SSE4-MOV5 6; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s -check-prefixes=AVX,AVX1,AVX-BLEND,AVX1-BLEND7; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s -check-prefixes=AVX,AVX1,AVX-MOV,AVX1-MOV8; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s -check-prefixes=AVX,AVX2,AVX-BLEND,AVX2-BLEND9; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s -check-prefixes=AVX,AVX2,AVX-BLEND,AVX2-BLEND10; RUN: llc < %s -mtriple=x86_64-- -mcpu=alderlake | FileCheck %s -check-prefixes=AVX,AVX2,AVX-MOV,AVX2-MOV11 12;13; v2f64 patterns14;15 16define <2 x double> @test_v2f64_blend_movsd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {17; SSE-MOV-LABEL: test_v2f64_blend_movsd:18; SSE-MOV: # %bb.0:19; SSE-MOV-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]20; SSE-MOV-NEXT: addpd %xmm2, %xmm021; SSE-MOV-NEXT: retq22;23; SSE4-BLEND-LABEL: test_v2f64_blend_movsd:24; SSE4-BLEND: # %bb.0:25; SSE4-BLEND-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]26; SSE4-BLEND-NEXT: addpd %xmm2, %xmm027; SSE4-BLEND-NEXT: retq28;29; AVX-BLEND-LABEL: test_v2f64_blend_movsd:30; AVX-BLEND: # %bb.0:31; AVX-BLEND-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]32; AVX-BLEND-NEXT: vaddpd %xmm2, %xmm0, %xmm033; AVX-BLEND-NEXT: retq34;35; AVX-MOV-LABEL: test_v2f64_blend_movsd:36; AVX-MOV: # %bb.0:37; AVX-MOV-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]38; AVX-MOV-NEXT: vaddpd %xmm2, %xmm0, %xmm039; AVX-MOV-NEXT: retq40 %s = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 2, i32 1>41 %r = fadd <2 x double> %s, %a242 ret <2 x double> %r43}44 45define <2 x double> @test_v2f64_blend_movsd_optsize(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) optsize {46; SSE-LABEL: test_v2f64_blend_movsd_optsize:47; SSE: # %bb.0:48; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]49; SSE-NEXT: addpd %xmm2, %xmm050; SSE-NEXT: retq51;52; AVX-LABEL: test_v2f64_blend_movsd_optsize:53; AVX: # %bb.0:54; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]55; AVX-NEXT: vaddpd %xmm2, %xmm0, %xmm056; AVX-NEXT: retq57 %s = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 2, i32 1>58 %r = fadd <2 x double> %s, %a259 ret <2 x double> %r60}61 62define <2 x double> @test_v2f64_blend_movsd_load(ptr %p0, <2 x double> %a1, <2 x double> %a2) {63; SSE2-LABEL: test_v2f64_blend_movsd_load:64; SSE2: # %bb.0:65; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1]66; SSE2-NEXT: addpd %xmm1, %xmm067; SSE2-NEXT: retq68;69; SSE4-LABEL: test_v2f64_blend_movsd_load:70; SSE4: # %bb.0:71; SSE4-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],mem[1]72; SSE4-NEXT: addpd %xmm1, %xmm073; SSE4-NEXT: retq74;75; AVX-LABEL: test_v2f64_blend_movsd_load:76; AVX: # %bb.0:77; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1]78; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm079; AVX-NEXT: retq80 %a0 = load <2 x double>, ptr %p081 %s = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 2, i32 1>82 %r = fadd <2 x double> %s, %a283 ret <2 x double> %r84}85 86define <2 x double> @test_v2f64_blend_movsd_load_commute(<2 x double> %a0, ptr %p1, <2 x double> %a2) {87; SSE2-LABEL: test_v2f64_blend_movsd_load_commute:88; SSE2: # %bb.0:89; SSE2-NEXT: movlpd {{.*#+}} xmm0 = mem[0],xmm0[1]90; SSE2-NEXT: addpd %xmm1, %xmm091; SSE2-NEXT: retq92;93; SSE4-LABEL: test_v2f64_blend_movsd_load_commute:94; SSE4: # %bb.0:95; SSE4-NEXT: blendpd {{.*#+}} xmm0 = mem[0],xmm0[1]96; SSE4-NEXT: addpd %xmm1, %xmm097; SSE4-NEXT: retq98;99; AVX-LABEL: test_v2f64_blend_movsd_load_commute:100; AVX: # %bb.0:101; AVX-NEXT: vblendpd {{.*#+}} xmm0 = mem[0],xmm0[1]102; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0103; AVX-NEXT: retq104 %a1 = load <2 x double>, ptr %p1105 %s = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 2, i32 1>106 %r = fadd <2 x double> %s, %a2107 ret <2 x double> %r108}109 110define <2 x double> @test_v2f64_blend_movsd_zero(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {111; SSE-MOV-LABEL: test_v2f64_blend_movsd_zero:112; SSE-MOV: # %bb.0:113; SSE-MOV-NEXT: xorpd %xmm1, %xmm1114; SSE-MOV-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]115; SSE-MOV-NEXT: addpd %xmm2, %xmm0116; SSE-MOV-NEXT: retq117;118; SSE4-BLEND-LABEL: test_v2f64_blend_movsd_zero:119; SSE4-BLEND: # %bb.0:120; SSE4-BLEND-NEXT: xorpd %xmm1, %xmm1121; SSE4-BLEND-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]122; SSE4-BLEND-NEXT: addpd %xmm2, %xmm0123; SSE4-BLEND-NEXT: retq124;125; AVX-BLEND-LABEL: test_v2f64_blend_movsd_zero:126; AVX-BLEND: # %bb.0:127; AVX-BLEND-NEXT: vxorpd %xmm1, %xmm1, %xmm1128; AVX-BLEND-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]129; AVX-BLEND-NEXT: vaddpd %xmm2, %xmm0, %xmm0130; AVX-BLEND-NEXT: retq131;132; AVX-MOV-LABEL: test_v2f64_blend_movsd_zero:133; AVX-MOV: # %bb.0:134; AVX-MOV-NEXT: vxorpd %xmm1, %xmm1, %xmm1135; AVX-MOV-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]136; AVX-MOV-NEXT: vaddpd %xmm2, %xmm0, %xmm0137; AVX-MOV-NEXT: retq138 %s = shufflevector <2 x double> %a0, <2 x double> zeroinitializer, <2 x i32> <i32 2, i32 1>139 %r = fadd <2 x double> %s, %a2140 ret <2 x double> %r141}142 143;144; v2i64 patterns145;146 147define <2 x i64> @test_v2i64_blend_movsd(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {148; SSE2-LABEL: test_v2i64_blend_movsd:149; SSE2: # %bb.0:150; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]151; SSE2-NEXT: paddq %xmm2, %xmm0152; SSE2-NEXT: retq153;154; SSE4-LABEL: test_v2i64_blend_movsd:155; SSE4: # %bb.0:156; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]157; SSE4-NEXT: paddq %xmm2, %xmm0158; SSE4-NEXT: retq159;160; AVX1-LABEL: test_v2i64_blend_movsd:161; AVX1: # %bb.0:162; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]163; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0164; AVX1-NEXT: retq165;166; AVX2-LABEL: test_v2i64_blend_movsd:167; AVX2: # %bb.0:168; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]169; AVX2-NEXT: vpaddq %xmm2, %xmm0, %xmm0170; AVX2-NEXT: retq171 %s = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 2, i32 1>172 %r = add <2 x i64> %s, %a2173 ret <2 x i64> %r174}175 176define <2 x i64> @test_v2i64_blend_movsd_optsize(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) optsize {177; SSE2-LABEL: test_v2i64_blend_movsd_optsize:178; SSE2: # %bb.0:179; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]180; SSE2-NEXT: paddq %xmm2, %xmm0181; SSE2-NEXT: retq182;183; SSE4-LABEL: test_v2i64_blend_movsd_optsize:184; SSE4: # %bb.0:185; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]186; SSE4-NEXT: paddq %xmm2, %xmm0187; SSE4-NEXT: retq188;189; AVX1-LABEL: test_v2i64_blend_movsd_optsize:190; AVX1: # %bb.0:191; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]192; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0193; AVX1-NEXT: retq194;195; AVX2-LABEL: test_v2i64_blend_movsd_optsize:196; AVX2: # %bb.0:197; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]198; AVX2-NEXT: vpaddq %xmm2, %xmm0, %xmm0199; AVX2-NEXT: retq200 %s = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 2, i32 1>201 %r = add <2 x i64> %s, %a2202 ret <2 x i64> %r203}204 205define <2 x i64> @test_v2i64_blend_movsd_load(ptr %p0, <2 x i64> %a1, <2 x i64> %a2) {206; SSE2-LABEL: test_v2i64_blend_movsd_load:207; SSE2: # %bb.0:208; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1]209; SSE2-NEXT: paddq %xmm1, %xmm0210; SSE2-NEXT: retq211;212; SSE4-LABEL: test_v2i64_blend_movsd_load:213; SSE4: # %bb.0:214; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],mem[4,5,6,7]215; SSE4-NEXT: paddq %xmm1, %xmm0216; SSE4-NEXT: retq217;218; AVX1-LABEL: test_v2i64_blend_movsd_load:219; AVX1: # %bb.0:220; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],mem[4,5,6,7]221; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0222; AVX1-NEXT: retq223;224; AVX2-LABEL: test_v2i64_blend_movsd_load:225; AVX2: # %bb.0:226; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]227; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0228; AVX2-NEXT: retq229 %a0 = load <2 x i64>, ptr %p0230 %s = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 2, i32 1>231 %r = add <2 x i64> %s, %a2232 ret <2 x i64> %r233}234 235define <2 x i64> @test_v2i64_blend_movsd_load_commute(<2 x i64> %a0, ptr %p1, <2 x i64> %a2) {236; SSE2-LABEL: test_v2i64_blend_movsd_load_commute:237; SSE2: # %bb.0:238; SSE2-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]239; SSE2-NEXT: paddq %xmm1, %xmm0240; SSE2-NEXT: retq241;242; SSE4-LABEL: test_v2i64_blend_movsd_load_commute:243; SSE4: # %bb.0:244; SSE4-NEXT: pblendw {{.*#+}} xmm0 = mem[0,1,2,3],xmm0[4,5,6,7]245; SSE4-NEXT: paddq %xmm1, %xmm0246; SSE4-NEXT: retq247;248; AVX1-LABEL: test_v2i64_blend_movsd_load_commute:249; AVX1: # %bb.0:250; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = mem[0,1,2,3],xmm0[4,5,6,7]251; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0252; AVX1-NEXT: retq253;254; AVX2-LABEL: test_v2i64_blend_movsd_load_commute:255; AVX2: # %bb.0:256; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]257; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0258; AVX2-NEXT: retq259 %a1 = load <2 x i64>, ptr %p1260 %s = shufflevector <2 x i64> %a0, <2 x i64> %a1, <2 x i32> <i32 2, i32 1>261 %r = add <2 x i64> %s, %a2262 ret <2 x i64> %r263}264 265define <2 x i64> @test_v2i64_blend_movsd_zero(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) {266; SSE2-LABEL: test_v2i64_blend_movsd_zero:267; SSE2: # %bb.0:268; SSE2-NEXT: pxor %xmm1, %xmm1269; SSE2-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]270; SSE2-NEXT: paddq %xmm2, %xmm1271; SSE2-NEXT: movdqa %xmm1, %xmm0272; SSE2-NEXT: retq273;274; SSE4-LABEL: test_v2i64_blend_movsd_zero:275; SSE4: # %bb.0:276; SSE4-NEXT: pxor %xmm1, %xmm1277; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]278; SSE4-NEXT: paddq %xmm2, %xmm0279; SSE4-NEXT: retq280;281; AVX1-LABEL: test_v2i64_blend_movsd_zero:282; AVX1: # %bb.0:283; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1284; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]285; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0286; AVX1-NEXT: retq287;288; AVX2-LABEL: test_v2i64_blend_movsd_zero:289; AVX2: # %bb.0:290; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1291; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]292; AVX2-NEXT: vpaddq %xmm2, %xmm0, %xmm0293; AVX2-NEXT: retq294 %s = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <2 x i32> <i32 2, i32 1>295 %r = add <2 x i64> %s, %a2296 ret <2 x i64> %r297}298 299;300; v4f32 patterns301;302 303define <4 x float> @test_v4f32_blend_movss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {304; SSE-MOV-LABEL: test_v4f32_blend_movss:305; SSE-MOV: # %bb.0:306; SSE-MOV-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]307; SSE-MOV-NEXT: addps %xmm2, %xmm0308; SSE-MOV-NEXT: retq309;310; SSE4-BLEND-LABEL: test_v4f32_blend_movss:311; SSE4-BLEND: # %bb.0:312; SSE4-BLEND-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]313; SSE4-BLEND-NEXT: addps %xmm2, %xmm0314; SSE4-BLEND-NEXT: retq315;316; AVX-BLEND-LABEL: test_v4f32_blend_movss:317; AVX-BLEND: # %bb.0:318; AVX-BLEND-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]319; AVX-BLEND-NEXT: vaddps %xmm2, %xmm0, %xmm0320; AVX-BLEND-NEXT: retq321;322; AVX-MOV-LABEL: test_v4f32_blend_movss:323; AVX-MOV: # %bb.0:324; AVX-MOV-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]325; AVX-MOV-NEXT: vaddps %xmm2, %xmm0, %xmm0326; AVX-MOV-NEXT: retq327 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>328 %r = fadd <4 x float> %s, %a2329 ret <4 x float> %r330}331 332define <4 x float> @test_v4f32_blend_movsd(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {333; SSE-MOV-LABEL: test_v4f32_blend_movsd:334; SSE-MOV: # %bb.0:335; SSE-MOV-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]336; SSE-MOV-NEXT: addps %xmm2, %xmm0337; SSE-MOV-NEXT: retq338;339; SSE4-BLEND-LABEL: test_v4f32_blend_movsd:340; SSE4-BLEND: # %bb.0:341; SSE4-BLEND-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]342; SSE4-BLEND-NEXT: addps %xmm2, %xmm0343; SSE4-BLEND-NEXT: retq344;345; AVX-BLEND-LABEL: test_v4f32_blend_movsd:346; AVX-BLEND: # %bb.0:347; AVX-BLEND-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]348; AVX-BLEND-NEXT: vaddps %xmm2, %xmm0, %xmm0349; AVX-BLEND-NEXT: retq350;351; AVX-MOV-LABEL: test_v4f32_blend_movsd:352; AVX-MOV: # %bb.0:353; AVX-MOV-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]354; AVX-MOV-NEXT: vaddps %xmm2, %xmm0, %xmm0355; AVX-MOV-NEXT: retq356 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>357 %r = fadd <4 x float> %s, %a2358 ret <4 x float> %r359}360 361define <4 x float> @test_v4f32_blend_movss_optsize(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) optsize {362; SSE-LABEL: test_v4f32_blend_movss_optsize:363; SSE: # %bb.0:364; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]365; SSE-NEXT: addps %xmm2, %xmm0366; SSE-NEXT: retq367;368; AVX-LABEL: test_v4f32_blend_movss_optsize:369; AVX: # %bb.0:370; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]371; AVX-NEXT: vaddps %xmm2, %xmm0, %xmm0372; AVX-NEXT: retq373 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>374 %r = fadd <4 x float> %s, %a2375 ret <4 x float> %r376}377 378define <4 x float> @test_v4f32_blend_movsd_optsize(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) optsize {379; SSE-LABEL: test_v4f32_blend_movsd_optsize:380; SSE: # %bb.0:381; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]382; SSE-NEXT: addps %xmm2, %xmm0383; SSE-NEXT: retq384;385; AVX-LABEL: test_v4f32_blend_movsd_optsize:386; AVX: # %bb.0:387; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]388; AVX-NEXT: vaddps %xmm2, %xmm0, %xmm0389; AVX-NEXT: retq390 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>391 %r = fadd <4 x float> %s, %a2392 ret <4 x float> %r393}394 395define <4 x float> @test_v4f32_blend_movss_load(ptr %p0, <4 x float> %a1, <4 x float> %a2) {396; SSE2-LABEL: test_v4f32_blend_movss_load:397; SSE2: # %bb.0:398; SSE2-NEXT: movaps (%rdi), %xmm2399; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]400; SSE2-NEXT: addps %xmm1, %xmm2401; SSE2-NEXT: movaps %xmm2, %xmm0402; SSE2-NEXT: retq403;404; SSE4-LABEL: test_v4f32_blend_movss_load:405; SSE4: # %bb.0:406; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]407; SSE4-NEXT: addps %xmm1, %xmm0408; SSE4-NEXT: retq409;410; AVX-LABEL: test_v4f32_blend_movss_load:411; AVX: # %bb.0:412; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]413; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0414; AVX-NEXT: retq415 %a0 = load <4 x float>, ptr %p0416 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>417 %r = fadd <4 x float> %s, %a2418 ret <4 x float> %r419}420 421define <4 x float> @test_v4f32_blend_movss_load_commute(<4 x float> %a0, ptr %p1, <4 x float> %a2) {422; SSE2-LABEL: test_v4f32_blend_movss_load_commute:423; SSE2: # %bb.0:424; SSE2-NEXT: movaps (%rdi), %xmm2425; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]426; SSE2-NEXT: addps %xmm1, %xmm0427; SSE2-NEXT: retq428;429; SSE4-LABEL: test_v4f32_blend_movss_load_commute:430; SSE4: # %bb.0:431; SSE4-NEXT: blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]432; SSE4-NEXT: addps %xmm1, %xmm0433; SSE4-NEXT: retq434;435; AVX-LABEL: test_v4f32_blend_movss_load_commute:436; AVX: # %bb.0:437; AVX-NEXT: vblendps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]438; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0439; AVX-NEXT: retq440 %a1 = load <4 x float>, ptr %p1441 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>442 %r = fadd <4 x float> %s, %a2443 ret <4 x float> %r444}445 446define <4 x float> @test_v4f32_blend_movsd_load(ptr %p0, <4 x float> %a1, <4 x float> %a2) {447; SSE2-LABEL: test_v4f32_blend_movsd_load:448; SSE2: # %bb.0:449; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1]450; SSE2-NEXT: addps %xmm1, %xmm0451; SSE2-NEXT: retq452;453; SSE4-LABEL: test_v4f32_blend_movsd_load:454; SSE4: # %bb.0:455; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]456; SSE4-NEXT: addps %xmm1, %xmm0457; SSE4-NEXT: retq458;459; AVX-LABEL: test_v4f32_blend_movsd_load:460; AVX: # %bb.0:461; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]462; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0463; AVX-NEXT: retq464 %a0 = load <4 x float>, ptr %p0465 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>466 %r = fadd <4 x float> %s, %a2467 ret <4 x float> %r468}469 470define <4 x float> @test_v4f32_blend_movsd_load_commute(<4 x float> %a0, ptr %p1, <4 x float> %a2) {471; SSE2-LABEL: test_v4f32_blend_movsd_load_commute:472; SSE2: # %bb.0:473; SSE2-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]474; SSE2-NEXT: addps %xmm1, %xmm0475; SSE2-NEXT: retq476;477; SSE4-LABEL: test_v4f32_blend_movsd_load_commute:478; SSE4: # %bb.0:479; SSE4-NEXT: blendps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]480; SSE4-NEXT: addps %xmm1, %xmm0481; SSE4-NEXT: retq482;483; AVX-LABEL: test_v4f32_blend_movsd_load_commute:484; AVX: # %bb.0:485; AVX-NEXT: vblendps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]486; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0487; AVX-NEXT: retq488 %a1 = load <4 x float>, ptr %p1489 %s = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>490 %r = fadd <4 x float> %s, %a2491 ret <4 x float> %r492}493 494define <4 x float> @test_v4f32_blend_movss_zero(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {495; SSE-MOV-LABEL: test_v4f32_blend_movss_zero:496; SSE-MOV: # %bb.0:497; SSE-MOV-NEXT: xorps %xmm1, %xmm1498; SSE-MOV-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]499; SSE-MOV-NEXT: addps %xmm2, %xmm0500; SSE-MOV-NEXT: retq501;502; SSE4-BLEND-LABEL: test_v4f32_blend_movss_zero:503; SSE4-BLEND: # %bb.0:504; SSE4-BLEND-NEXT: xorps %xmm1, %xmm1505; SSE4-BLEND-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]506; SSE4-BLEND-NEXT: addps %xmm2, %xmm0507; SSE4-BLEND-NEXT: retq508;509; AVX-BLEND-LABEL: test_v4f32_blend_movss_zero:510; AVX-BLEND: # %bb.0:511; AVX-BLEND-NEXT: vxorps %xmm1, %xmm1, %xmm1512; AVX-BLEND-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]513; AVX-BLEND-NEXT: vaddps %xmm2, %xmm0, %xmm0514; AVX-BLEND-NEXT: retq515;516; AVX-MOV-LABEL: test_v4f32_blend_movss_zero:517; AVX-MOV: # %bb.0:518; AVX-MOV-NEXT: vxorps %xmm1, %xmm1, %xmm1519; AVX-MOV-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]520; AVX-MOV-NEXT: vaddps %xmm2, %xmm0, %xmm0521; AVX-MOV-NEXT: retq522 %s = shufflevector <4 x float> %a0, <4 x float> zeroinitializer, <4 x i32> <i32 4, i32 1, i32 2, i32 3>523 %r = fadd <4 x float> %s, %a2524 ret <4 x float> %r525}526 527define <4 x float> @test_v4f32_blend_movsd_zero(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {528; SSE2-LABEL: test_v4f32_blend_movsd_zero:529; SSE2: # %bb.0:530; SSE2-NEXT: xorpd %xmm1, %xmm1531; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]532; SSE2-NEXT: addps %xmm2, %xmm0533; SSE2-NEXT: retq534;535; SSE4-BLEND-LABEL: test_v4f32_blend_movsd_zero:536; SSE4-BLEND: # %bb.0:537; SSE4-BLEND-NEXT: xorps %xmm1, %xmm1538; SSE4-BLEND-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]539; SSE4-BLEND-NEXT: addps %xmm2, %xmm0540; SSE4-BLEND-NEXT: retq541;542; SSE4-MOV-LABEL: test_v4f32_blend_movsd_zero:543; SSE4-MOV: # %bb.0:544; SSE4-MOV-NEXT: xorps %xmm1, %xmm1545; SSE4-MOV-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]546; SSE4-MOV-NEXT: addps %xmm2, %xmm0547; SSE4-MOV-NEXT: retq548;549; AVX-BLEND-LABEL: test_v4f32_blend_movsd_zero:550; AVX-BLEND: # %bb.0:551; AVX-BLEND-NEXT: vxorps %xmm1, %xmm1, %xmm1552; AVX-BLEND-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]553; AVX-BLEND-NEXT: vaddps %xmm2, %xmm0, %xmm0554; AVX-BLEND-NEXT: retq555;556; AVX-MOV-LABEL: test_v4f32_blend_movsd_zero:557; AVX-MOV: # %bb.0:558; AVX-MOV-NEXT: vxorps %xmm1, %xmm1, %xmm1559; AVX-MOV-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]560; AVX-MOV-NEXT: vaddps %xmm2, %xmm0, %xmm0561; AVX-MOV-NEXT: retq562 %s = shufflevector <4 x float> %a0, <4 x float> zeroinitializer, <4 x i32> <i32 4, i32 5, i32 2, i32 3>563 %r = fadd <4 x float> %s, %a2564 ret <4 x float> %r565}566 567;568; v4i32 patterns569;570 571define <4 x i32> @test_v4i32_blend_movss(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {572; SSE2-LABEL: test_v4i32_blend_movss:573; SSE2: # %bb.0:574; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]575; SSE2-NEXT: paddd %xmm2, %xmm0576; SSE2-NEXT: retq577;578; SSE4-LABEL: test_v4i32_blend_movss:579; SSE4: # %bb.0:580; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]581; SSE4-NEXT: paddd %xmm2, %xmm0582; SSE4-NEXT: retq583;584; AVX1-LABEL: test_v4i32_blend_movss:585; AVX1: # %bb.0:586; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]587; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0588; AVX1-NEXT: retq589;590; AVX2-LABEL: test_v4i32_blend_movss:591; AVX2: # %bb.0:592; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]593; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm0594; AVX2-NEXT: retq595 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>596 %r = add <4 x i32> %s, %a2597 ret <4 x i32> %r598}599 600define <4 x i32> @test_v4i32_blend_movsd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {601; SSE2-LABEL: test_v4i32_blend_movsd:602; SSE2: # %bb.0:603; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]604; SSE2-NEXT: paddd %xmm2, %xmm0605; SSE2-NEXT: retq606;607; SSE4-LABEL: test_v4i32_blend_movsd:608; SSE4: # %bb.0:609; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]610; SSE4-NEXT: paddd %xmm2, %xmm0611; SSE4-NEXT: retq612;613; AVX1-LABEL: test_v4i32_blend_movsd:614; AVX1: # %bb.0:615; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]616; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0617; AVX1-NEXT: retq618;619; AVX2-LABEL: test_v4i32_blend_movsd:620; AVX2: # %bb.0:621; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]622; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm0623; AVX2-NEXT: retq624 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>625 %r = add <4 x i32> %s, %a2626 ret <4 x i32> %r627}628 629define <4 x i32> @test_v4i32_blend_movss_optsize(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) optsize {630; SSE2-LABEL: test_v4i32_blend_movss_optsize:631; SSE2: # %bb.0:632; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]633; SSE2-NEXT: paddd %xmm2, %xmm0634; SSE2-NEXT: retq635;636; SSE4-LABEL: test_v4i32_blend_movss_optsize:637; SSE4: # %bb.0:638; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]639; SSE4-NEXT: paddd %xmm2, %xmm0640; SSE4-NEXT: retq641;642; AVX1-LABEL: test_v4i32_blend_movss_optsize:643; AVX1: # %bb.0:644; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]645; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0646; AVX1-NEXT: retq647;648; AVX2-LABEL: test_v4i32_blend_movss_optsize:649; AVX2: # %bb.0:650; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]651; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm0652; AVX2-NEXT: retq653 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>654 %r = add <4 x i32> %s, %a2655 ret <4 x i32> %r656}657 658define <4 x i32> @test_v4i32_blend_movsd_optsize(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) optsize {659; SSE2-LABEL: test_v4i32_blend_movsd_optsize:660; SSE2: # %bb.0:661; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]662; SSE2-NEXT: paddd %xmm2, %xmm0663; SSE2-NEXT: retq664;665; SSE4-LABEL: test_v4i32_blend_movsd_optsize:666; SSE4: # %bb.0:667; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]668; SSE4-NEXT: paddd %xmm2, %xmm0669; SSE4-NEXT: retq670;671; AVX1-LABEL: test_v4i32_blend_movsd_optsize:672; AVX1: # %bb.0:673; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]674; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0675; AVX1-NEXT: retq676;677; AVX2-LABEL: test_v4i32_blend_movsd_optsize:678; AVX2: # %bb.0:679; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]680; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm0681; AVX2-NEXT: retq682 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>683 %r = add <4 x i32> %s, %a2684 ret <4 x i32> %r685}686 687define <4 x i32> @test_v4i32_blend_movss_load(ptr %p0, <4 x i32> %a1, <4 x i32> %a2) {688; SSE2-LABEL: test_v4i32_blend_movss_load:689; SSE2: # %bb.0:690; SSE2-NEXT: movaps (%rdi), %xmm2691; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]692; SSE2-NEXT: paddd %xmm1, %xmm2693; SSE2-NEXT: movdqa %xmm2, %xmm0694; SSE2-NEXT: retq695;696; SSE4-LABEL: test_v4i32_blend_movss_load:697; SSE4: # %bb.0:698; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3,4,5,6,7]699; SSE4-NEXT: paddd %xmm1, %xmm0700; SSE4-NEXT: retq701;702; AVX1-LABEL: test_v4i32_blend_movss_load:703; AVX1: # %bb.0:704; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3,4,5,6,7]705; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0706; AVX1-NEXT: retq707;708; AVX2-LABEL: test_v4i32_blend_movss_load:709; AVX2: # %bb.0:710; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]711; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0712; AVX2-NEXT: retq713 %a0 = load <4 x i32>, ptr %p0714 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>715 %r = add <4 x i32> %s, %a2716 ret <4 x i32> %r717}718 719define <4 x i32> @test_v4i32_blend_movss_load_commute(<4 x i32> %a0, ptr %p1, <4 x i32> %a2) {720; SSE2-LABEL: test_v4i32_blend_movss_load_commute:721; SSE2: # %bb.0:722; SSE2-NEXT: movaps (%rdi), %xmm2723; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]724; SSE2-NEXT: paddd %xmm1, %xmm0725; SSE2-NEXT: retq726;727; SSE4-LABEL: test_v4i32_blend_movss_load_commute:728; SSE4: # %bb.0:729; SSE4-NEXT: pblendw {{.*#+}} xmm0 = mem[0,1],xmm0[2,3,4,5,6,7]730; SSE4-NEXT: paddd %xmm1, %xmm0731; SSE4-NEXT: retq732;733; AVX1-LABEL: test_v4i32_blend_movss_load_commute:734; AVX1: # %bb.0:735; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = mem[0,1],xmm0[2,3,4,5,6,7]736; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0737; AVX1-NEXT: retq738;739; AVX2-LABEL: test_v4i32_blend_movss_load_commute:740; AVX2: # %bb.0:741; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]742; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0743; AVX2-NEXT: retq744 %a1 = load <4 x i32>, ptr %p1745 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 1, i32 2, i32 3>746 %r = add <4 x i32> %s, %a2747 ret <4 x i32> %r748}749 750define <4 x i32> @test_v4i32_blend_movsd_load(ptr %p0, <4 x i32> %a1, <4 x i32> %a2) {751; SSE2-LABEL: test_v4i32_blend_movsd_load:752; SSE2: # %bb.0:753; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1]754; SSE2-NEXT: paddd %xmm1, %xmm0755; SSE2-NEXT: retq756;757; SSE4-LABEL: test_v4i32_blend_movsd_load:758; SSE4: # %bb.0:759; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],mem[4,5,6,7]760; SSE4-NEXT: paddd %xmm1, %xmm0761; SSE4-NEXT: retq762;763; AVX1-LABEL: test_v4i32_blend_movsd_load:764; AVX1: # %bb.0:765; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],mem[4,5,6,7]766; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0767; AVX1-NEXT: retq768;769; AVX2-LABEL: test_v4i32_blend_movsd_load:770; AVX2: # %bb.0:771; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]772; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0773; AVX2-NEXT: retq774 %a0 = load <4 x i32>, ptr %p0775 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>776 %r = add <4 x i32> %s, %a2777 ret <4 x i32> %r778}779 780define <4 x i32> @test_v4i32_blend_movsd_load_commute(<4 x i32> %a0, ptr %p1, <4 x i32> %a2) {781; SSE2-LABEL: test_v4i32_blend_movsd_load_commute:782; SSE2: # %bb.0:783; SSE2-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]784; SSE2-NEXT: paddd %xmm1, %xmm0785; SSE2-NEXT: retq786;787; SSE4-LABEL: test_v4i32_blend_movsd_load_commute:788; SSE4: # %bb.0:789; SSE4-NEXT: pblendw {{.*#+}} xmm0 = mem[0,1,2,3],xmm0[4,5,6,7]790; SSE4-NEXT: paddd %xmm1, %xmm0791; SSE4-NEXT: retq792;793; AVX1-LABEL: test_v4i32_blend_movsd_load_commute:794; AVX1: # %bb.0:795; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = mem[0,1,2,3],xmm0[4,5,6,7]796; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0797; AVX1-NEXT: retq798;799; AVX2-LABEL: test_v4i32_blend_movsd_load_commute:800; AVX2: # %bb.0:801; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]802; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0803; AVX2-NEXT: retq804 %a1 = load <4 x i32>, ptr %p1805 %s = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>806 %r = add <4 x i32> %s, %a2807 ret <4 x i32> %r808}809 810define <4 x i32> @test_v4i32_blend_movss_zero(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {811; SSE2-LABEL: test_v4i32_blend_movss_zero:812; SSE2: # %bb.0:813; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0814; SSE2-NEXT: paddd %xmm2, %xmm0815; SSE2-NEXT: retq816;817; SSE4-LABEL: test_v4i32_blend_movss_zero:818; SSE4: # %bb.0:819; SSE4-NEXT: pxor %xmm1, %xmm1820; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]821; SSE4-NEXT: paddd %xmm2, %xmm0822; SSE4-NEXT: retq823;824; AVX1-LABEL: test_v4i32_blend_movss_zero:825; AVX1: # %bb.0:826; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1827; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]828; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0829; AVX1-NEXT: retq830;831; AVX2-LABEL: test_v4i32_blend_movss_zero:832; AVX2: # %bb.0:833; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1834; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]835; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm0836; AVX2-NEXT: retq837 %s = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 1, i32 2, i32 3>838 %r = add <4 x i32> %s, %a2839 ret <4 x i32> %r840}841 842define <4 x i32> @test_v4i32_blend_movsd_zero(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {843; SSE2-LABEL: test_v4i32_blend_movsd_zero:844; SSE2: # %bb.0:845; SSE2-NEXT: pxor %xmm1, %xmm1846; SSE2-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]847; SSE2-NEXT: paddd %xmm2, %xmm1848; SSE2-NEXT: movdqa %xmm1, %xmm0849; SSE2-NEXT: retq850;851; SSE4-LABEL: test_v4i32_blend_movsd_zero:852; SSE4: # %bb.0:853; SSE4-NEXT: pxor %xmm1, %xmm1854; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]855; SSE4-NEXT: paddd %xmm2, %xmm0856; SSE4-NEXT: retq857;858; AVX1-LABEL: test_v4i32_blend_movsd_zero:859; AVX1: # %bb.0:860; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1861; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]862; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0863; AVX1-NEXT: retq864;865; AVX2-LABEL: test_v4i32_blend_movsd_zero:866; AVX2: # %bb.0:867; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1868; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]869; AVX2-NEXT: vpaddd %xmm2, %xmm0, %xmm0870; AVX2-NEXT: retq871 %s = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 5, i32 2, i32 3>872 %r = add <4 x i32> %s, %a2873 ret <4 x i32> %r874}875;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:876; AVX1-BLEND: {{.*}}877; AVX1-MOV: {{.*}}878; AVX2-BLEND: {{.*}}879; AVX2-MOV: {{.*}}880