65 lines · plain
1; REQUIRES: asserts2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck %s3 4; This tests the propagation of fast-math-flags from IR instructions to SDNodeFlags.5 6; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_transfer:'7 8; CHECK: t5: f32 = fadd nsz t2, t49; CHECK-NEXT: t6: f32 = fadd arcp t5, t410; CHECK-NEXT: t7: f32 = fadd nnan t6, t411; CHECK-NEXT: t8: f32 = fadd ninf t7, t412; CHECK-NEXT: t9: f32 = fadd contract t8, t413; CHECK-NEXT: t10: f32 = fadd afn t9, t414; CHECK-NEXT: t11: f32 = fadd reassoc t10, t415; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t416 17; CHECK: Optimized lowered selection DAG: %bb.0 'fmf_transfer:'18 19define float @fmf_transfer(float %x, float %y) {20 %f1 = fadd nsz float %x, %y21 %f2 = fadd arcp float %f1, %y22 %f3 = fadd nnan float %f2, %y23 %f4 = fadd ninf float %f3, %y24 %f5 = fadd contract float %f4, %y25 %f6 = fadd afn float %f5, %y26 %f7 = fadd reassoc float %f6, %y27 %f8 = fadd fast float %f7, %y28 ret float %f829}30 31; CHECK-LABEL: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:'32; CHECK: t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setlt:ch33 34define float @fmf_setcc(float %x, float %y) {35 %cmp = fcmp fast ult float %x, 0.036 %ret = select i1 %cmp, float %x, float %y37 ret float %ret38}39 40; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_setcc_canon:'41; CHECK: t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setgt:ch42define float @fmf_setcc_canon(float %x, float %y) {43 %cmp = fcmp fast ult float 0.0, %x44 %ret = select i1 %cmp, float %x, float %y45 ret float %ret46}47 48declare <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i32)49 50; Check that FMF are propagated twice: from IR to x86-specific node and from x86-specific node to generic node.51 52; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_target_intrinsic:'53; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 ninf nsz TargetConstant:i64<{{.*}}>54; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 nsz TargetConstant:i64<{{.*}}>55 56; CHECK-LABEL: Legalized selection DAG: %bb.0 'fmf_target_intrinsic:'57; CHECK: v16f32 = fma ninf nsz t{{.*}}58; CHECK: v16f32 = fma nsz t{{.*}}59 60define <16 x float> @fmf_target_intrinsic(<16 x float> %a, <16 x float> %b, <16 x float> %c) nounwind {61 %t0 = tail call ninf nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i32 4)62 %t1 = tail call nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %t0, <16 x float> %b, <16 x float> %c, i32 4)63 ret <16 x float> %t164}65