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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=fma | FileCheck %s3 4; Propagation of IR FMF should not drop flags when adding the DAG reduction flag.5; This should include an FMA instruction, not separate FMUL/FADD.6 7define double @julia_dotf(<4 x double> %x, <4 x double> %y, <4 x double> %z, i1 %t3) {8; CHECK-LABEL: julia_dotf:9; CHECK: # %bb.0:10; CHECK-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm211; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm112; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm013; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]14; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm015; CHECK-NEXT: vzeroupper16; CHECK-NEXT: retq17 %t1 = fmul contract <4 x double> %x, %y18 %t2 = fadd fast <4 x double> %z, %t119 %rdx.shuf = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>20 %bin.rdx22 = fadd fast <4 x double> %t2, %rdx.shuf21 %rdx.shuf23 = shufflevector <4 x double> %bin.rdx22, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>22 %bin.rdx24 = fadd fast <4 x double> %bin.rdx22, %rdx.shuf2323 %t4 = extractelement <4 x double> %bin.rdx24, i32 024 ret double %t425}26 27