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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s -check-prefixes=CHECK,NOFMA3; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+fma | FileCheck %s -check-prefixes=CHECK,FMA3,FMA3_2564; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+fma,+avx512f | FileCheck %s -check-prefixes=CHECK,FMA3,FMA3_5125; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+fma4 | FileCheck %s -check-prefixes=CHECK,FMA46 7; This test checks the fusing of MUL + SUB/ADD to FMSUBADD.8 9define <2 x double> @mul_subadd_pd128(<2 x double> %A, <2 x double> %B, <2 x double> %C) {10; NOFMA-LABEL: mul_subadd_pd128:11; NOFMA: # %bb.0: # %entry12; NOFMA-NEXT: vmulpd %xmm1, %xmm0, %xmm013; NOFMA-NEXT: vsubpd %xmm2, %xmm0, %xmm114; NOFMA-NEXT: vaddpd %xmm2, %xmm0, %xmm015; NOFMA-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]16; NOFMA-NEXT: retq17;18; FMA3-LABEL: mul_subadd_pd128:19; FMA3: # %bb.0: # %entry20; FMA3-NEXT: vfmsubadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm221; FMA3-NEXT: retq22;23; FMA4-LABEL: mul_subadd_pd128:24; FMA4: # %bb.0: # %entry25; FMA4-NEXT: vfmsubaddpd {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm226; FMA4-NEXT: retq27entry:28 %AB = fmul contract<2 x double> %A, %B29 %Sub = fsub contract<2 x double> %AB, %C30 %Add = fadd contract<2 x double> %AB, %C31 %subadd = shufflevector <2 x double> %Add, <2 x double> %Sub, <2 x i32> <i32 0, i32 3>32 ret <2 x double> %subadd33}34 35define <4 x float> @mul_subadd_ps128(<4 x float> %A, <4 x float> %B, <4 x float> %C) {36; NOFMA-LABEL: mul_subadd_ps128:37; NOFMA: # %bb.0: # %entry38; NOFMA-NEXT: vmulps %xmm1, %xmm0, %xmm039; NOFMA-NEXT: vsubps %xmm2, %xmm0, %xmm140; NOFMA-NEXT: vaddps %xmm2, %xmm0, %xmm041; NOFMA-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]42; NOFMA-NEXT: retq43;44; FMA3-LABEL: mul_subadd_ps128:45; FMA3: # %bb.0: # %entry46; FMA3-NEXT: vfmsubadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm247; FMA3-NEXT: retq48;49; FMA4-LABEL: mul_subadd_ps128:50; FMA4: # %bb.0: # %entry51; FMA4-NEXT: vfmsubaddps {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm252; FMA4-NEXT: retq53entry:54 %AB = fmul contract <4 x float> %A, %B55 %Sub = fsub contract <4 x float> %AB, %C56 %Add = fadd contract <4 x float> %AB, %C57 %subadd = shufflevector <4 x float> %Add, <4 x float> %Sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>58 ret <4 x float> %subadd59}60 61define <4 x double> @mul_subadd_pd256(<4 x double> %A, <4 x double> %B, <4 x double> %C) {62; NOFMA-LABEL: mul_subadd_pd256:63; NOFMA: # %bb.0: # %entry64; NOFMA-NEXT: vmulpd %ymm1, %ymm0, %ymm065; NOFMA-NEXT: vsubpd %ymm2, %ymm0, %ymm166; NOFMA-NEXT: vaddpd %ymm2, %ymm0, %ymm067; NOFMA-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]68; NOFMA-NEXT: retq69;70; FMA3-LABEL: mul_subadd_pd256:71; FMA3: # %bb.0: # %entry72; FMA3-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm273; FMA3-NEXT: retq74;75; FMA4-LABEL: mul_subadd_pd256:76; FMA4: # %bb.0: # %entry77; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm278; FMA4-NEXT: retq79entry:80 %AB = fmul contract <4 x double> %A, %B81 %Sub = fsub contract <4 x double> %AB, %C82 %Add = fadd contract <4 x double> %AB, %C83 %subadd = shufflevector <4 x double> %Add, <4 x double> %Sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>84 ret <4 x double> %subadd85}86 87define <8 x float> @mul_subadd_ps256(<8 x float> %A, <8 x float> %B, <8 x float> %C) {88; NOFMA-LABEL: mul_subadd_ps256:89; NOFMA: # %bb.0: # %entry90; NOFMA-NEXT: vmulps %ymm1, %ymm0, %ymm091; NOFMA-NEXT: vsubps %ymm2, %ymm0, %ymm192; NOFMA-NEXT: vaddps %ymm2, %ymm0, %ymm093; NOFMA-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]94; NOFMA-NEXT: retq95;96; FMA3-LABEL: mul_subadd_ps256:97; FMA3: # %bb.0: # %entry98; FMA3-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm299; FMA3-NEXT: retq100;101; FMA4-LABEL: mul_subadd_ps256:102; FMA4: # %bb.0: # %entry103; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2104; FMA4-NEXT: retq105entry:106 %AB = fmul contract <8 x float> %A, %B107 %Sub = fsub contract <8 x float> %AB, %C108 %Add = fadd contract <8 x float> %AB, %C109 %subadd = shufflevector <8 x float> %Add, <8 x float> %Sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>110 ret <8 x float> %subadd111}112 113define <8 x double> @mul_subadd_pd512(<8 x double> %A, <8 x double> %B, <8 x double> %C) {114; NOFMA-LABEL: mul_subadd_pd512:115; NOFMA: # %bb.0: # %entry116; NOFMA-NEXT: vmulpd %ymm2, %ymm0, %ymm0117; NOFMA-NEXT: vmulpd %ymm3, %ymm1, %ymm1118; NOFMA-NEXT: vsubpd %ymm5, %ymm1, %ymm2119; NOFMA-NEXT: vsubpd %ymm4, %ymm0, %ymm3120; NOFMA-NEXT: vaddpd %ymm5, %ymm1, %ymm1121; NOFMA-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2],ymm2[3]122; NOFMA-NEXT: vaddpd %ymm4, %ymm0, %ymm0123; NOFMA-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm3[1],ymm0[2],ymm3[3]124; NOFMA-NEXT: retq125;126; FMA3_256-LABEL: mul_subadd_pd512:127; FMA3_256: # %bb.0: # %entry128; FMA3_256-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm2 * ymm0) -/+ ymm4129; FMA3_256-NEXT: vfmsubadd213pd {{.*#+}} ymm1 = (ymm3 * ymm1) -/+ ymm5130; FMA3_256-NEXT: retq131;132; FMA3_512-LABEL: mul_subadd_pd512:133; FMA3_512: # %bb.0: # %entry134; FMA3_512-NEXT: vfmsubadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) -/+ zmm2135; FMA3_512-NEXT: retq136;137; FMA4-LABEL: mul_subadd_pd512:138; FMA4: # %bb.0: # %entry139; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm4140; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm1 = (ymm1 * ymm3) -/+ ymm5141; FMA4-NEXT: retq142entry:143 %AB = fmul contract <8 x double> %A, %B144 %Sub = fsub contract <8 x double> %AB, %C145 %Add = fadd contract <8 x double> %AB, %C146 %subadd = shufflevector <8 x double> %Add, <8 x double> %Sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>147 ret <8 x double> %subadd148}149 150define <16 x float> @mul_subadd_ps512(<16 x float> %A, <16 x float> %B, <16 x float> %C) {151; NOFMA-LABEL: mul_subadd_ps512:152; NOFMA: # %bb.0: # %entry153; NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0154; NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1155; NOFMA-NEXT: vsubps %ymm5, %ymm1, %ymm2156; NOFMA-NEXT: vsubps %ymm4, %ymm0, %ymm3157; NOFMA-NEXT: vaddps %ymm5, %ymm1, %ymm1158; NOFMA-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7]159; NOFMA-NEXT: vaddps %ymm4, %ymm0, %ymm0160; NOFMA-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm3[1],ymm0[2],ymm3[3],ymm0[4],ymm3[5],ymm0[6],ymm3[7]161; NOFMA-NEXT: retq162;163; FMA3_256-LABEL: mul_subadd_ps512:164; FMA3_256: # %bb.0: # %entry165; FMA3_256-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm2 * ymm0) -/+ ymm4166; FMA3_256-NEXT: vfmsubadd213ps {{.*#+}} ymm1 = (ymm3 * ymm1) -/+ ymm5167; FMA3_256-NEXT: retq168;169; FMA3_512-LABEL: mul_subadd_ps512:170; FMA3_512: # %bb.0: # %entry171; FMA3_512-NEXT: vfmsubadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) -/+ zmm2172; FMA3_512-NEXT: retq173;174; FMA4-LABEL: mul_subadd_ps512:175; FMA4: # %bb.0: # %entry176; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm4177; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm1 = (ymm1 * ymm3) -/+ ymm5178; FMA4-NEXT: retq179entry:180 %AB = fmul contract <16 x float> %A, %B181 %Sub = fsub contract <16 x float> %AB, %C182 %Add = fadd contract <16 x float> %AB, %C183 %subadd = shufflevector <16 x float> %Add, <16 x float> %Sub, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>184 ret <16 x float> %subadd185}186 187; This should not be matched to fmsubadd because the mul is on the wrong side of the fsub.188define <2 x double> @mul_subadd_bad_commute(<2 x double> %A, <2 x double> %B, <2 x double> %C) {189; CHECK-LABEL: mul_subadd_bad_commute:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vmulpd %xmm1, %xmm0, %xmm0192; CHECK-NEXT: vsubpd %xmm0, %xmm2, %xmm1193; CHECK-NEXT: vaddpd %xmm2, %xmm0, %xmm0194; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]195; CHECK-NEXT: retq196entry:197 %AB = fmul contract <2 x double> %A, %B198 %Sub = fsub <2 x double> %C, %AB199 %Add = fadd <2 x double> %AB, %C200 %subadd = shufflevector <2 x double> %Add, <2 x double> %Sub, <2 x i32> <i32 0, i32 3>201 ret <2 x double> %subadd202}203