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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE3; RUN: llc -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX4; RUN: llc -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512f < %s | FileCheck %s --check-prefix=AVX5 6; Verify that we're folding the load into the math instruction.7; This pattern is generated out of the simplest intrinsics usage:8; _mm_add_ss(a, _mm_load_ss(b));9 10define <4 x float> @addss(<4 x float> %va, ptr %pb) {11; SSE-LABEL: addss:12; SSE: # %bb.0:13; SSE-NEXT: addss (%rdi), %xmm014; SSE-NEXT: retq15;16; AVX-LABEL: addss:17; AVX: # %bb.0:18; AVX-NEXT: vaddss (%rdi), %xmm0, %xmm019; AVX-NEXT: retq20 %a = extractelement <4 x float> %va, i32 021 %b = load float, ptr %pb22 %r = fadd float %a, %b23 %vr = insertelement <4 x float> %va, float %r, i32 024 ret <4 x float> %vr25}26 27define <2 x double> @addsd(<2 x double> %va, ptr %pb) {28; SSE-LABEL: addsd:29; SSE: # %bb.0:30; SSE-NEXT: addsd (%rdi), %xmm031; SSE-NEXT: retq32;33; AVX-LABEL: addsd:34; AVX: # %bb.0:35; AVX-NEXT: vaddsd (%rdi), %xmm0, %xmm036; AVX-NEXT: retq37 %a = extractelement <2 x double> %va, i32 038 %b = load double, ptr %pb39 %r = fadd double %a, %b40 %vr = insertelement <2 x double> %va, double %r, i32 041 ret <2 x double> %vr42}43 44define <4 x float> @subss(<4 x float> %va, ptr %pb) {45; SSE-LABEL: subss:46; SSE: # %bb.0:47; SSE-NEXT: subss (%rdi), %xmm048; SSE-NEXT: retq49;50; AVX-LABEL: subss:51; AVX: # %bb.0:52; AVX-NEXT: vsubss (%rdi), %xmm0, %xmm053; AVX-NEXT: retq54 %a = extractelement <4 x float> %va, i32 055 %b = load float, ptr %pb56 %r = fsub float %a, %b57 %vr = insertelement <4 x float> %va, float %r, i32 058 ret <4 x float> %vr59}60 61define <2 x double> @subsd(<2 x double> %va, ptr %pb) {62; SSE-LABEL: subsd:63; SSE: # %bb.0:64; SSE-NEXT: subsd (%rdi), %xmm065; SSE-NEXT: retq66;67; AVX-LABEL: subsd:68; AVX: # %bb.0:69; AVX-NEXT: vsubsd (%rdi), %xmm0, %xmm070; AVX-NEXT: retq71 %a = extractelement <2 x double> %va, i32 072 %b = load double, ptr %pb73 %r = fsub double %a, %b74 %vr = insertelement <2 x double> %va, double %r, i32 075 ret <2 x double> %vr76}77 78define <4 x float> @mulss(<4 x float> %va, ptr %pb) {79; SSE-LABEL: mulss:80; SSE: # %bb.0:81; SSE-NEXT: mulss (%rdi), %xmm082; SSE-NEXT: retq83;84; AVX-LABEL: mulss:85; AVX: # %bb.0:86; AVX-NEXT: vmulss (%rdi), %xmm0, %xmm087; AVX-NEXT: retq88 %a = extractelement <4 x float> %va, i32 089 %b = load float, ptr %pb90 %r = fmul float %a, %b91 %vr = insertelement <4 x float> %va, float %r, i32 092 ret <4 x float> %vr93}94 95define <2 x double> @mulsd(<2 x double> %va, ptr %pb) {96; SSE-LABEL: mulsd:97; SSE: # %bb.0:98; SSE-NEXT: mulsd (%rdi), %xmm099; SSE-NEXT: retq100;101; AVX-LABEL: mulsd:102; AVX: # %bb.0:103; AVX-NEXT: vmulsd (%rdi), %xmm0, %xmm0104; AVX-NEXT: retq105 %a = extractelement <2 x double> %va, i32 0106 %b = load double, ptr %pb107 %r = fmul double %a, %b108 %vr = insertelement <2 x double> %va, double %r, i32 0109 ret <2 x double> %vr110}111 112define <4 x float> @divss(<4 x float> %va, ptr %pb) {113; SSE-LABEL: divss:114; SSE: # %bb.0:115; SSE-NEXT: divss (%rdi), %xmm0116; SSE-NEXT: retq117;118; AVX-LABEL: divss:119; AVX: # %bb.0:120; AVX-NEXT: vdivss (%rdi), %xmm0, %xmm0121; AVX-NEXT: retq122 %a = extractelement <4 x float> %va, i32 0123 %b = load float, ptr %pb124 %r = fdiv float %a, %b125 %vr = insertelement <4 x float> %va, float %r, i32 0126 ret <4 x float> %vr127}128 129define <2 x double> @divsd(<2 x double> %va, ptr %pb) {130; SSE-LABEL: divsd:131; SSE: # %bb.0:132; SSE-NEXT: divsd (%rdi), %xmm0133; SSE-NEXT: retq134;135; AVX-LABEL: divsd:136; AVX: # %bb.0:137; AVX-NEXT: vdivsd (%rdi), %xmm0, %xmm0138; AVX-NEXT: retq139 %a = extractelement <2 x double> %va, i32 0140 %b = load double, ptr %pb141 %r = fdiv double %a, %b142 %vr = insertelement <2 x double> %va, double %r, i32 0143 ret <2 x double> %vr144}145