35 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Use CPU parameters to ensure that a CPU-specific attribute is not overriding the AVX definition.3 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx | FileCheck %s --check-prefix=SSE8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx -mattr=-avx | FileCheck %s --check-prefix=SSE9; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -mattr=-avx | FileCheck %s --check-prefix=SSE10 11; No need to load unaligned operand from memory using an explicit instruction with AVX.12; The operand should be folded into the AND instr.13 14; With SSE, folding memory operands into math/logic ops requires 16-byte alignment15; unless specially configured on some CPUs such as AMD Family 10H.16 17define <4 x i32> @test1(ptr %p0, <4 x i32> %in1) nounwind {18; CHECK-LABEL: test1:19; CHECK: # %bb.0:20; CHECK-NEXT: vandps (%rdi), %xmm0, %xmm021; CHECK-NEXT: retq22;23; SSE-LABEL: test1:24; SSE: # %bb.0:25; SSE-NEXT: movups (%rdi), %xmm126; SSE-NEXT: andps %xmm1, %xmm027; SSE-NEXT: retq28 %in0 = load <4 x i32>, ptr %p0, align 229 %a = and <4 x i32> %in0, %in130 ret <4 x i32> %a31 32 33}34 35