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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s3 4; PR22428: https://llvm.org/bugs/show_bug.cgi?id=224285; f1, f2, f3, and f4 should use an integer logic instruction.6; f5, f6, f9, and f10 should use an FP (SSE) logic instruction.7;8; f7 and f8 are less clear.9;10; For f7 and f8, the SSE instructions don't take immediate operands, so if we11; use one of those, we either have to load a constant from memory or move the12; scalar immediate value from an integer register over to an SSE register.13; Optimizing for size may affect that decision. Also, note that there are no14; scalar versions of the FP logic ops, so if we want to fold a load into a15; logic op, we have to load or splat a 16-byte vector constant.16 17; 1 FP operand, 1 int operand, int result18 19define i32 @f1(float %x, i32 %y) {20; CHECK-LABEL: f1:21; CHECK: # %bb.0:22; CHECK-NEXT: movd %xmm0, %eax23; CHECK-NEXT: andl %edi, %eax24; CHECK-NEXT: retq25 %bc1 = bitcast float %x to i3226 %and = and i32 %bc1, %y27 ret i32 %and28}29 30; Swap operands of the logic op.31 32define i32 @f2(float %x, i32 %y) {33; CHECK-LABEL: f2:34; CHECK: # %bb.0:35; CHECK-NEXT: movd %xmm0, %eax36; CHECK-NEXT: andl %edi, %eax37; CHECK-NEXT: retq38 %bc1 = bitcast float %x to i3239 %and = and i32 %y, %bc140 ret i32 %and41}42 43; 1 FP operand, 1 constant operand, int result44 45define i32 @f3(float %x) {46; CHECK-LABEL: f3:47; CHECK: # %bb.0:48; CHECK-NEXT: movd %xmm0, %eax49; CHECK-NEXT: andl $1, %eax50; CHECK-NEXT: retq51 %bc1 = bitcast float %x to i3252 %and = and i32 %bc1, 153 ret i32 %and54}55 56; Swap operands of the logic op.57 58define i32 @f4(float %x) {59; CHECK-LABEL: f4:60; CHECK: # %bb.0:61; CHECK-NEXT: movd %xmm0, %eax62; CHECK-NEXT: andl $2, %eax63; CHECK-NEXT: retq64 %bc1 = bitcast float %x to i3265 %and = and i32 2, %bc166 ret i32 %and67}68 69; 1 FP operand, 1 integer operand, FP result70 71define float @f5(float %x, i32 %y) {72; CHECK-LABEL: f5:73; CHECK: # %bb.0:74; CHECK-NEXT: movd %edi, %xmm175; CHECK-NEXT: pand %xmm1, %xmm076; CHECK-NEXT: retq77 %bc1 = bitcast float %x to i3278 %and = and i32 %bc1, %y79 %bc2 = bitcast i32 %and to float80 ret float %bc281}82 83; Swap operands of the logic op.84 85define float @f6(float %x, i32 %y) {86; CHECK-LABEL: f6:87; CHECK: # %bb.0:88; CHECK-NEXT: movd %edi, %xmm189; CHECK-NEXT: pand %xmm1, %xmm090; CHECK-NEXT: retq91 %bc1 = bitcast float %x to i3292 %and = and i32 %y, %bc193 %bc2 = bitcast i32 %and to float94 ret float %bc295}96 97; 1 FP operand, 1 constant operand, FP result98 99define float @f7(float %x) {100; CHECK-LABEL: f7:101; CHECK: # %bb.0:102; CHECK-NEXT: movss {{.*#+}} xmm1 = [4.20389539E-45,0.0E+0,0.0E+0,0.0E+0]103; CHECK-NEXT: andps %xmm1, %xmm0104; CHECK-NEXT: retq105 %bc1 = bitcast float %x to i32106 %and = and i32 %bc1, 3107 %bc2 = bitcast i32 %and to float108 ret float %bc2109}110 111; Swap operands of the logic op.112 113define float @f8(float %x) {114; CHECK-LABEL: f8:115; CHECK: # %bb.0:116; CHECK-NEXT: movss {{.*#+}} xmm1 = [5.60519386E-45,0.0E+0,0.0E+0,0.0E+0]117; CHECK-NEXT: andps %xmm1, %xmm0118; CHECK-NEXT: retq119 %bc1 = bitcast float %x to i32120 %and = and i32 4, %bc1121 %bc2 = bitcast i32 %and to float122 ret float %bc2123}124 125; 2 FP operands, int result126 127define i32 @f9(float %x, float %y) {128; CHECK-LABEL: f9:129; CHECK: # %bb.0:130; CHECK-NEXT: pand %xmm1, %xmm0131; CHECK-NEXT: movd %xmm0, %eax132; CHECK-NEXT: retq133 %bc1 = bitcast float %x to i32134 %bc2 = bitcast float %y to i32135 %and = and i32 %bc1, %bc2136 ret i32 %and137}138 139; 2 FP operands, FP result140 141define float @f10(float %x, float %y) {142; CHECK-LABEL: f10:143; CHECK: # %bb.0:144; CHECK-NEXT: andps %xmm1, %xmm0145; CHECK-NEXT: retq146 %bc1 = bitcast float %x to i32147 %bc2 = bitcast float %y to i32148 %and = and i32 %bc1, %bc2149 %bc3 = bitcast i32 %and to float150 ret float %bc3151}152 153define float @or(float %x, float %y) {154; CHECK-LABEL: or:155; CHECK: # %bb.0:156; CHECK-NEXT: orps %xmm1, %xmm0157; CHECK-NEXT: retq158 %bc1 = bitcast float %x to i32159 %bc2 = bitcast float %y to i32160 %and = or i32 %bc1, %bc2161 %bc3 = bitcast i32 %and to float162 ret float %bc3163}164 165define float @xor(float %x, float %y) {166; CHECK-LABEL: xor:167; CHECK: # %bb.0:168; CHECK-NEXT: xorps %xmm1, %xmm0169; CHECK-NEXT: retq170 %bc1 = bitcast float %x to i32171 %bc2 = bitcast float %y to i32172 %and = xor i32 %bc1, %bc2173 %bc3 = bitcast i32 %and to float174 ret float %bc3175}176 177define float @f7_or(float %x) {178; CHECK-LABEL: f7_or:179; CHECK: # %bb.0:180; CHECK-NEXT: movss {{.*#+}} xmm1 = [4.20389539E-45,0.0E+0,0.0E+0,0.0E+0]181; CHECK-NEXT: orps %xmm1, %xmm0182; CHECK-NEXT: retq183 %bc1 = bitcast float %x to i32184 %and = or i32 %bc1, 3185 %bc2 = bitcast i32 %and to float186 ret float %bc2187}188 189define float @f7_xor(float %x) {190; CHECK-LABEL: f7_xor:191; CHECK: # %bb.0:192; CHECK-NEXT: movss {{.*#+}} xmm1 = [4.20389539E-45,0.0E+0,0.0E+0,0.0E+0]193; CHECK-NEXT: xorps %xmm1, %xmm0194; CHECK-NEXT: retq195 %bc1 = bitcast float %x to i32196 %and = xor i32 %bc1, 3197 %bc2 = bitcast i32 %and to float198 ret float %bc2199}200 201; Make sure that doubles work too.202 203define double @doubles(double %x, double %y) {204; CHECK-LABEL: doubles:205; CHECK: # %bb.0:206; CHECK-NEXT: andps %xmm1, %xmm0207; CHECK-NEXT: retq208 %bc1 = bitcast double %x to i64209 %bc2 = bitcast double %y to i64210 %and = and i64 %bc1, %bc2211 %bc3 = bitcast i64 %and to double212 ret double %bc3213}214 215define double @f7_double(double %x) {216; CHECK-LABEL: f7_double:217; CHECK: # %bb.0:218; CHECK-NEXT: movsd {{.*#+}} xmm1 = [1.4821969375237396E-323,0.0E+0]219; CHECK-NEXT: andps %xmm1, %xmm0220; CHECK-NEXT: retq221 %bc1 = bitcast double %x to i64222 %and = and i64 %bc1, 3223 %bc2 = bitcast i64 %and to double224 ret double %bc2225}226 227; Grabbing the sign bit is a special case that could be handled228; by movmskps/movmskpd, but if we're not shifting it over, then229; a simple FP logic op is cheaper.230 231define float @movmsk(float %x) {232; CHECK-LABEL: movmsk:233; CHECK: # %bb.0:234; CHECK-NEXT: movss {{.*#+}} xmm1 = [-0.0E+0,0.0E+0,0.0E+0,0.0E+0]235; CHECK-NEXT: andps %xmm1, %xmm0236; CHECK-NEXT: retq237 %bc1 = bitcast float %x to i32238 %and = and i32 %bc1, 2147483648239 %bc2 = bitcast i32 %and to float240 ret float %bc2241}242 243define double @bitcast_fabs(double %x) {244; CHECK-LABEL: bitcast_fabs:245; CHECK: # %bb.0:246; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0247; CHECK-NEXT: retq248 %bc1 = bitcast double %x to i64249 %and = and i64 %bc1, 9223372036854775807250 %bc2 = bitcast i64 %and to double251 ret double %bc2252}253 254define float @bitcast_fneg(float %x) {255; CHECK-LABEL: bitcast_fneg:256; CHECK: # %bb.0:257; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0258; CHECK-NEXT: retq259 %bc1 = bitcast float %x to i32260 %xor = xor i32 %bc1, 2147483648261 %bc2 = bitcast i32 %xor to float262 ret float %bc2263}264 265define <2 x double> @bitcast_fabs_vec(<2 x double> %x) {266; CHECK-LABEL: bitcast_fabs_vec:267; CHECK: # %bb.0:268; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0269; CHECK-NEXT: retq270 %bc1 = bitcast <2 x double> %x to <2 x i64>271 %and = and <2 x i64> %bc1, <i64 9223372036854775807, i64 9223372036854775807>272 %bc2 = bitcast <2 x i64> %and to <2 x double>273 ret <2 x double> %bc2274}275 276define <4 x float> @bitcast_fneg_vec(<4 x float> %x) {277; CHECK-LABEL: bitcast_fneg_vec:278; CHECK: # %bb.0:279; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0280; CHECK-NEXT: retq281 %bc1 = bitcast <4 x float> %x to <4 x i32>282 %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>283 %bc2 = bitcast <4 x i32> %xor to <4 x float>284 ret <4 x float> %bc2285}286 287define float @fadd_bitcast_fneg(float %x, float %y) {288; CHECK-LABEL: fadd_bitcast_fneg:289; CHECK: # %bb.0:290; CHECK-NEXT: subss %xmm1, %xmm0291; CHECK-NEXT: retq292 %bc1 = bitcast float %y to i32293 %xor = xor i32 %bc1, 2147483648294 %bc2 = bitcast i32 %xor to float295 %fadd = fadd float %x, %bc2296 ret float %fadd297}298 299define float @fsub_bitcast_fneg(float %x, float %y) {300; CHECK-LABEL: fsub_bitcast_fneg:301; CHECK: # %bb.0:302; CHECK-NEXT: addss %xmm1, %xmm0303; CHECK-NEXT: retq304 %bc1 = bitcast float %y to i32305 %xor = xor i32 %bc1, 2147483648306 %bc2 = bitcast i32 %xor to float307 %fsub = fsub float %x, %bc2308 ret float %fsub309}310 311define float @nabsf(float %a) {312; CHECK-LABEL: nabsf:313; CHECK: # %bb.0:314; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0315; CHECK-NEXT: retq316 %conv = bitcast float %a to i32317 %and = or i32 %conv, -2147483648318 %conv1 = bitcast i32 %and to float319 ret float %conv1320}321 322define double @nabsd(double %a) {323; CHECK-LABEL: nabsd:324; CHECK: # %bb.0:325; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0326; CHECK-NEXT: retq327 %conv = bitcast double %a to i64328 %and = or i64 %conv, -9223372036854775808329 %conv1 = bitcast i64 %and to double330 ret double %conv1331}332 333define <4 x float> @nabsv4f32(<4 x float> %a) {334; CHECK-LABEL: nabsv4f32:335; CHECK: # %bb.0:336; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0337; CHECK-NEXT: retq338 %conv = bitcast <4 x float> %a to <4 x i32>339 %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>340 %conv1 = bitcast <4 x i32> %and to <4 x float>341 ret <4 x float> %conv1342}343 344define <2 x double> @nabsv2d64(<2 x double> %a) {345; CHECK-LABEL: nabsv2d64:346; CHECK: # %bb.0:347; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0348; CHECK-NEXT: retq349 %conv = bitcast <2 x double> %a to <2 x i64>350 %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>351 %conv1 = bitcast <2 x i64> %and to <2 x double>352 ret <2 x double> %conv1353}354 355define <4 x float> @fadd_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) {356; CHECK-LABEL: fadd_bitcast_fneg_vec:357; CHECK: # %bb.0:358; CHECK-NEXT: subps %xmm1, %xmm0359; CHECK-NEXT: retq360 %bc1 = bitcast <4 x float> %y to <4 x i32>361 %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>362 %bc2 = bitcast <4 x i32> %xor to <4 x float>363 %fadd = fadd <4 x float> %x, %bc2364 ret <4 x float> %fadd365}366 367define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {368; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts:369; CHECK: # %bb.0:370; CHECK-NEXT: subps %xmm1, %xmm0371; CHECK-NEXT: retq372 %bc1 = bitcast <4 x float> %y to <4 x i32>373 %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 undef, i32 2147483648>374 %bc2 = bitcast <4 x i32> %xor to <4 x float>375 %fadd = fadd <4 x float> %x, %bc2376 ret <4 x float> %fadd377}378 379define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) {380; CHECK-LABEL: fsub_bitcast_fneg_vec:381; CHECK: # %bb.0:382; CHECK-NEXT: addps %xmm1, %xmm0383; CHECK-NEXT: retq384 %bc1 = bitcast <4 x float> %y to <4 x i32>385 %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>386 %bc2 = bitcast <4 x i32> %xor to <4 x float>387 %fsub = fsub <4 x float> %x, %bc2388 ret <4 x float> %fsub389}390 391define <4 x float> @fsub_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {392; CHECK-LABEL: fsub_bitcast_fneg_vec_undef_elts:393; CHECK: # %bb.0:394; CHECK-NEXT: addps %xmm1, %xmm0395; CHECK-NEXT: retq396 %bc1 = bitcast <4 x float> %y to <4 x i32>397 %xor = xor <4 x i32> %bc1, <i32 undef, i32 2147483648, i32 undef, i32 2147483648>398 %bc2 = bitcast <4 x i32> %xor to <4 x float>399 %fsub = fsub <4 x float> %x, %bc2400 ret <4 x float> %fsub401}402 403define <4 x float> @fadd_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) {404; CHECK-LABEL: fadd_bitcast_fneg_vec_width:405; CHECK: # %bb.0:406; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1407; CHECK-NEXT: addps %xmm1, %xmm0408; CHECK-NEXT: retq409 %bc1 = bitcast <4 x float> %y to <2 x i64>410 %xor = xor <2 x i64> %bc1, <i64 -9223372034707292160, i64 -9223372034707292160>411 %bc2 = bitcast <2 x i64> %xor to <4 x float>412 %fadd = fadd <4 x float> %x, %bc2413 ret <4 x float> %fadd414}415 416define <4 x float> @fsub_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) {417; CHECK-LABEL: fsub_bitcast_fneg_vec_width:418; CHECK: # %bb.0:419; CHECK-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1420; CHECK-NEXT: subps %xmm1, %xmm0421; CHECK-NEXT: retq422 %bc1 = bitcast <4 x float> %y to <2 x i64>423 %xor = xor <2 x i64> %bc1, <i64 -9223372034707292160, i64 -9223372034707292160>424 %bc2 = bitcast <2 x i64> %xor to <4 x float>425 %fsub = fsub <4 x float> %x, %bc2426 ret <4 x float> %fsub427}428