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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s3 4; Check constant FP to signed integer conversions that overflow the integer type.5 6define i32 @constant_v2f64_to_i32() {7; CHECK-LABEL: constant_v2f64_to_i32:8; CHECK: # %bb.0:9; CHECK-NEXT: cvtsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax10; CHECK-NEXT: retq11 %r = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> <double 5.0e+09, double undef>)12 ret i32 %r13}14 15define i32 @constant_v2f64_to_i32_round_to_zero() {16; CHECK-LABEL: constant_v2f64_to_i32_round_to_zero:17; CHECK: # %bb.0:18; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax19; CHECK-NEXT: retq20 %r = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> <double 5.0e+09, double undef>)21 ret i32 %r22}23 24define i64 @constant_v2f64_to_i64() {25; CHECK-LABEL: constant_v2f64_to_i64:26; CHECK: # %bb.0:27; CHECK-NEXT: cvtsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax28; CHECK-NEXT: retq29 %r = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> <double 5.0e+19, double undef>)30 ret i64 %r31}32 33define i64 @constant_v2f64_to_i64_round_to_zero() {34; CHECK-LABEL: constant_v2f64_to_i64_round_to_zero:35; CHECK: # %bb.0:36; CHECK-NEXT: cvttsd2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax37; CHECK-NEXT: retq38 %r = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> <double 5.0e+19, double undef>)39 ret i64 %r40}41 42define <4 x i32> @constant_v2f64_to_v4i32() {43; CHECK-LABEL: constant_v2f64_to_v4i32:44; CHECK: # %bb.0:45; CHECK-NEXT: cvtpd2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm046; CHECK-NEXT: retq47 %r = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> <double 5.0e+09, double 5.0e+09>)48 ret <4 x i32> %r49}50 51define <4 x i32> @constant_v2f64_to_v4i32_round_to_zero() {52; CHECK-LABEL: constant_v2f64_to_v4i32_round_to_zero:53; CHECK: # %bb.0:54; CHECK-NEXT: cvttpd2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm055; CHECK-NEXT: retq56 %r = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> <double 5.0e+09, double 5.0e+09>)57 ret <4 x i32> %r58}59 60define i32 @constant_v4f32_to_i32() {61; CHECK-LABEL: constant_v4f32_to_i32:62; CHECK: # %bb.0:63; CHECK-NEXT: cvtss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax64; CHECK-NEXT: retq65 %r = call i32 @llvm.x86.sse.cvtss2si(<4 x float> <float 5.0e+09, float undef, float undef, float undef>)66 ret i32 %r67}68 69define i32 @constant_v4f32_to_i32_round_to_zero() {70; CHECK-LABEL: constant_v4f32_to_i32_round_to_zero:71; CHECK: # %bb.0:72; CHECK-NEXT: cvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax73; CHECK-NEXT: retq74 %r = call i32 @llvm.x86.sse.cvttss2si(<4 x float> <float 5.0e+09, float undef, float undef, float undef>)75 ret i32 %r76}77 78; 9223372036854775808.0 = 0x800000000000000079 80define i64 @constant_v4f32_to_i64() {81; CHECK-LABEL: constant_v4f32_to_i64:82; CHECK: # %bb.0:83; CHECK-NEXT: cvtss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax84; CHECK-NEXT: retq85 %r = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> <float 9223372036854775808.0, float undef, float undef, float undef>)86 ret i64 %r87}88 89define i64 @constant_v4f32_to_i64_round_to_zero() {90; CHECK-LABEL: constant_v4f32_to_i64_round_to_zero:91; CHECK: # %bb.0:92; CHECK-NEXT: cvttss2si {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax93; CHECK-NEXT: retq94 %r = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> <float 9223372036854775808.0, float undef, float undef, float undef>)95 ret i64 %r96}97 98define <4 x i32> @constant_v4f32_to_v4i32() {99; CHECK-LABEL: constant_v4f32_to_v4i32:100; CHECK: # %bb.0:101; CHECK-NEXT: cvtps2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0102; CHECK-NEXT: retq103 %r = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> <float 5.0e+09, float 5.0e+09, float 5.0e+09, float 5.0e+09>)104 ret <4 x i32> %r105}106 107define <4 x i32> @constant_v4f32_to_v4i32_round_to_zero() {108; CHECK-LABEL: constant_v4f32_to_v4i32_round_to_zero:109; CHECK: # %bb.0:110; CHECK-NEXT: cvttps2dq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0111; CHECK-NEXT: retq112 %r = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> <float 5.0e+09, float 5.0e+09, float 5.0e+09, float 5.0e+09>)113 ret <4 x i32> %r114}115 116declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)117declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)118 119declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)120declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)121 122declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>)123declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>)124 125declare i32 @llvm.x86.sse.cvtss2si(<4 x float>)126declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)127 128declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>)129declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>)130 131declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>)132declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)133 134