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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=X86ASM3 4%struct.T = type { i32, i32 }5 6define i32 @freeze_int() {7; X86ASM-LABEL: freeze_int:8; X86ASM: # %bb.0:9; X86ASM-NEXT: imull %eax, %eax10; X86ASM-NEXT: retq11 %y1 = freeze i32 undef12 %t1 = mul i32 %y1, %y113 ret i32 %t114}15 16define i5 @freeze_int2() {17; X86ASM-LABEL: freeze_int2:18; X86ASM: # %bb.0:19; X86ASM-NEXT: mulb %al20; X86ASM-NEXT: retq21 %y1 = freeze i5 undef22 %t1 = mul i5 %y1, %y123 ret i5 %t124}25 26define float @freeze_float() {27; X86ASM-LABEL: freeze_float:28; X86ASM: # %bb.0:29; X86ASM-NEXT: addss %xmm0, %xmm030; X86ASM-NEXT: retq31 %y1 = freeze float undef32 %t1 = fadd float %y1, %y133 ret float %t134}35 36define half @freeze_half() {37; X86ASM-LABEL: freeze_half:38; X86ASM: # %bb.0:39; X86ASM-NEXT: pushq %rax40; X86ASM-NEXT: .cfi_def_cfa_offset 1641; X86ASM-NEXT: callq __extendhfsf2@PLT42; X86ASM-NEXT: addss %xmm0, %xmm043; X86ASM-NEXT: callq __truncsfhf2@PLT44; X86ASM-NEXT: popq %rax45; X86ASM-NEXT: .cfi_def_cfa_offset 846; X86ASM-NEXT: retq47 %y1 = freeze half undef48 %t1 = fadd half %y1, %y149 ret half %t150}51 52define <2 x i32> @freeze_ivec() {53; X86ASM-LABEL: freeze_ivec:54; X86ASM: # %bb.0:55; X86ASM-NEXT: paddd %xmm0, %xmm056; X86ASM-NEXT: retq57 %y1 = freeze <2 x i32> undef58 %t1 = add <2 x i32> %y1, %y159 ret <2 x i32> %t160}61 62define ptr @freeze_ptr() {63; X86ASM-LABEL: freeze_ptr:64; X86ASM: # %bb.0:65; X86ASM-NEXT: addq $4, %rax66; X86ASM-NEXT: retq67 %y1 = freeze ptr undef68 %t1 = getelementptr i8, ptr %y1, i64 469 ret ptr %t170}71 72define i32 @freeze_struct() {73; X86ASM-LABEL: freeze_struct:74; X86ASM: # %bb.0:75; X86ASM-NEXT: addl %eax, %eax76; X86ASM-NEXT: retq77 %y1 = freeze %struct.T undef78 %v1 = extractvalue %struct.T %y1, 079 %v2 = extractvalue %struct.T %y1, 180 %t1 = add i32 %v1, %v281 ret i32 %t182}83 84define i32 @freeze_anonstruct() {85; X86ASM-LABEL: freeze_anonstruct:86; X86ASM: # %bb.0:87; X86ASM-NEXT: addl %eax, %eax88; X86ASM-NEXT: retq89 %y1 = freeze {i32, i32} undef90 %v1 = extractvalue {i32, i32} %y1, 091 %v2 = extractvalue {i32, i32} %y1, 192 %t1 = add i32 %v1, %v293 ret i32 %t194}95 96define i32 @freeze_anonstruct2() {97; X86ASM-LABEL: freeze_anonstruct2:98; X86ASM: # %bb.0:99; X86ASM-NEXT: movzwl %ax, %eax100; X86ASM-NEXT: addl %eax, %eax101; X86ASM-NEXT: retq102 %y1 = freeze {i32, i16} undef103 %v1 = extractvalue {i32, i16} %y1, 0104 %v2 = extractvalue {i32, i16} %y1, 1105 %z2 = zext i16 %v2 to i32106 %t1 = add i32 %v1, %z2107 ret i32 %t1108}109 110define i64 @freeze_array() {111; X86ASM-LABEL: freeze_array:112; X86ASM: # %bb.0:113; X86ASM-NEXT: addq %rax, %rax114; X86ASM-NEXT: retq115 %y1 = freeze [2 x i64] undef116 %v1 = extractvalue [2 x i64] %y1, 0117 %v2 = extractvalue [2 x i64] %y1, 1118 %t1 = add i64 %v1, %v2119 ret i64 %t1120}121 122; Make sure we emit a movl to zext the input before the imulq. This previously123; failed because freeze was not listed in the instructions that don't zext their124; result in the def32 pattern X86InstrCompiler.td.125define i32 @freeze_zext(i64 %a) nounwind {126; X86ASM-LABEL: freeze_zext:127; X86ASM: # %bb.0: # %entry128; X86ASM-NEXT: movq %rdi, %rax129; X86ASM-NEXT: movl %eax, %ecx130; X86ASM-NEXT: movl $3435973837, %edx # imm = 0xCCCCCCCD131; X86ASM-NEXT: imulq %rcx, %rdx132; X86ASM-NEXT: shrq $35, %rdx133; X86ASM-NEXT: addl %edx, %edx134; X86ASM-NEXT: leal (%rdx,%rdx,4), %ecx135; X86ASM-NEXT: subl %ecx, %eax136; X86ASM-NEXT: # kill: def $eax killed $eax killed $rax137; X86ASM-NEXT: retq138entry:139 %x = trunc i64 %a to i32140 %y = freeze i32 %x141 %z = urem i32 %y, 10142 ret i32 %z143}144 145; Make sure we don't crash when replacing all uses of N with an existing freeze N.146 147define i64 @pr155345(ptr %p1, i1 %cond, ptr %p2, ptr %p3) {148; X86ASM-LABEL: pr155345:149; X86ASM: # %bb.0: # %entry150; X86ASM-NEXT: movzbl (%rdi), %edi151; X86ASM-NEXT: xorl %eax, %eax152; X86ASM-NEXT: orb $1, %dil153; X86ASM-NEXT: movb %dil, (%rdx)154; X86ASM-NEXT: movzbl %dil, %edx155; X86ASM-NEXT: cmovel %edx, %eax156; X86ASM-NEXT: sete %dil157; X86ASM-NEXT: testb $1, %sil158; X86ASM-NEXT: cmovnel %edx, %eax159; X86ASM-NEXT: movb %dl, (%rcx)160; X86ASM-NEXT: movl $1, %edx161; X86ASM-NEXT: movl %eax, %ecx162; X86ASM-NEXT: shlq %cl, %rdx163; X86ASM-NEXT: orb %sil, %dil164; X86ASM-NEXT: movzbl %dil, %eax165; X86ASM-NEXT: andl %edx, %eax166; X86ASM-NEXT: andl $1, %eax167; X86ASM-NEXT: retq168entry:169 %load1 = load i8, ptr %p1, align 1170 %v1 = or i8 %load1, 1171 %v2 = zext i8 %v1 to i32172 store i8 %v1, ptr %p2, align 1173 %v3 = load i8, ptr %p2, align 1174 %ext1 = sext i8 %v3 to i64175 %ext2 = zext i32 %v2 to i64176 %cmp1 = icmp ult i64 0, %ext1177 %v4 = select i1 %cond, i1 false, i1 %cmp1178 %sel1 = select i1 %v4, i64 0, i64 %ext2179 %shl = shl i64 1, %sel1180 store i8 %v1, ptr %p3, align 1181 %v5 = load i8, ptr %p3, align 1182 %ext3 = sext i8 %v5 to i64183 %cmp2 = icmp ult i64 0, %ext3184 %v6 = select i1 %cond, i1 false, i1 %cmp2185 %sel2 = select i1 %v6, i64 0, i64 1186 %and = and i64 %sel2, %shl187 ret i64 %and188}189