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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s3 4; Eliminating a shuffle means we have to replace an undef operand of a horizontal op.5 6define void @PR43225(ptr %p0, ptr %p1, <4 x double> %x, <4 x double> %y, <4 x double> %z) nounwind {7; CHECK-LABEL: PR43225:8; CHECK: # %bb.0:9; CHECK-NEXT: vmovaps (%rdi), %ymm010; CHECK-NEXT: vmovaps (%rsi), %ymm011; CHECK-NEXT: vhsubpd %ymm2, %ymm2, %ymm012; CHECK-NEXT: vmovapd %ymm0, (%rdi)13; CHECK-NEXT: vzeroupper14; CHECK-NEXT: retq15 %t39 = load volatile <4 x double>, ptr %p0, align 3216 %shuffle11 = shufflevector <4 x double> %t39, <4 x double> %x, <4 x i32> <i32 1, i32 5, i32 3, i32 7>17 %t40 = load volatile <4 x double>, ptr %p1, align 3218 %t41 = tail call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %shuffle11, <4 x double> %t40)19 %t42 = tail call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %z, <4 x double> %t41)20 %shuffle12 = shufflevector <4 x double> %t42, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>21 store volatile <4 x double> %shuffle12, ptr %p0, align 3222 ret void23}24 25declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>)26declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>)27