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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3 | FileCheck %s --check-prefixes=SSE,SSE-SLOW3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3,fast-hops | FileCheck %s --check-prefixes=SSE,SSE-FAST4; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX-SLOW,AVX1-SLOW5; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=AVX,AVX-FAST,AVX1-FAST6; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX-SLOW,AVX512,AVX512-SLOW7; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,fast-hops | FileCheck %s --check-prefixes=AVX,AVX-FAST,AVX512,AVX512-FAST8 9; Verify that we correctly fold horizontal binop even in the presence of UNDEFs.10 11define <4 x float> @test1_undef(<4 x float> %a, <4 x float> %b) {12; SSE-LABEL: test1_undef:13; SSE: # %bb.0:14; SSE-NEXT: haddps %xmm1, %xmm015; SSE-NEXT: retq16;17; AVX-LABEL: test1_undef:18; AVX: # %bb.0:19; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm020; AVX-NEXT: retq21 %vecext = extractelement <4 x float> %a, i32 022 %vecext1 = extractelement <4 x float> %a, i32 123 %add = fadd float %vecext, %vecext124 %vecinit = insertelement <4 x float> undef, float %add, i32 025 %vecext2 = extractelement <4 x float> %a, i32 226 %vecext3 = extractelement <4 x float> %a, i32 327 %add4 = fadd float %vecext2, %vecext328 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 129 %vecext10 = extractelement <4 x float> %b, i32 230 %vecext11 = extractelement <4 x float> %b, i32 331 %add12 = fadd float %vecext10, %vecext1132 %vecinit13 = insertelement <4 x float> %vecinit5, float %add12, i32 333 ret <4 x float> %vecinit1334}35 36define <4 x float> @test2_undef(<4 x float> %a, <4 x float> %b) {37; SSE-LABEL: test2_undef:38; SSE: # %bb.0:39; SSE-NEXT: haddps %xmm1, %xmm040; SSE-NEXT: retq41;42; AVX-LABEL: test2_undef:43; AVX: # %bb.0:44; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm045; AVX-NEXT: retq46 %vecext = extractelement <4 x float> %a, i32 047 %vecext1 = extractelement <4 x float> %a, i32 148 %add = fadd float %vecext, %vecext149 %vecinit = insertelement <4 x float> undef, float %add, i32 050 %vecext6 = extractelement <4 x float> %b, i32 051 %vecext7 = extractelement <4 x float> %b, i32 152 %add8 = fadd float %vecext6, %vecext753 %vecinit9 = insertelement <4 x float> %vecinit, float %add8, i32 254 %vecext10 = extractelement <4 x float> %b, i32 255 %vecext11 = extractelement <4 x float> %b, i32 356 %add12 = fadd float %vecext10, %vecext1157 %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 358 ret <4 x float> %vecinit1359}60 61define <4 x float> @test3_undef(<4 x float> %a, <4 x float> %b) {62; SSE-LABEL: test3_undef:63; SSE: # %bb.0:64; SSE-NEXT: haddps %xmm1, %xmm065; SSE-NEXT: retq66;67; AVX-LABEL: test3_undef:68; AVX: # %bb.0:69; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm070; AVX-NEXT: retq71 %vecext = extractelement <4 x float> %a, i32 072 %vecext1 = extractelement <4 x float> %a, i32 173 %add = fadd float %vecext, %vecext174 %vecinit = insertelement <4 x float> undef, float %add, i32 075 %vecext2 = extractelement <4 x float> %a, i32 276 %vecext3 = extractelement <4 x float> %a, i32 377 %add4 = fadd float %vecext2, %vecext378 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 179 %vecext6 = extractelement <4 x float> %b, i32 080 %vecext7 = extractelement <4 x float> %b, i32 181 %add8 = fadd float %vecext6, %vecext782 %vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 283 ret <4 x float> %vecinit984}85 86define <4 x float> @test4_undef(<4 x float> %a, <4 x float> %b) {87; SSE-SLOW-LABEL: test4_undef:88; SSE-SLOW: # %bb.0:89; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]90; SSE-SLOW-NEXT: addss %xmm1, %xmm091; SSE-SLOW-NEXT: retq92;93; SSE-FAST-LABEL: test4_undef:94; SSE-FAST: # %bb.0:95; SSE-FAST-NEXT: haddps %xmm0, %xmm096; SSE-FAST-NEXT: retq97;98; AVX-SLOW-LABEL: test4_undef:99; AVX-SLOW: # %bb.0:100; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]101; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0102; AVX-SLOW-NEXT: retq103;104; AVX-FAST-LABEL: test4_undef:105; AVX-FAST: # %bb.0:106; AVX-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0107; AVX-FAST-NEXT: retq108 %vecext = extractelement <4 x float> %a, i32 0109 %vecext1 = extractelement <4 x float> %a, i32 1110 %add = fadd float %vecext, %vecext1111 %vecinit = insertelement <4 x float> undef, float %add, i32 0112 ret <4 x float> %vecinit113}114 115define <2 x double> @test5_undef(<2 x double> %a, <2 x double> %b) {116; SSE-SLOW-LABEL: test5_undef:117; SSE-SLOW: # %bb.0:118; SSE-SLOW-NEXT: movapd %xmm0, %xmm1119; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]120; SSE-SLOW-NEXT: addsd %xmm1, %xmm0121; SSE-SLOW-NEXT: retq122;123; SSE-FAST-LABEL: test5_undef:124; SSE-FAST: # %bb.0:125; SSE-FAST-NEXT: haddpd %xmm0, %xmm0126; SSE-FAST-NEXT: retq127;128; AVX-SLOW-LABEL: test5_undef:129; AVX-SLOW: # %bb.0:130; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]131; AVX-SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0132; AVX-SLOW-NEXT: retq133;134; AVX-FAST-LABEL: test5_undef:135; AVX-FAST: # %bb.0:136; AVX-FAST-NEXT: vhaddpd %xmm0, %xmm0, %xmm0137; AVX-FAST-NEXT: retq138 %vecext = extractelement <2 x double> %a, i32 0139 %vecext1 = extractelement <2 x double> %a, i32 1140 %add = fadd double %vecext, %vecext1141 %vecinit = insertelement <2 x double> undef, double %add, i32 0142 ret <2 x double> %vecinit143}144 145define <4 x float> @test6_undef(<4 x float> %a, <4 x float> %b) {146; SSE-LABEL: test6_undef:147; SSE: # %bb.0:148; SSE-NEXT: haddps %xmm0, %xmm0149; SSE-NEXT: retq150;151; AVX-LABEL: test6_undef:152; AVX: # %bb.0:153; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0154; AVX-NEXT: retq155 %vecext = extractelement <4 x float> %a, i32 0156 %vecext1 = extractelement <4 x float> %a, i32 1157 %add = fadd float %vecext, %vecext1158 %vecinit = insertelement <4 x float> undef, float %add, i32 0159 %vecext2 = extractelement <4 x float> %a, i32 2160 %vecext3 = extractelement <4 x float> %a, i32 3161 %add4 = fadd float %vecext2, %vecext3162 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1163 ret <4 x float> %vecinit5164}165 166define <4 x float> @test7_undef(<4 x float> %a, <4 x float> %b) {167; SSE-LABEL: test7_undef:168; SSE: # %bb.0:169; SSE-NEXT: haddps %xmm1, %xmm0170; SSE-NEXT: retq171;172; AVX-LABEL: test7_undef:173; AVX: # %bb.0:174; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0175; AVX-NEXT: retq176 %vecext = extractelement <4 x float> %b, i32 0177 %vecext1 = extractelement <4 x float> %b, i32 1178 %add = fadd float %vecext, %vecext1179 %vecinit = insertelement <4 x float> undef, float %add, i32 2180 %vecext2 = extractelement <4 x float> %b, i32 2181 %vecext3 = extractelement <4 x float> %b, i32 3182 %add4 = fadd float %vecext2, %vecext3183 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 3184 ret <4 x float> %vecinit5185}186 187define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) {188; SSE-SLOW-LABEL: test8_undef:189; SSE-SLOW: # %bb.0:190; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]191; SSE-SLOW-NEXT: addss %xmm0, %xmm1192; SSE-SLOW-NEXT: movaps %xmm0, %xmm2193; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]194; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]195; SSE-SLOW-NEXT: addss %xmm2, %xmm0196; SSE-SLOW-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]197; SSE-SLOW-NEXT: movaps %xmm1, %xmm0198; SSE-SLOW-NEXT: retq199;200; SSE-FAST-LABEL: test8_undef:201; SSE-FAST: # %bb.0:202; SSE-FAST-NEXT: haddps %xmm0, %xmm0203; SSE-FAST-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,1]204; SSE-FAST-NEXT: retq205;206; AVX-SLOW-LABEL: test8_undef:207; AVX-SLOW: # %bb.0:208; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]209; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm1210; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]211; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]212; AVX-SLOW-NEXT: vaddss %xmm0, %xmm2, %xmm0213; AVX-SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]214; AVX-SLOW-NEXT: retq215;216; AVX-FAST-LABEL: test8_undef:217; AVX-FAST: # %bb.0:218; AVX-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0219; AVX-FAST-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1,1,3]220; AVX-FAST-NEXT: retq221 %vecext = extractelement <4 x float> %a, i32 0222 %vecext1 = extractelement <4 x float> %a, i32 1223 %add = fadd float %vecext, %vecext1224 %vecinit = insertelement <4 x float> undef, float %add, i32 0225 %vecext2 = extractelement <4 x float> %a, i32 2226 %vecext3 = extractelement <4 x float> %a, i32 3227 %add4 = fadd float %vecext2, %vecext3228 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 2229 ret <4 x float> %vecinit5230}231 232define <4 x float> @test9_undef(<4 x float> %a, <4 x float> %b) {233; SSE-LABEL: test9_undef:234; SSE: # %bb.0:235; SSE-NEXT: haddps %xmm1, %xmm0236; SSE-NEXT: retq237;238; AVX-LABEL: test9_undef:239; AVX: # %bb.0:240; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0241; AVX-NEXT: retq242 %vecext = extractelement <4 x float> %a, i32 0243 %vecext1 = extractelement <4 x float> %a, i32 1244 %add = fadd float %vecext, %vecext1245 %vecinit = insertelement <4 x float> undef, float %add, i32 0246 %vecext2 = extractelement <4 x float> %b, i32 2247 %vecext3 = extractelement <4 x float> %b, i32 3248 %add4 = fadd float %vecext2, %vecext3249 %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 3250 ret <4 x float> %vecinit5251}252 253define <8 x float> @test10_undef(<8 x float> %a, <8 x float> %b) {254; SSE-LABEL: test10_undef:255; SSE: # %bb.0:256; SSE-NEXT: haddps %xmm2, %xmm0257; SSE-NEXT: retq258;259; AVX-LABEL: test10_undef:260; AVX: # %bb.0:261; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0262; AVX-NEXT: retq263 %vecext = extractelement <8 x float> %a, i32 0264 %vecext1 = extractelement <8 x float> %a, i32 1265 %add = fadd float %vecext, %vecext1266 %vecinit = insertelement <8 x float> undef, float %add, i32 0267 %vecext2 = extractelement <8 x float> %b, i32 2268 %vecext3 = extractelement <8 x float> %b, i32 3269 %add4 = fadd float %vecext2, %vecext3270 %vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 3271 ret <8 x float> %vecinit5272}273 274define <8 x float> @test11_undef(<8 x float> %a, <8 x float> %b) {275; SSE-SLOW-LABEL: test11_undef:276; SSE-SLOW: # %bb.0:277; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]278; SSE-SLOW-NEXT: addss %xmm1, %xmm0279; SSE-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]280; SSE-SLOW-NEXT: addss %xmm3, %xmm1281; SSE-SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0]282; SSE-SLOW-NEXT: retq283;284; SSE-FAST-LABEL: test11_undef:285; SSE-FAST: # %bb.0:286; SSE-FAST-NEXT: movaps %xmm3, %xmm1287; SSE-FAST-NEXT: haddps %xmm0, %xmm0288; SSE-FAST-NEXT: haddps %xmm3, %xmm1289; SSE-FAST-NEXT: retq290;291; AVX-LABEL: test11_undef:292; AVX: # %bb.0:293; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0294; AVX-NEXT: retq295 %vecext = extractelement <8 x float> %a, i32 0296 %vecext1 = extractelement <8 x float> %a, i32 1297 %add = fadd float %vecext, %vecext1298 %vecinit = insertelement <8 x float> undef, float %add, i32 0299 %vecext2 = extractelement <8 x float> %b, i32 4300 %vecext3 = extractelement <8 x float> %b, i32 5301 %add4 = fadd float %vecext2, %vecext3302 %vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 6303 ret <8 x float> %vecinit5304}305 306define <8 x float> @test12_undef(<8 x float> %a, <8 x float> %b) {307; SSE-LABEL: test12_undef:308; SSE: # %bb.0:309; SSE-NEXT: haddps %xmm0, %xmm0310; SSE-NEXT: retq311;312; AVX-LABEL: test12_undef:313; AVX: # %bb.0:314; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0315; AVX-NEXT: retq316 %vecext = extractelement <8 x float> %a, i32 0317 %vecext1 = extractelement <8 x float> %a, i32 1318 %add = fadd float %vecext, %vecext1319 %vecinit = insertelement <8 x float> undef, float %add, i32 0320 %vecext2 = extractelement <8 x float> %a, i32 2321 %vecext3 = extractelement <8 x float> %a, i32 3322 %add4 = fadd float %vecext2, %vecext3323 %vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 1324 ret <8 x float> %vecinit5325}326 327define <8 x float> @test13_undef(<8 x float> %a, <8 x float> %b) {328; SSE-LABEL: test13_undef:329; SSE: # %bb.0:330; SSE-NEXT: haddps %xmm1, %xmm0331; SSE-NEXT: retq332;333; AVX-LABEL: test13_undef:334; AVX: # %bb.0:335; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1336; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0337; AVX-NEXT: retq338 %vecext = extractelement <8 x float> %a, i32 0339 %vecext1 = extractelement <8 x float> %a, i32 1340 %add1 = fadd float %vecext, %vecext1341 %vecinit1 = insertelement <8 x float> undef, float %add1, i32 0342 %vecext2 = extractelement <8 x float> %a, i32 2343 %vecext3 = extractelement <8 x float> %a, i32 3344 %add2 = fadd float %vecext2, %vecext3345 %vecinit2 = insertelement <8 x float> %vecinit1, float %add2, i32 1346 %vecext4 = extractelement <8 x float> %a, i32 4347 %vecext5 = extractelement <8 x float> %a, i32 5348 %add3 = fadd float %vecext4, %vecext5349 %vecinit3 = insertelement <8 x float> %vecinit2, float %add3, i32 2350 %vecext6 = extractelement <8 x float> %a, i32 6351 %vecext7 = extractelement <8 x float> %a, i32 7352 %add4 = fadd float %vecext6, %vecext7353 %vecinit4 = insertelement <8 x float> %vecinit3, float %add4, i32 3354 ret <8 x float> %vecinit4355}356 357define <16 x float> @test13_v16f32_undef(<16 x float> %a, <16 x float> %b) {358; SSE-LABEL: test13_v16f32_undef:359; SSE: # %bb.0:360; SSE-NEXT: haddps %xmm1, %xmm0361; SSE-NEXT: retq362;363; AVX1-SLOW-LABEL: test13_v16f32_undef:364; AVX1-SLOW: # %bb.0:365; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1366; AVX1-SLOW-NEXT: vhaddps %xmm1, %xmm0, %xmm0367; AVX1-SLOW-NEXT: retq368;369; AVX-FAST-LABEL: test13_v16f32_undef:370; AVX-FAST: # %bb.0:371; AVX-FAST-NEXT: vextractf128 $1, %ymm0, %xmm1372; AVX-FAST-NEXT: vhaddps %xmm1, %xmm0, %xmm0373; AVX-FAST-NEXT: retq374;375; AVX512-SLOW-LABEL: test13_v16f32_undef:376; AVX512-SLOW: # %bb.0:377; AVX512-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]378; AVX512-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm1379; AVX512-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]380; AVX512-SLOW-NEXT: vshufps {{.*#+}} xmm3 = xmm0[3,3,3,3]381; AVX512-SLOW-NEXT: vaddss %xmm3, %xmm2, %xmm2382; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]383; AVX512-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0384; AVX512-SLOW-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]385; AVX512-SLOW-NEXT: vaddss %xmm2, %xmm0, %xmm2386; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]387; AVX512-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]388; AVX512-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]389; AVX512-SLOW-NEXT: vaddss %xmm0, %xmm2, %xmm0390; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]391; AVX512-SLOW-NEXT: retq392 %vecext = extractelement <16 x float> %a, i32 0393 %vecext1 = extractelement <16 x float> %a, i32 1394 %add1 = fadd float %vecext, %vecext1395 %vecinit1 = insertelement <16 x float> undef, float %add1, i32 0396 %vecext2 = extractelement <16 x float> %a, i32 2397 %vecext3 = extractelement <16 x float> %a, i32 3398 %add2 = fadd float %vecext2, %vecext3399 %vecinit2 = insertelement <16 x float> %vecinit1, float %add2, i32 1400 %vecext4 = extractelement <16 x float> %a, i32 4401 %vecext5 = extractelement <16 x float> %a, i32 5402 %add3 = fadd float %vecext4, %vecext5403 %vecinit3 = insertelement <16 x float> %vecinit2, float %add3, i32 2404 %vecext6 = extractelement <16 x float> %a, i32 6405 %vecext7 = extractelement <16 x float> %a, i32 7406 %add4 = fadd float %vecext6, %vecext7407 %vecinit4 = insertelement <16 x float> %vecinit3, float %add4, i32 3408 ret <16 x float> %vecinit4409}410define <2 x double> @add_pd_003(<2 x double> %x) {411; SSE-SLOW-LABEL: add_pd_003:412; SSE-SLOW: # %bb.0:413; SSE-SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm0[0,0]414; SSE-SLOW-NEXT: addpd %xmm1, %xmm0415; SSE-SLOW-NEXT: retq416;417; SSE-FAST-LABEL: add_pd_003:418; SSE-FAST: # %bb.0:419; SSE-FAST-NEXT: haddpd %xmm0, %xmm0420; SSE-FAST-NEXT: retq421;422; AVX-SLOW-LABEL: add_pd_003:423; AVX-SLOW: # %bb.0:424; AVX-SLOW-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0]425; AVX-SLOW-NEXT: vaddpd %xmm0, %xmm1, %xmm0426; AVX-SLOW-NEXT: retq427;428; AVX-FAST-LABEL: add_pd_003:429; AVX-FAST: # %bb.0:430; AVX-FAST-NEXT: vhaddpd %xmm0, %xmm0, %xmm0431; AVX-FAST-NEXT: retq432 %l = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 undef, i32 0>433 %add = fadd <2 x double> %l, %x434 ret <2 x double> %add435}436 437; Change shuffle mask - no undefs.438 439define <2 x double> @add_pd_003_2(<2 x double> %x) {440; SSE-SLOW-LABEL: add_pd_003_2:441; SSE-SLOW: # %bb.0:442; SSE-SLOW-NEXT: movapd %xmm0, %xmm1443; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm0[0]444; SSE-SLOW-NEXT: addpd %xmm1, %xmm0445; SSE-SLOW-NEXT: retq446;447; SSE-FAST-LABEL: add_pd_003_2:448; SSE-FAST: # %bb.0:449; SSE-FAST-NEXT: haddpd %xmm0, %xmm0450; SSE-FAST-NEXT: retq451;452; AVX-SLOW-LABEL: add_pd_003_2:453; AVX-SLOW: # %bb.0:454; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]455; AVX-SLOW-NEXT: vaddpd %xmm0, %xmm1, %xmm0456; AVX-SLOW-NEXT: retq457;458; AVX-FAST-LABEL: add_pd_003_2:459; AVX-FAST: # %bb.0:460; AVX-FAST-NEXT: vhaddpd %xmm0, %xmm0, %xmm0461; AVX-FAST-NEXT: retq462 %l = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 0>463 %add = fadd <2 x double> %l, %x464 ret <2 x double> %add465}466 467define <2 x double> @add_pd_010(<2 x double> %x) {468; SSE-LABEL: add_pd_010:469; SSE: # %bb.0:470; SSE-NEXT: haddpd %xmm0, %xmm0471; SSE-NEXT: retq472;473; AVX-SLOW-LABEL: add_pd_010:474; AVX-SLOW: # %bb.0:475; AVX-SLOW-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0]476; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]477; AVX-SLOW-NEXT: vaddpd %xmm0, %xmm1, %xmm0478; AVX-SLOW-NEXT: retq479;480; AVX-FAST-LABEL: add_pd_010:481; AVX-FAST: # %bb.0:482; AVX-FAST-NEXT: vhaddpd %xmm0, %xmm0, %xmm0483; AVX-FAST-NEXT: retq484 %l = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 undef, i32 0>485 %add = fadd <2 x double> %l, %x486 %shuffle2 = shufflevector <2 x double> %add, <2 x double> undef, <2 x i32> <i32 1, i32 undef>487 ret <2 x double> %shuffle2488}489 490define <4 x float> @add_ps_007(<4 x float> %x) {491; SSE-LABEL: add_ps_007:492; SSE: # %bb.0:493; SSE-NEXT: haddps %xmm0, %xmm0494; SSE-NEXT: retq495;496; AVX-LABEL: add_ps_007:497; AVX: # %bb.0:498; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0499; AVX-NEXT: retq500 %l = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 2>501 %r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 3>502 %add = fadd <4 x float> %l, %r503 ret <4 x float> %add504}505 506define <4 x float> @add_ps_030(<4 x float> %x) {507; SSE-SLOW-LABEL: add_ps_030:508; SSE-SLOW: # %bb.0:509; SSE-SLOW-NEXT: movaps %xmm0, %xmm1510; SSE-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]511; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0,2,3]512; SSE-SLOW-NEXT: addps %xmm1, %xmm0513; SSE-SLOW-NEXT: retq514;515; SSE-FAST-LABEL: add_ps_030:516; SSE-FAST: # %bb.0:517; SSE-FAST-NEXT: haddps %xmm0, %xmm0518; SSE-FAST-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,2,3]519; SSE-FAST-NEXT: retq520;521; AVX-SLOW-LABEL: add_ps_030:522; AVX-SLOW: # %bb.0:523; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,1,2,3]524; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,0,2,3]525; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0526; AVX-SLOW-NEXT: retq527;528; AVX-FAST-LABEL: add_ps_030:529; AVX-FAST: # %bb.0:530; AVX-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0531; AVX-FAST-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,2,3]532; AVX-FAST-NEXT: retq533 %l = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 2>534 %r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 3>535 %add = fadd <4 x float> %l, %r536 %shuffle2 = shufflevector <4 x float> %add, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 undef, i32 undef>537 ret <4 x float> %shuffle2538}539 540define <4 x float> @add_ps_007_2(<4 x float> %x) {541; SSE-LABEL: add_ps_007_2:542; SSE: # %bb.0:543; SSE-NEXT: haddps %xmm0, %xmm0544; SSE-NEXT: retq545;546; AVX-LABEL: add_ps_007_2:547; AVX: # %bb.0:548; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0549; AVX-NEXT: retq550 %l = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 undef>551 %r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 undef>552 %add = fadd <4 x float> %l, %r553 ret <4 x float> %add554}555 556define <4 x float> @add_ps_008(<4 x float> %x) {557; SSE-SLOW-LABEL: add_ps_008:558; SSE-SLOW: # %bb.0:559; SSE-SLOW-NEXT: movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2]560; SSE-SLOW-NEXT: addps %xmm1, %xmm0561; SSE-SLOW-NEXT: retq562;563; SSE-FAST-LABEL: add_ps_008:564; SSE-FAST: # %bb.0:565; SSE-FAST-NEXT: haddps %xmm0, %xmm0566; SSE-FAST-NEXT: retq567;568; AVX-SLOW-LABEL: add_ps_008:569; AVX-SLOW: # %bb.0:570; AVX-SLOW-NEXT: vmovsldup {{.*#+}} xmm1 = xmm0[0,0,2,2]571; AVX-SLOW-NEXT: vaddps %xmm0, %xmm1, %xmm0572; AVX-SLOW-NEXT: retq573;574; AVX-FAST-LABEL: add_ps_008:575; AVX-FAST: # %bb.0:576; AVX-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0577; AVX-FAST-NEXT: retq578 %l = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>579 %add = fadd <4 x float> %l, %x580 ret <4 x float> %add581}582 583define <4 x float> @add_ps_016(<4 x float> %0, <4 x float> %1) {584; SSE-LABEL: add_ps_016:585; SSE: # %bb.0:586; SSE-NEXT: haddps %xmm0, %xmm1587; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0,3,3]588; SSE-NEXT: movaps %xmm1, %xmm0589; SSE-NEXT: retq590;591; AVX-LABEL: add_ps_016:592; AVX: # %bb.0:593; AVX-NEXT: vhaddps %xmm0, %xmm1, %xmm0594; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,3,3]595; AVX-NEXT: retq596 %3 = shufflevector <4 x float> %1, <4 x float> %0, <2 x i32> <i32 0, i32 6>597 %4 = shufflevector <4 x float> %1, <4 x float> %0, <2 x i32> <i32 1, i32 7>598 %5 = fadd <2 x float> %3, %4599 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>600 %7 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 3, i32 undef>601 %8 = fadd <4 x float> %7, %1602 %9 = shufflevector <4 x float> %6, <4 x float> %8, <4 x i32> <i32 6, i32 1, i32 2, i32 undef>603 ret <4 x float> %9604}605 606define <4 x float> @add_ps_017(<4 x float> %x) {607; SSE-SLOW-LABEL: add_ps_017:608; SSE-SLOW: # %bb.0:609; SSE-SLOW-NEXT: movaps %xmm0, %xmm1610; SSE-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]611; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,2,2,2]612; SSE-SLOW-NEXT: addps %xmm1, %xmm0613; SSE-SLOW-NEXT: retq614;615; SSE-FAST-LABEL: add_ps_017:616; SSE-FAST: # %bb.0:617; SSE-FAST-NEXT: haddps %xmm0, %xmm0618; SSE-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]619; SSE-FAST-NEXT: retq620;621; AVX-SLOW-LABEL: add_ps_017:622; AVX-SLOW: # %bb.0:623; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]624; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,2,2]625; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0626; AVX-SLOW-NEXT: retq627;628; AVX-FAST-LABEL: add_ps_017:629; AVX-FAST: # %bb.0:630; AVX-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0631; AVX-FAST-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]632; AVX-FAST-NEXT: retq633 %l = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>634 %add = fadd <4 x float> %l, %x635 %shuffle2 = shufflevector <4 x float> %add, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef>636 ret <4 x float> %shuffle2637}638 639define <4 x float> @add_ps_018(<4 x float> %x) {640; SSE-LABEL: add_ps_018:641; SSE: # %bb.0:642; SSE-NEXT: haddps %xmm0, %xmm0643; SSE-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]644; SSE-NEXT: retq645;646; AVX1-SLOW-LABEL: add_ps_018:647; AVX1-SLOW: # %bb.0:648; AVX1-SLOW-NEXT: vhaddps %xmm0, %xmm0, %xmm0649; AVX1-SLOW-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]650; AVX1-SLOW-NEXT: retq651;652; AVX1-FAST-LABEL: add_ps_018:653; AVX1-FAST: # %bb.0:654; AVX1-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0655; AVX1-FAST-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]656; AVX1-FAST-NEXT: retq657;658; AVX512-LABEL: add_ps_018:659; AVX512: # %bb.0:660; AVX512-NEXT: vhaddps %xmm0, %xmm0, %xmm0661; AVX512-NEXT: vbroadcastss %xmm0, %xmm0662; AVX512-NEXT: retq663 %l = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 undef>664 %r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 undef>665 %add = fadd <4 x float> %l, %r666 %shuffle2 = shufflevector <4 x float> %add, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>667 ret <4 x float> %shuffle2668}669 670define <4 x double> @add_pd_011(<4 x double> %0, <4 x double> %1) {671; SSE-SLOW-LABEL: add_pd_011:672; SSE-SLOW: # %bb.0:673; SSE-SLOW-NEXT: movapd %xmm2, %xmm1674; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]675; SSE-SLOW-NEXT: movapd %xmm0, %xmm3676; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]677; SSE-SLOW-NEXT: addpd %xmm3, %xmm0678; SSE-SLOW-NEXT: addpd %xmm2, %xmm1679; SSE-SLOW-NEXT: retq680;681; SSE-FAST-LABEL: add_pd_011:682; SSE-FAST: # %bb.0:683; SSE-FAST-NEXT: movapd %xmm2, %xmm1684; SSE-FAST-NEXT: haddpd %xmm0, %xmm0685; SSE-FAST-NEXT: haddpd %xmm2, %xmm1686; SSE-FAST-NEXT: retq687;688; AVX1-SLOW-LABEL: add_pd_011:689; AVX1-SLOW: # %bb.0:690; AVX1-SLOW-NEXT: vhaddpd %xmm1, %xmm0, %xmm0691; AVX1-SLOW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]692; AVX1-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0693; AVX1-SLOW-NEXT: retq694;695; AVX1-FAST-LABEL: add_pd_011:696; AVX1-FAST: # %bb.0:697; AVX1-FAST-NEXT: vhaddpd %xmm0, %xmm1, %xmm2698; AVX1-FAST-NEXT: vhaddpd %xmm1, %xmm0, %xmm0699; AVX1-FAST-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0700; AVX1-FAST-NEXT: retq701;702; AVX512-LABEL: add_pd_011:703; AVX512: # %bb.0:704; AVX512-NEXT: vhaddpd %xmm1, %xmm0, %xmm0705; AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3]706; AVX512-NEXT: retq707 %3 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 0, i32 undef, i32 4, i32 undef>708 %4 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 1, i32 undef, i32 5, i32 undef>709 %5 = fadd <4 x double> %3, %4710 %6 = shufflevector <4 x double> %5, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>711 ret <4 x double> %6712}713 714define <4 x float> @v8f32_inputs_v4f32_output_0101(<8 x float> %a, <8 x float> %b) {715; SSE-LABEL: v8f32_inputs_v4f32_output_0101:716; SSE: # %bb.0:717; SSE-NEXT: haddps %xmm2, %xmm0718; SSE-NEXT: retq719;720; AVX-LABEL: v8f32_inputs_v4f32_output_0101:721; AVX: # %bb.0:722; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0723; AVX-NEXT: vzeroupper724; AVX-NEXT: retq725 %a0 = extractelement <8 x float> %a, i32 0726 %a1 = extractelement <8 x float> %a, i32 1727 %b0 = extractelement <8 x float> %b, i32 0728 %b1 = extractelement <8 x float> %b, i32 1729 %add0 = fadd float %a0, %a1730 %add2 = fadd float %b0, %b1731 %r0 = insertelement <4 x float> undef, float %add0, i32 0732 %r = insertelement <4 x float> %r0, float %add2, i32 2733 ret <4 x float> %r734}735 736define <4 x float> @v8f32_input0_v4f32_output_0123(<8 x float> %a, <4 x float> %b) {737; SSE-LABEL: v8f32_input0_v4f32_output_0123:738; SSE: # %bb.0:739; SSE-NEXT: haddps %xmm2, %xmm0740; SSE-NEXT: retq741;742; AVX-LABEL: v8f32_input0_v4f32_output_0123:743; AVX: # %bb.0:744; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0745; AVX-NEXT: vzeroupper746; AVX-NEXT: retq747 %a0 = extractelement <8 x float> %a, i32 0748 %a1 = extractelement <8 x float> %a, i32 1749 %b2 = extractelement <4 x float> %b, i32 2750 %b3 = extractelement <4 x float> %b, i32 3751 %add0 = fadd float %a0, %a1752 %add3 = fadd float %b2, %b3753 %r0 = insertelement <4 x float> undef, float %add0, i32 0754 %r = insertelement <4 x float> %r0, float %add3, i32 3755 ret <4 x float> %r756}757 758define <4 x float> @v8f32_input1_v4f32_output_2301(<4 x float> %a, <8 x float> %b) {759; SSE-LABEL: v8f32_input1_v4f32_output_2301:760; SSE: # %bb.0:761; SSE-NEXT: haddps %xmm1, %xmm0762; SSE-NEXT: retq763;764; AVX-LABEL: v8f32_input1_v4f32_output_2301:765; AVX: # %bb.0:766; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0767; AVX-NEXT: vzeroupper768; AVX-NEXT: retq769 %a2 = extractelement <4 x float> %a, i32 2770 %a3 = extractelement <4 x float> %a, i32 3771 %b0 = extractelement <8 x float> %b, i32 0772 %b1 = extractelement <8 x float> %b, i32 1773 %add1 = fadd float %a2, %a3774 %add2 = fadd float %b0, %b1775 %r1 = insertelement <4 x float> undef, float %add1, i32 1776 %r = insertelement <4 x float> %r1, float %add2, i32 2777 ret <4 x float> %r778}779 780define <4 x float> @v8f32_inputs_v4f32_output_2323(<8 x float> %a, <8 x float> %b) {781; SSE-LABEL: v8f32_inputs_v4f32_output_2323:782; SSE: # %bb.0:783; SSE-NEXT: haddps %xmm2, %xmm0784; SSE-NEXT: retq785;786; AVX-LABEL: v8f32_inputs_v4f32_output_2323:787; AVX: # %bb.0:788; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0789; AVX-NEXT: vzeroupper790; AVX-NEXT: retq791 %a2 = extractelement <8 x float> %a, i32 2792 %a3 = extractelement <8 x float> %a, i32 3793 %b2 = extractelement <8 x float> %b, i32 2794 %b3 = extractelement <8 x float> %b, i32 3795 %add1 = fadd float %a2, %a3796 %add3 = fadd float %b2, %b3797 %r1 = insertelement <4 x float> undef, float %add1, i32 1798 %r = insertelement <4 x float> %r1, float %add3, i32 3799 ret <4 x float> %r800}801 802define <4 x float> @v16f32_inputs_v4f32_output_0123(<16 x float> %a, <16 x float> %b) {803; SSE-LABEL: v16f32_inputs_v4f32_output_0123:804; SSE: # %bb.0:805; SSE-NEXT: haddps %xmm4, %xmm0806; SSE-NEXT: retq807;808; AVX1-SLOW-LABEL: v16f32_inputs_v4f32_output_0123:809; AVX1-SLOW: # %bb.0:810; AVX1-SLOW-NEXT: vhaddps %xmm2, %xmm0, %xmm0811; AVX1-SLOW-NEXT: vzeroupper812; AVX1-SLOW-NEXT: retq813;814; AVX1-FAST-LABEL: v16f32_inputs_v4f32_output_0123:815; AVX1-FAST: # %bb.0:816; AVX1-FAST-NEXT: vhaddps %xmm2, %xmm0, %xmm0817; AVX1-FAST-NEXT: vzeroupper818; AVX1-FAST-NEXT: retq819;820; AVX512-LABEL: v16f32_inputs_v4f32_output_0123:821; AVX512: # %bb.0:822; AVX512-NEXT: vhaddps %xmm1, %xmm0, %xmm0823; AVX512-NEXT: vzeroupper824; AVX512-NEXT: retq825 %a0 = extractelement <16 x float> %a, i32 0826 %a1 = extractelement <16 x float> %a, i32 1827 %b2 = extractelement <16 x float> %b, i32 2828 %b3 = extractelement <16 x float> %b, i32 3829 %add0 = fadd float %a0, %a1830 %add3 = fadd float %b2, %b3831 %r0 = insertelement <4 x float> undef, float %add0, i32 0832 %r = insertelement <4 x float> %r0, float %add3, i32 3833 ret <4 x float> %r834}835 836define <8 x float> @v16f32_inputs_v8f32_output_4567(<16 x float> %a, <16 x float> %b) {837; SSE-LABEL: v16f32_inputs_v8f32_output_4567:838; SSE: # %bb.0:839; SSE-NEXT: haddps %xmm5, %xmm1840; SSE-NEXT: retq841;842; AVX1-SLOW-LABEL: v16f32_inputs_v8f32_output_4567:843; AVX1-SLOW: # %bb.0:844; AVX1-SLOW-NEXT: vhaddps %ymm2, %ymm0, %ymm0845; AVX1-SLOW-NEXT: retq846;847; AVX1-FAST-LABEL: v16f32_inputs_v8f32_output_4567:848; AVX1-FAST: # %bb.0:849; AVX1-FAST-NEXT: vhaddps %ymm2, %ymm0, %ymm0850; AVX1-FAST-NEXT: retq851;852; AVX512-LABEL: v16f32_inputs_v8f32_output_4567:853; AVX512: # %bb.0:854; AVX512-NEXT: vhaddps %ymm1, %ymm0, %ymm0855; AVX512-NEXT: retq856 %a4 = extractelement <16 x float> %a, i32 4857 %a5 = extractelement <16 x float> %a, i32 5858 %b6 = extractelement <16 x float> %b, i32 6859 %b7 = extractelement <16 x float> %b, i32 7860 %add4 = fadd float %a4, %a5861 %add7 = fadd float %b6, %b7862 %r4 = insertelement <8 x float> undef, float %add4, i32 4863 %r = insertelement <8 x float> %r4, float %add7, i32 7864 ret <8 x float> %r865}866 867define <8 x float> @PR40243(<8 x float> %a, <8 x float> %b) {868; SSE-LABEL: PR40243:869; SSE: # %bb.0:870; SSE-NEXT: haddps %xmm3, %xmm1871; SSE-NEXT: retq872;873; AVX-LABEL: PR40243:874; AVX: # %bb.0:875; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0876; AVX-NEXT: retq877 %a4 = extractelement <8 x float> %a, i32 4878 %a5 = extractelement <8 x float> %a, i32 5879 %add4 = fadd float %a4, %a5880 %b6 = extractelement <8 x float> %b, i32 6881 %b7 = extractelement <8 x float> %b, i32 7882 %add7 = fadd float %b6, %b7883 %r4 = insertelement <8 x float> undef, float %add4, i32 4884 %r = insertelement <8 x float> %r4, float %add7, i32 7885 ret <8 x float> %r886}887 888define <4 x double> @PR44694(<4 x double> %0, <4 x double> %1) {889; SSE-SLOW-LABEL: PR44694:890; SSE-SLOW: # %bb.0:891; SSE-SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]892; SSE-SLOW-NEXT: haddpd %xmm3, %xmm2893; SSE-SLOW-NEXT: addpd %xmm1, %xmm0894; SSE-SLOW-NEXT: movapd %xmm2, %xmm1895; SSE-SLOW-NEXT: retq896;897; SSE-FAST-LABEL: PR44694:898; SSE-FAST: # %bb.0:899; SSE-FAST-NEXT: movapd %xmm1, %xmm0900; SSE-FAST-NEXT: haddpd %xmm3, %xmm2901; SSE-FAST-NEXT: haddpd %xmm1, %xmm0902; SSE-FAST-NEXT: movapd %xmm2, %xmm1903; SSE-FAST-NEXT: retq904;905; AVX1-SLOW-LABEL: PR44694:906; AVX1-SLOW: # %bb.0:907; AVX1-SLOW-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]908; AVX1-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1909; AVX1-SLOW-NEXT: vhaddpd %ymm0, %ymm1, %ymm0910; AVX1-SLOW-NEXT: retq911;912; AVX1-FAST-LABEL: PR44694:913; AVX1-FAST: # %bb.0:914; AVX1-FAST-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]915; AVX1-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1916; AVX1-FAST-NEXT: vhaddpd %ymm0, %ymm1, %ymm0917; AVX1-FAST-NEXT: retq918;919; AVX512-LABEL: PR44694:920; AVX512: # %bb.0:921; AVX512-NEXT: vhaddpd %ymm1, %ymm0, %ymm0922; AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]923; AVX512-NEXT: retq924 %3 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>925 %4 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>926 %5 = fadd <4 x double> %3, %4927 ret <4 x double> %5928}929 930define <4 x float> @PR45747_1(<4 x float> %a, <4 x float> %b) nounwind {931; SSE-SLOW-LABEL: PR45747_1:932; SSE-SLOW: # %bb.0:933; SSE-SLOW-NEXT: movaps %xmm0, %xmm1934; SSE-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,2],xmm0[2,2]935; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]936; SSE-SLOW-NEXT: addps %xmm1, %xmm0937; SSE-SLOW-NEXT: retq938;939; SSE-FAST-LABEL: PR45747_1:940; SSE-FAST: # %bb.0:941; SSE-FAST-NEXT: haddps %xmm0, %xmm0942; SSE-FAST-NEXT: retq943;944; AVX-SLOW-LABEL: PR45747_1:945; AVX-SLOW: # %bb.0:946; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,2,2,2]947; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]948; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0949; AVX-SLOW-NEXT: retq950;951; AVX-FAST-LABEL: PR45747_1:952; AVX-FAST: # %bb.0:953; AVX-FAST-NEXT: vhaddps %xmm0, %xmm0, %xmm0954; AVX-FAST-NEXT: retq955 %t0 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 3, i32 undef>956 %t1 = fadd <4 x float> %t0, %a957 %shuffle = shufflevector <4 x float> %t1, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>958 ret <4 x float> %shuffle959}960 961define <4 x float> @PR45747_2(<4 x float> %a, <4 x float> %b) nounwind {962; SSE-SLOW-LABEL: PR45747_2:963; SSE-SLOW: # %bb.0:964; SSE-SLOW-NEXT: movaps %xmm1, %xmm0965; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]966; SSE-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]967; SSE-SLOW-NEXT: addps %xmm1, %xmm0968; SSE-SLOW-NEXT: retq969;970; SSE-FAST-LABEL: PR45747_2:971; SSE-FAST: # %bb.0:972; SSE-FAST-NEXT: haddps %xmm1, %xmm1973; SSE-FAST-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]974; SSE-FAST-NEXT: retq975;976; AVX-SLOW-LABEL: PR45747_2:977; AVX-SLOW: # %bb.0:978; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]979; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[3,3,1,1]980; AVX-SLOW-NEXT: vaddps %xmm0, %xmm1, %xmm0981; AVX-SLOW-NEXT: retq982;983; AVX-FAST-LABEL: PR45747_2:984; AVX-FAST: # %bb.0:985; AVX-FAST-NEXT: vhaddps %xmm1, %xmm1, %xmm0986; AVX-FAST-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]987; AVX-FAST-NEXT: retq988 %t0 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 3, i32 undef>989 %t1 = fadd <4 x float> %t0, %b990 %shuffle = shufflevector <4 x float> %t1, <4 x float> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>991 ret <4 x float> %shuffle992}993 994define <4 x float> @PR34724_add_v4f32_u123(<4 x float> %0, <4 x float> %1) {995; SSE-LABEL: PR34724_add_v4f32_u123:996; SSE: # %bb.0:997; SSE-NEXT: haddps %xmm1, %xmm0998; SSE-NEXT: retq999;1000; AVX-LABEL: PR34724_add_v4f32_u123:1001; AVX: # %bb.0:1002; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm01003; AVX-NEXT: retq1004 %3 = shufflevector <4 x float> %0, <4 x float> %1, <2 x i32> <i32 2, i32 4>1005 %4 = shufflevector <4 x float> %0, <4 x float> %1, <2 x i32> <i32 3, i32 5>1006 %5 = fadd <2 x float> %3, %41007 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>1008 %7 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>1009 %8 = fadd <4 x float> %7, %11010 %9 = shufflevector <4 x float> %6, <4 x float> %8, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>1011 ret <4 x float> %91012}1013 1014define <4 x float> @PR34724_add_v4f32_0u23(<4 x float> %0, <4 x float> %1) {1015; SSE-SLOW-LABEL: PR34724_add_v4f32_0u23:1016; SSE-SLOW: # %bb.0:1017; SSE-SLOW-NEXT: movaps %xmm0, %xmm21018; SSE-SLOW-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]1019; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]1020; SSE-SLOW-NEXT: addps %xmm2, %xmm01021; SSE-SLOW-NEXT: movsldup {{.*#+}} xmm2 = xmm1[0,0,2,2]1022; SSE-SLOW-NEXT: addps %xmm1, %xmm21023; SSE-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm0[2,0]1024; SSE-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]1025; SSE-SLOW-NEXT: retq1026;1027; SSE-FAST-LABEL: PR34724_add_v4f32_0u23:1028; SSE-FAST: # %bb.0:1029; SSE-FAST-NEXT: haddps %xmm1, %xmm01030; SSE-FAST-NEXT: retq1031;1032; AVX-SLOW-LABEL: PR34724_add_v4f32_0u23:1033; AVX-SLOW: # %bb.0:1034; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,1],xmm1[0,3]1035; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,2]1036; AVX-SLOW-NEXT: vaddps %xmm2, %xmm0, %xmm01037; AVX-SLOW-NEXT: retq1038;1039; AVX-FAST-LABEL: PR34724_add_v4f32_0u23:1040; AVX-FAST: # %bb.0:1041; AVX-FAST-NEXT: vhaddps %xmm1, %xmm0, %xmm01042; AVX-FAST-NEXT: retq1043 %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>1044 %4 = fadd <4 x float> %3, %01045 %5 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>1046 %6 = fadd <4 x float> %5, %11047 %7 = shufflevector <4 x float> %4, <4 x float> %6, <4 x i32> <i32 0, i32 undef, i32 4, i32 undef>1048 %8 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>1049 %9 = fadd <4 x float> %8, %11050 %10 = shufflevector <4 x float> %7, <4 x float> %9, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>1051 ret <4 x float> %101052}1053 1054define <4 x float> @PR34724_add_v4f32_01u3(<4 x float> %0, <4 x float> %1) {1055; SSE-LABEL: PR34724_add_v4f32_01u3:1056; SSE: # %bb.0:1057; SSE-NEXT: haddps %xmm1, %xmm01058; SSE-NEXT: retq1059;1060; AVX-LABEL: PR34724_add_v4f32_01u3:1061; AVX: # %bb.0:1062; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm01063; AVX-NEXT: retq1064 %3 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 0, i32 2>1065 %4 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 1, i32 3>1066 %5 = fadd <2 x float> %3, %41067 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>1068 %7 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>1069 %8 = fadd <4 x float> %7, %11070 %9 = shufflevector <4 x float> %6, <4 x float> %8, <4 x i32> <i32 0, i32 1, i32 undef, i32 7>1071 ret <4 x float> %91072}1073 1074define <4 x float> @PR34724_add_v4f32_012u(<4 x float> %0, <4 x float> %1) {1075; SSE-LABEL: PR34724_add_v4f32_012u:1076; SSE: # %bb.0:1077; SSE-NEXT: haddps %xmm1, %xmm01078; SSE-NEXT: retq1079;1080; AVX-LABEL: PR34724_add_v4f32_012u:1081; AVX: # %bb.0:1082; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm01083; AVX-NEXT: retq1084 %3 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 0, i32 2>1085 %4 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 1, i32 3>1086 %5 = fadd <2 x float> %3, %41087 %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>1088 %7 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>1089 %8 = fadd <4 x float> %7, %11090 %9 = shufflevector <4 x float> %6, <4 x float> %8, <4 x i32> <i32 0, i32 1, i32 4, i32 undef>1091 ret <4 x float> %91092}1093 1094define <4 x double> @PR34724_add_v4f64_u123(<4 x double> %0, <4 x double> %1) {1095; SSE-SLOW-LABEL: PR34724_add_v4f64_u123:1096; SSE-SLOW: # %bb.0:1097; SSE-SLOW-NEXT: haddpd %xmm2, %xmm11098; SSE-SLOW-NEXT: movapd %xmm3, %xmm21099; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1]1100; SSE-SLOW-NEXT: addsd %xmm3, %xmm21101; SSE-SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]1102; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm2[0]1103; SSE-SLOW-NEXT: retq1104;1105; SSE-FAST-LABEL: PR34724_add_v4f64_u123:1106; SSE-FAST: # %bb.0:1107; SSE-FAST-NEXT: movapd %xmm1, %xmm01108; SSE-FAST-NEXT: haddpd %xmm3, %xmm21109; SSE-FAST-NEXT: haddpd %xmm1, %xmm01110; SSE-FAST-NEXT: movapd %xmm2, %xmm11111; SSE-FAST-NEXT: retq1112;1113; AVX-SLOW-LABEL: PR34724_add_v4f64_u123:1114; AVX-SLOW: # %bb.0:1115; AVX-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm01116; AVX-SLOW-NEXT: vhaddpd %xmm1, %xmm0, %xmm01117; AVX-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm11118; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]1119; AVX-SLOW-NEXT: vaddsd %xmm2, %xmm1, %xmm11120; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1],xmm1[0]1121; AVX-SLOW-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]1122; AVX-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01123; AVX-SLOW-NEXT: retq1124;1125; AVX-FAST-LABEL: PR34724_add_v4f64_u123:1126; AVX-FAST: # %bb.0:1127; AVX-FAST-NEXT: vextractf128 $1, %ymm0, %xmm21128; AVX-FAST-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]1129; AVX-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm11130; AVX-FAST-NEXT: vhaddpd %ymm0, %ymm1, %ymm01131; AVX-FAST-NEXT: retq1132 %3 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 2, i32 4>1133 %4 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 3, i32 5>1134 %5 = fadd <2 x double> %3, %41135 %6 = extractelement <2 x double> %5, i32 01136 %7 = insertelement <4 x double> undef, double %6, i32 11137 %8 = extractelement <2 x double> %5, i32 11138 %9 = insertelement <4 x double> %7, double %8, i32 21139 %10 = extractelement <4 x double> %1, i32 21140 %11 = extractelement <4 x double> %1, i32 31141 %12 = fadd double %10, %111142 %13 = insertelement <4 x double> %9, double %12, i32 31143 ret <4 x double> %131144}1145 1146define <4 x double> @PR34724_add_v4f64_0u23(<4 x double> %0, <4 x double> %1) {1147; SSE-SLOW-LABEL: PR34724_add_v4f64_0u23:1148; SSE-SLOW: # %bb.0:1149; SSE-SLOW-NEXT: haddpd %xmm2, %xmm01150; SSE-SLOW-NEXT: movapd %xmm3, %xmm21151; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1]1152; SSE-SLOW-NEXT: addsd %xmm3, %xmm21153; SSE-SLOW-NEXT: movapd %xmm0, %xmm11154; SSE-SLOW-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1],xmm2[0]1155; SSE-SLOW-NEXT: retq1156;1157; SSE-FAST-LABEL: PR34724_add_v4f64_0u23:1158; SSE-FAST: # %bb.0:1159; SSE-FAST-NEXT: movapd %xmm2, %xmm11160; SSE-FAST-NEXT: haddpd %xmm2, %xmm01161; SSE-FAST-NEXT: haddpd %xmm3, %xmm11162; SSE-FAST-NEXT: retq1163;1164; AVX-SLOW-LABEL: PR34724_add_v4f64_0u23:1165; AVX-SLOW: # %bb.0:1166; AVX-SLOW-NEXT: vhaddpd %xmm1, %xmm0, %xmm01167; AVX-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm11168; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]1169; AVX-SLOW-NEXT: vaddsd %xmm2, %xmm1, %xmm11170; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1],xmm1[0]1171; AVX-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01172; AVX-SLOW-NEXT: retq1173;1174; AVX-FAST-LABEL: PR34724_add_v4f64_0u23:1175; AVX-FAST: # %bb.0:1176; AVX-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01177; AVX-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm01178; AVX-FAST-NEXT: retq1179 %3 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 0, i32 4>1180 %4 = shufflevector <4 x double> %0, <4 x double> %1, <2 x i32> <i32 1, i32 5>1181 %5 = fadd <2 x double> %3, %41182 %6 = extractelement <2 x double> %5, i32 01183 %7 = insertelement <4 x double> undef, double %6, i32 01184 %8 = extractelement <2 x double> %5, i32 11185 %9 = insertelement <4 x double> %7, double %8, i32 21186 %10 = extractelement <4 x double> %1, i32 21187 %11 = extractelement <4 x double> %1, i32 31188 %12 = fadd double %10, %111189 %13 = insertelement <4 x double> %9, double %12, i32 31190 ret <4 x double> %131191}1192 1193define <4 x double> @PR34724_add_v4f64_01u3(<4 x double> %0, <4 x double> %1) {1194; SSE-SLOW-LABEL: PR34724_add_v4f64_01u3:1195; SSE-SLOW: # %bb.0:1196; SSE-SLOW-NEXT: haddpd %xmm1, %xmm01197; SSE-SLOW-NEXT: movapd %xmm3, %xmm11198; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1]1199; SSE-SLOW-NEXT: addsd %xmm3, %xmm11200; SSE-SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0]1201; SSE-SLOW-NEXT: retq1202;1203; SSE-FAST-LABEL: PR34724_add_v4f64_01u3:1204; SSE-FAST: # %bb.0:1205; SSE-FAST-NEXT: haddpd %xmm1, %xmm01206; SSE-FAST-NEXT: haddpd %xmm3, %xmm31207; SSE-FAST-NEXT: movapd %xmm3, %xmm11208; SSE-FAST-NEXT: retq1209;1210; AVX-SLOW-LABEL: PR34724_add_v4f64_01u3:1211; AVX-SLOW: # %bb.0:1212; AVX-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm21213; AVX-SLOW-NEXT: vhaddpd %xmm2, %xmm0, %xmm01214; AVX-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm11215; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]1216; AVX-SLOW-NEXT: vaddsd %xmm2, %xmm1, %xmm11217; AVX-SLOW-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]1218; AVX-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01219; AVX-SLOW-NEXT: retq1220;1221; AVX1-FAST-LABEL: PR34724_add_v4f64_01u3:1222; AVX1-FAST: # %bb.0:1223; AVX1-FAST-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]1224; AVX1-FAST-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]1225; AVX1-FAST-NEXT: vhaddpd %ymm2, %ymm0, %ymm01226; AVX1-FAST-NEXT: retq1227;1228; AVX512-FAST-LABEL: PR34724_add_v4f64_01u3:1229; AVX512-FAST: # %bb.0:1230; AVX512-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm01231; AVX512-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3]1232; AVX512-FAST-NEXT: retq1233 %3 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 0, i32 2>1234 %4 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 1, i32 3>1235 %5 = fadd <2 x double> %3, %41236 %6 = extractelement <2 x double> %5, i32 01237 %7 = insertelement <4 x double> undef, double %6, i32 01238 %8 = extractelement <2 x double> %5, i32 11239 %9 = insertelement <4 x double> %7, double %8, i32 11240 %10 = extractelement <4 x double> %1, i32 21241 %11 = extractelement <4 x double> %1, i32 31242 %12 = fadd double %10, %111243 %13 = insertelement <4 x double> %9, double %12, i32 31244 ret <4 x double> %131245}1246 1247define <4 x double> @PR34724_add_v4f64_012u(<4 x double> %0, <4 x double> %1) {1248; SSE-SLOW-LABEL: PR34724_add_v4f64_012u:1249; SSE-SLOW: # %bb.0:1250; SSE-SLOW-NEXT: haddpd %xmm1, %xmm01251; SSE-SLOW-NEXT: movapd %xmm2, %xmm11252; SSE-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]1253; SSE-SLOW-NEXT: addsd %xmm2, %xmm11254; SSE-SLOW-NEXT: retq1255;1256; SSE-FAST-LABEL: PR34724_add_v4f64_012u:1257; SSE-FAST: # %bb.0:1258; SSE-FAST-NEXT: haddpd %xmm1, %xmm01259; SSE-FAST-NEXT: haddpd %xmm2, %xmm21260; SSE-FAST-NEXT: movapd %xmm2, %xmm11261; SSE-FAST-NEXT: retq1262;1263; AVX-SLOW-LABEL: PR34724_add_v4f64_012u:1264; AVX-SLOW: # %bb.0:1265; AVX-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm21266; AVX-SLOW-NEXT: vhaddpd %xmm2, %xmm0, %xmm01267; AVX-SLOW-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]1268; AVX-SLOW-NEXT: vaddsd %xmm2, %xmm1, %xmm11269; AVX-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01270; AVX-SLOW-NEXT: retq1271;1272; AVX-FAST-LABEL: PR34724_add_v4f64_012u:1273; AVX-FAST: # %bb.0:1274; AVX-FAST-NEXT: vextractf128 $1, %ymm0, %xmm21275; AVX-FAST-NEXT: vhaddpd %xmm2, %xmm0, %xmm01276; AVX-FAST-NEXT: vhaddpd %xmm1, %xmm1, %xmm11277; AVX-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01278; AVX-FAST-NEXT: retq1279 %3 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 0, i32 2>1280 %4 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 1, i32 3>1281 %5 = fadd <2 x double> %3, %41282 %6 = extractelement <2 x double> %5, i32 01283 %7 = insertelement <4 x double> undef, double %6, i32 01284 %8 = extractelement <2 x double> %5, i32 11285 %9 = insertelement <4 x double> %7, double %8, i32 11286 %10 = extractelement <4 x double> %1, i32 01287 %11 = extractelement <4 x double> %1, i32 11288 %12 = fadd double %10, %111289 %13 = insertelement <4 x double> %9, double %12, i32 21290 ret <4 x double> %131291}1292