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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -verify-machineinstrs -no-integrated-as | FileCheck %s3 4; There should be no stack manipulations between the inline asm and ret.5define x86_fp80 @test1() nounwind {6; CHECK-LABEL: test1:7; CHECK: ## %bb.0:8; CHECK-NEXT: ## InlineAsm Start9; CHECK-NEXT: fld010; CHECK-NEXT: ## InlineAsm End11; CHECK-NEXT: retl12 %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"()13 ret x86_fp80 %tmp8514}15 16define double @test2() nounwind {17; CHECK-LABEL: test2:18; CHECK: ## %bb.0:19; CHECK-NEXT: ## InlineAsm Start20; CHECK-NEXT: fld021; CHECK-NEXT: ## InlineAsm End22; CHECK-NEXT: retl23 %tmp85 = call double asm sideeffect "fld0", "={st(0)}"()24 ret double %tmp8525}26 27; Setting up argument in st(0) should be a single fld.28; Asm consumes stack, nothing should be popped.29define void @test3(x86_fp80 %X) nounwind {30; CHECK-LABEL: test3:31; CHECK: ## %bb.0:32; CHECK-NEXT: fldt {{[0-9]+}}(%esp)33; CHECK-NEXT: ## InlineAsm Start34; CHECK-NEXT: frob35; CHECK-NEXT: ## InlineAsm End36; CHECK-NEXT: retl37 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X)38 ret void39}40 41define void @test4(double %X) nounwind {42; CHECK-LABEL: test4:43; CHECK: ## %bb.0:44; CHECK-NEXT: fldl {{[0-9]+}}(%esp)45; CHECK-NEXT: ## InlineAsm Start46; CHECK-NEXT: frob47; CHECK-NEXT: ## InlineAsm End48; CHECK-NEXT: retl49 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %X)50 ret void51}52 53; Same as test3/4, but using value from fadd.54; The fadd can be done in xmm or x87 regs - we don't test that.55define void @test5(double %X) nounwind {56; CHECK-LABEL: test5:57; CHECK: ## %bb.0:58; CHECK-NEXT: fldl {{[0-9]+}}(%esp)59; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}60; CHECK-NEXT: ## InlineAsm Start61; CHECK-NEXT: frob62; CHECK-NEXT: ## InlineAsm End63; CHECK-NEXT: retl64 %Y = fadd double %X, 123.065 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %Y)66 ret void67}68 69define void @test6(double %A, double %B, double %C, double %D, double %E) nounwind {70; CHECK-LABEL: test6:71; CHECK: ## %bb.0: ## %entry72; CHECK-NEXT: fldl {{[0-9]+}}(%esp)73; CHECK-NEXT: fldl {{[0-9]+}}(%esp)74; CHECK-NEXT: fldl {{[0-9]+}}(%esp)75; CHECK-NEXT: fldl {{[0-9]+}}(%esp)76; CHECK-NEXT: fldl {{[0-9]+}}(%esp)77; CHECK-NEXT: ## InlineAsm Start78; CHECK-NEXT: foo %st %st79; CHECK-NEXT: ## InlineAsm End80; CHECK-NEXT: fstp %st(0)81; CHECK-NEXT: ## InlineAsm Start82; CHECK-NEXT: bar %st(1) %st83; CHECK-NEXT: ## InlineAsm End84; CHECK-NEXT: fstp %st(1)85; CHECK-NEXT: fstp %st(0)86; CHECK-NEXT: ## InlineAsm Start87; CHECK-NEXT: baz %st(1) %st88; CHECK-NEXT: ## InlineAsm End89; CHECK-NEXT: fstp %st(0)90; CHECK-NEXT: ## InlineAsm Start91; CHECK-NEXT: baz %st92; CHECK-NEXT: ## InlineAsm End93; CHECK-NEXT: fstp %st(0)94; CHECK-NEXT: retl95entry:96; Uses the same value twice, should have one fstp after the asm.97 tail call void asm sideeffect "foo $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %A, double %A ) nounwind98; Uses two different values, should be in st(0)/st(1) and both be popped.99 tail call void asm sideeffect "bar $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %B, double %C ) nounwind100; Uses two different values, one of which isn't killed in this asm, it should not be popped after the asm.101 tail call void asm sideeffect "baz $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %D, double %E ) nounwind102; This is the last use of %D, so it should be popped after.103 tail call void asm sideeffect "baz $0", "f,~{dirflag},~{fpsr},~{flags}"( double %D ) nounwind104 ret void105}106 107; PR4185108; Passing a non-killed value to asm in {st}.109; Make sure it is duped before.110; asm kills st(0), so we shouldn't pop anything111; A valid alternative would be to remat the constant pool load before each112; inline asm.113define void @testPR4185() nounwind {114; CHECK-LABEL: testPR4185:115; CHECK: ## %bb.0: ## %return116; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}117; CHECK-NEXT: fld %st(0)118; CHECK-NEXT: ## InlineAsm Start119; CHECK-NEXT: fistpl %st120; CHECK-NEXT: ## InlineAsm End121; CHECK-NEXT: ## InlineAsm Start122; CHECK-NEXT: fistpl %st123; CHECK-NEXT: ## InlineAsm End124; CHECK-NEXT: retl125return:126 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06)127 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06)128 ret void129}130 131; Passing a non-killed value through asm in {st}.132; Make sure it is not duped before.133; Second asm kills st(0), so we shouldn't pop anything134; A valid alternative would be to remat the constant pool load before each inline asm.135define void @testPR4185b() nounwind {136; CHECK-LABEL: testPR4185b:137; CHECK: ## %bb.0: ## %return138; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}139; CHECK-NEXT: ## InlineAsm Start140; CHECK-NEXT: fistl %st141; CHECK-NEXT: ## InlineAsm End142; CHECK-NEXT: ## InlineAsm Start143; CHECK-NEXT: fistpl %st144; CHECK-NEXT: ## InlineAsm End145; CHECK-NEXT: retl146return:147 call void asm sideeffect "fistl $0", "{st}"(double 1.000000e+06)148 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06)149 ret void150}151 152; PR4459153; The return value from ceil must be duped before being consumed by asm.154define void @testPR4459(x86_fp80 %a) nounwind {155; CHECK-LABEL: testPR4459:156; CHECK: ## %bb.0: ## %entry157; CHECK-NEXT: subl $28, %esp158; CHECK-NEXT: fldt {{[0-9]+}}(%esp)159; CHECK-NEXT: fstpt (%esp)160; CHECK-NEXT: calll _ceil161; CHECK-NEXT: fld %st(0)162; CHECK-NEXT: fxch %st(1)163; CHECK-NEXT: ## InlineAsm Start164; CHECK-NEXT: fistpl %st165; CHECK-NEXT: ## InlineAsm End166; CHECK-NEXT: fstpt (%esp)167; CHECK-NEXT: calll _test3168; CHECK-NEXT: addl $28, %esp169; CHECK-NEXT: retl170entry:171 %0 = call x86_fp80 @ceil(x86_fp80 %a)172 call void asm sideeffect "fistpl $0", "{st},~{st}"( x86_fp80 %0)173 call void @test3(x86_fp80 %0 )174 ret void175}176declare x86_fp80 @ceil(x86_fp80)177 178; PR4484179; test1 leaves a value on the stack that is needed after the asm.180; Load %a from stack after ceil181; Set up call to test.182define void @testPR4484(x86_fp80 %a) nounwind {183; CHECK-LABEL: testPR4484:184; CHECK: ## %bb.0: ## %entry185; CHECK-NEXT: subl $28, %esp186; CHECK-NEXT: fldt {{[0-9]+}}(%esp)187; CHECK-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill188; CHECK-NEXT: calll _test1189; CHECK-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload190; CHECK-NEXT: ## InlineAsm Start191; CHECK-NEXT: fistpl %st192; CHECK-NEXT: ## InlineAsm End193; CHECK-NEXT: fstpt (%esp)194; CHECK-NEXT: calll _test3195; CHECK-NEXT: addl $28, %esp196; CHECK-NEXT: retl197entry:198 %0 = call x86_fp80 @test1()199 call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a)200 call void @test3(x86_fp80 %0)201 ret void202}203 204; PR4485205define void @testPR4485(ptr %a) nounwind {206; CHECK-LABEL: testPR4485:207; CHECK: ## %bb.0: ## %entry208; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax209; CHECK-NEXT: fldt (%eax)210; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}211; CHECK-NEXT: fmul %st, %st(1)212; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}213; CHECK-NEXT: fmul %st, %st(2)214; CHECK-NEXT: fxch %st(2)215; CHECK-NEXT: ## InlineAsm Start216; CHECK-NEXT: fistpl %st217; CHECK-NEXT: ## InlineAsm End218; CHECK-NEXT: fldt (%eax)219; CHECK-NEXT: fmulp %st, %st(1)220; CHECK-NEXT: fmulp %st, %st(1)221; CHECK-NEXT: ## InlineAsm Start222; CHECK-NEXT: fistpl %st223; CHECK-NEXT: ## InlineAsm End224; CHECK-NEXT: retl225entry:226 %0 = load x86_fp80, ptr %a, align 16227 %1 = fmul x86_fp80 %0, 0xK4006B400000000000000228 %2 = fmul x86_fp80 %1, 0xK4012F424000000000000229 tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2)230 %3 = load x86_fp80, ptr %a, align 16231 %4 = fmul x86_fp80 %3, 0xK4006B400000000000000232 %5 = fmul x86_fp80 %4, 0xK4012F424000000000000233 tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5)234 ret void235}236 237; An input argument in a fixed position is implicitly popped by the asm only if238; the input argument is tied to an output register, or it is in the clobber list.239; The clobber list case is tested above.240;241; This doesn't implicitly pop the stack:242;243; void fist1(long double x, int *p) {244; asm volatile ("fistl %1" : : "t"(x), "m"(*p));245; }246define void @fist1(x86_fp80 %x, ptr %p) nounwind ssp {247; CHECK-LABEL: fist1:248; CHECK: ## %bb.0: ## %entry249; CHECK-NEXT: fldt {{[0-9]+}}(%esp)250; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax251; CHECK-NEXT: ## InlineAsm Start252; CHECK-NEXT: fistl (%eax)253; CHECK-NEXT: ## InlineAsm End254; CHECK-NEXT: fstp %st(0)255; CHECK-NEXT: retl256entry:257 tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, ptr elementtype(i32) %p) nounwind258 ret void259}260 261; Here, the input operand is tied to an output which means that is is262; implicitly popped (and then the output is implicitly pushed).263;264; long double fist2(long double x, int *p) {265; long double y;266; asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory");267; return y;268; }269define x86_fp80 @fist2(x86_fp80 %x, ptr %p) nounwind ssp {270; CHECK-LABEL: fist2:271; CHECK: ## %bb.0: ## %entry272; CHECK-NEXT: fldt {{[0-9]+}}(%esp)273; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax274; CHECK-NEXT: ## InlineAsm Start275; CHECK-NEXT: fistl (%eax)276; CHECK-NEXT: ## InlineAsm End277; CHECK-NEXT: retl278entry:279 %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, ptr elementtype(i32) %p) nounwind280 ret x86_fp80 %0281}282 283; An 'f' constraint is never implicitly popped:284;285; void fucomp1(long double x, long double y) {286; asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st");287; }288define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp {289; CHECK-LABEL: fucomp1:290; CHECK: ## %bb.0: ## %entry291; CHECK-NEXT: fldt {{[0-9]+}}(%esp)292; CHECK-NEXT: fldt {{[0-9]+}}(%esp)293; CHECK-NEXT: fxch %st(1)294; CHECK-NEXT: ## InlineAsm Start295; CHECK-NEXT: fucomp %st(1)296; CHECK-NEXT: ## InlineAsm End297; CHECK-NEXT: fstp %st(0)298; CHECK-NEXT: retl299entry:300 tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind301 ret void302}303 304; The 'u' constraint is only popped implicitly when clobbered:305;306; void fucomp2(long double x, long double y) {307; asm volatile ("fucomp %1" : : "t"(x), "u"(y) : "st");308; }309;310; void fucomp3(long double x, long double y) {311; asm volatile ("fucompp %1" : : "t"(x), "u"(y) : "st", "st(1)");312; }313;314define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp {315; CHECK-LABEL: fucomp2:316; CHECK: ## %bb.0: ## %entry317; CHECK-NEXT: fldt {{[0-9]+}}(%esp)318; CHECK-NEXT: fldt {{[0-9]+}}(%esp)319; CHECK-NEXT: fxch %st(1)320; CHECK-NEXT: ## InlineAsm Start321; CHECK-NEXT: fucomp %st(1)322; CHECK-NEXT: ## InlineAsm End323; CHECK-NEXT: fstp %st(0)324; CHECK-NEXT: retl325entry:326 tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind327 ret void328}329 330define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp {331; CHECK-LABEL: fucomp3:332; CHECK: ## %bb.0: ## %entry333; CHECK-NEXT: fldt {{[0-9]+}}(%esp)334; CHECK-NEXT: fldt {{[0-9]+}}(%esp)335; CHECK-NEXT: fxch %st(1)336; CHECK-NEXT: ## InlineAsm Start337; CHECK-NEXT: fucompp %st(1)338; CHECK-NEXT: ## InlineAsm End339; CHECK-NEXT: retl340entry:341 tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind342 ret void343}344 345; One input, two outputs, one dead output.346%complex = type { float, float }347define float @sincos1(float %x) nounwind ssp {348; CHECK-LABEL: sincos1:349; CHECK: ## %bb.0: ## %entry350; CHECK-NEXT: flds {{[0-9]+}}(%esp)351; CHECK-NEXT: ## InlineAsm Start352; CHECK-NEXT: sincos353; CHECK-NEXT: ## InlineAsm End354; CHECK-NEXT: fstp %st(1)355; CHECK-NEXT: retl356entry:357 %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind358 %asmresult = extractvalue %complex %0, 0359 ret float %asmresult360}361 362; Same thing, swapped output operands.363define float @sincos2(float %x) nounwind ssp {364; CHECK-LABEL: sincos2:365; CHECK: ## %bb.0: ## %entry366; CHECK-NEXT: flds {{[0-9]+}}(%esp)367; CHECK-NEXT: ## InlineAsm Start368; CHECK-NEXT: sincos369; CHECK-NEXT: ## InlineAsm End370; CHECK-NEXT: fstp %st(1)371; CHECK-NEXT: retl372entry:373 %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind374 %asmresult = extractvalue %complex %0, 1375 ret float %asmresult376}377 378; Clobber st(0) after it was live-out/dead from the previous asm.379; Load x, make a copy for the second asm.380; Discard dead result in st(0), bring x to the top.381; x is now in st(0) for the second asm382; Discard both results.383define float @sincos3(float %x) nounwind ssp {384; CHECK-LABEL: sincos3:385; CHECK: ## %bb.0: ## %entry386; CHECK-NEXT: flds {{[0-9]+}}(%esp)387; CHECK-NEXT: fld %st(0)388; CHECK-NEXT: ## InlineAsm Start389; CHECK-NEXT: sincos390; CHECK-NEXT: ## InlineAsm End391; CHECK-NEXT: fstp %st(0)392; CHECK-NEXT: fxch %st(1)393; CHECK-NEXT: ## InlineAsm Start394; CHECK-NEXT: sincos395; CHECK-NEXT: ## InlineAsm End396; CHECK-NEXT: fstp %st(1)397; CHECK-NEXT: fstp %st(0)398; CHECK-NEXT: retl399entry:400 %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind401 %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind402 %asmresult = extractvalue %complex %0, 0403 ret float %asmresult404}405 406; Pass the same value in two fixed stack slots.407define i32 @PR10602() nounwind ssp {408; CHECK-LABEL: PR10602:409; CHECK: ## %bb.0: ## %entry410; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}411; CHECK-NEXT: fld %st(0)412; CHECK-NEXT: fxch %st(1)413; CHECK-NEXT: ## InlineAsm Start414; CHECK-NEXT: fcomi %st(1), %st; pushf; pop %eax415; CHECK-NEXT: ## InlineAsm End416; CHECK-NEXT: fstp %st(0)417; CHECK-NEXT: fstp %st(0)418; CHECK-NEXT: retl419entry:420 %0 = tail call i32 asm "fcomi $2, $1; pushf; pop $0", "=r,{st},{st(1)},~{dirflag},~{fpsr},~{flags}"(double 2.000000e+00, double 2.000000e+00) nounwind421 ret i32 %0422}423 424; <rdar://problem/16952634>425; X87 stackifier asserted when there was an ST register defined by an426; inline-asm instruction and the ST register was live across another427; inline-asm instruction.428;429; INLINEASM $frndint [sideeffect] [attdialect], $0:[regdef], %st0<imp-def,tied5>, $1:[reguse tiedto:$0], %st0<tied3>, $2:[clobber], early-clobber implicit dead %eflags430; INLINEASM $fldcw $0 [sideeffect] [mayload] [attdialect], $0:[mem], undef %eax, 1, %noreg, 0, %noreg, $1:[clobber], early-clobber implicit dead %eflags431; %fp0 = COPY %st0432 433%struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] }434%struct.anon1 = type { i32, i32, i32 }435%struct.anon2 = type { i32, i32, i32, i32 }436 437@fpu = external global %struct.fpu_t, align 16438 439; Function Attrs: ssp440define void @test_live_st(i32 %a1) nounwind {441; CHECK-LABEL: test_live_st:442; CHECK: ## %bb.0: ## %entry443; CHECK-NEXT: subl $12, %esp444; CHECK-NEXT: fldt (%eax)445; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp)446; CHECK-NEXT: jne LBB20_2447; CHECK-NEXT: ## %bb.1: ## %sw.bb4.i448; CHECK-NEXT: ## InlineAsm Start449; CHECK-NEXT: frndint450; CHECK-NEXT: ## InlineAsm End451; CHECK-NEXT: ## InlineAsm Start452; CHECK-NEXT: fldcw (%eax)453; CHECK-NEXT: ## InlineAsm End454; CHECK-NEXT: LBB20_2: ## %_Z5tointRKe.exit455; CHECK-NEXT: fnstcw (%esp)456; CHECK-NEXT: movzwl (%esp), %eax457; CHECK-NEXT: orl $3072, %eax ## imm = 0xC00458; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)459; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)460; CHECK-NEXT: fistpl {{[0-9]+}}(%esp)461; CHECK-NEXT: fldcw (%esp)462; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax463; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)464; CHECK-NEXT: fildl {{[0-9]+}}(%esp)465; CHECK-NEXT: movl L_fpu$non_lazy_ptr, %eax466; CHECK-NEXT: fstpt 128(%eax)467; CHECK-NEXT: addl $12, %esp468; CHECK-NEXT: retl469entry:470 %0 = load x86_fp80, ptr undef, align 16471 %cond = icmp eq i32 %a1, 1472 br i1 %cond, label %sw.bb4.i, label %_Z5tointRKe.exit473 474sw.bb4.i:475 %1 = call x86_fp80 asm sideeffect "frndint", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %0)476 call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) undef)477 br label %_Z5tointRKe.exit478 479_Z5tointRKe.exit:480 %result.0.i = phi x86_fp80 [ %1, %sw.bb4.i ], [ %0, %entry ]481 %conv.i1814 = fptosi x86_fp80 %result.0.i to i32482 %conv626 = sitofp i32 %conv.i1814 to x86_fp80483 store x86_fp80 %conv626, ptr getelementptr inbounds (%struct.fpu_t, ptr @fpu, i32 0, i32 1)484 br label %return485 486return:487 ret void488}489 490; Check that x87 stackifier is correctly rewriting FP registers to ST registers.491define double @test_operand_rewrite() nounwind {492; CHECK-LABEL: test_operand_rewrite:493; CHECK: ## %bb.0: ## %entry494; CHECK-NEXT: ## InlineAsm Start495; CHECK-NEXT: foo %st, %st(1)496; CHECK-NEXT: ## InlineAsm End497; CHECK-NEXT: fsubp %st, %st(1)498; CHECK-NEXT: retl499entry:500 %0 = tail call { double, double } asm sideeffect "foo $0, $1", "={st},={st(1)},~{dirflag},~{fpsr},~{flags}"()501 %asmresult = extractvalue { double, double } %0, 0502 %asmresult1 = extractvalue { double, double } %0, 1503 %sub = fsub double %asmresult, %asmresult1504 ret double %sub505}506