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1; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X862; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X863; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X644; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X645 6; PR16133 - we must treat XMM registers as v4f32 as SSE1 targets don't permit other vector types.7 8define void @nop() nounwind {9; X86-LABEL: nop:10; X86: # %bb.0:11; X86-NEXT: pushl %ebp12; X86-NEXT: movl %esp, %ebp13; X86-NEXT: andl $-16, %esp14; X86-NEXT: subl $32, %esp15; X86-NEXT: #APP16; X86-NEXT: #NO_APP17; X86-NEXT: movaps %xmm0, (%esp)18; X86-NEXT: movl %ebp, %esp19; X86-NEXT: popl %ebp20; X86-NEXT: retl21;22; X64-LABEL: nop:23; X64: # %bb.0:24; X64-NEXT: #APP25; X64-NEXT: #NO_APP26; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)27; X64-NEXT: retq28 %1 = alloca <4 x float>, align 1629 %2 = call <4 x float> asm "", "=x,~{dirflag},~{fpsr},~{flags}"()30 store <4 x float> %2, ptr %1, align 1631 ret void32}33