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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_mem_shuffle2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX6 7define <4 x float> @shuffle_v4f32_0z27(<4 x float> %x, <4 x float> %a) {8; SSE-LABEL: shuffle_v4f32_0z27:9; SSE: # %bb.0:10; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]11; SSE-NEXT: retq12;13; AVX-LABEL: shuffle_v4f32_0z27:14; AVX: # %bb.0:15; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]16; AVX-NEXT: retq17 %vecext = extractelement <4 x float> %x, i32 018 %vecinit = insertelement <4 x float> undef, float %vecext, i32 019 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 120 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>21 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>22 ret <4 x float> %vecinit523}24 25define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %xyzw, <4 x float> %abcd) {26; SSE-LABEL: shuffle_v4f32_0zz4:27; SSE: # %bb.0:28; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]29; SSE-NEXT: retq30;31; AVX-LABEL: shuffle_v4f32_0zz4:32; AVX: # %bb.0:33; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]34; AVX-NEXT: retq35 %vecext = extractelement <4 x float> %xyzw, i32 036 %vecinit = insertelement <4 x float> undef, float %vecext, i32 037 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 138 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 239 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>40 ret <4 x float> %vecinit441}42 43define <4 x float> @shuffle_v4f32_0z24(<4 x float> %xyzw, <4 x float> %abcd) {44; SSE-LABEL: shuffle_v4f32_0z24:45; SSE: # %bb.0:46; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]47; SSE-NEXT: retq48;49; AVX-LABEL: shuffle_v4f32_0z24:50; AVX: # %bb.0:51; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]52; AVX-NEXT: retq53 %vecext = extractelement <4 x float> %xyzw, i32 054 %vecinit = insertelement <4 x float> undef, float %vecext, i32 055 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 156 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %xyzw, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>57 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>58 ret <4 x float> %vecinit559}60 61define <4 x float> @shuffle_v4f32_0zz0(float %a) {62; SSE-LABEL: shuffle_v4f32_0zz0:63; SSE: # %bb.0:64; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0]65; SSE-NEXT: retq66;67; AVX-LABEL: shuffle_v4f32_0zz0:68; AVX: # %bb.0:69; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm0[0]70; AVX-NEXT: retq71 %vecinit = insertelement <4 x float> undef, float %a, i32 072 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 173 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 274 %vecinit3 = insertelement <4 x float> %vecinit2, float %a, i32 375 ret <4 x float> %vecinit376}77 78define <4 x float> @shuffle_v4f32_0z6z(<4 x float> %A, <4 x float> %B) {79; SSE-LABEL: shuffle_v4f32_0z6z:80; SSE: # %bb.0:81; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero82; SSE-NEXT: retq83;84; AVX-LABEL: shuffle_v4f32_0z6z:85; AVX: # %bb.0:86; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero87; AVX-NEXT: retq88 %vecext = extractelement <4 x float> %A, i32 089 %vecinit = insertelement <4 x float> undef, float %vecext, i32 090 %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 191 %vecext2 = extractelement <4 x float> %B, i32 292 %vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 293 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 394 ret <4 x float> %vecinit495}96 97define <4 x float> @shuffle_v4f32_z06z(<4 x float> %a, <4 x float> %b) {98; SSE-LABEL: shuffle_v4f32_z06z:99; SSE: # %bb.0:100; SSE-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero101; SSE-NEXT: movaps %xmm1, %xmm0102; SSE-NEXT: retq103;104; AVX-LABEL: shuffle_v4f32_z06z:105; AVX: # %bb.0:106; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[0],xmm1[2],zero107; AVX-NEXT: retq108 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 undef, i32 0, i32 6, i32 undef>109 %shuffle1 = shufflevector <4 x float> %shuffle, <4 x float> <float 0.000000e+00, float undef, float undef, float 0.000000e+00>, <4 x i32> <i32 4, i32 1, i32 2, i32 7>110 ret <4 x float> %shuffle1111}112 113define <4 x float> @shuffle_v4f32_05zz(<4 x float> %a, <4 x float> %b) {114; SSE-LABEL: shuffle_v4f32_05zz:115; SSE: # %bb.0:116; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero117; SSE-NEXT: retq118;119; AVX-LABEL: shuffle_v4f32_05zz:120; AVX: # %bb.0:121; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero122; AVX-NEXT: retq123 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>124 %shuffle1 = shufflevector <4 x float> %shuffle, <4 x float> <float undef, float undef, float 0.000000e+00, float 0.000000e+00>, <4 x i32> <i32 0, i32 1, i32 6, i32 7>125 ret <4 x float> %shuffle1126}127 128define <4 x float> @insertps_undef_input0(<4 x float> %a0, <4 x float> %a1) {129; SSE-LABEL: insertps_undef_input0:130; SSE: # %bb.0:131; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero132; SSE-NEXT: retq133;134; AVX-LABEL: insertps_undef_input0:135; AVX: # %bb.0:136; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero137; AVX-NEXT: retq138 %res0 = fadd <4 x float> %a0, <float 1.0, float 1.0, float 1.0, float 1.0>139 %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %res0, <4 x float> %a1, i8 21)140 %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>141 ret <4 x float> %res2142}143 144define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) {145; SSE-LABEL: insertps_undef_input1:146; SSE: # %bb.0:147; SSE-NEXT: xorps %xmm1, %xmm1148; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]149; SSE-NEXT: retq150;151; AVX-LABEL: insertps_undef_input1:152; AVX: # %bb.0:153; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1154; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]155; AVX-NEXT: retq156 %res0 = fadd <4 x float> %a1, <float 1.0, float 1.0, float 1.0, float 1.0>157 %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %res0, i8 21)158 %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 3>159 ret <4 x float> %res2160}161 162define <4 x float> @insertps_zero_from_v2f64(<4 x float> %a0, ptr %a1) nounwind {163; SSE-LABEL: insertps_zero_from_v2f64:164; SSE: # %bb.0:165; SSE-NEXT: movapd (%rdi), %xmm1166; SSE-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1167; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]168; SSE-NEXT: movapd %xmm1, (%rdi)169; SSE-NEXT: retq170;171; AVX-LABEL: insertps_zero_from_v2f64:172; AVX: # %bb.0:173; AVX-NEXT: vmovapd (%rdi), %xmm1174; AVX-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1175; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]176; AVX-NEXT: vmovapd %xmm1, (%rdi)177; AVX-NEXT: retq178 %1 = load <2 x double>, ptr %a1179 %2 = bitcast <2 x double> <double 1.0, double 2.0> to <4 x float>180 %3 = fadd <2 x double> %1, <double 1.0, double 2.0>181 %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 6, i32 2, i32 2, i32 3>182 store <2 x double> %3, ptr%a1183 ret <4 x float> %4184}185 186define <4 x float> @insertps_zero_from_v2i64(<4 x float> %a0, ptr %a1) nounwind {187; SSE-LABEL: insertps_zero_from_v2i64:188; SSE: # %bb.0:189; SSE-NEXT: movdqa (%rdi), %xmm1190; SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1191; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]192; SSE-NEXT: movdqa %xmm1, (%rdi)193; SSE-NEXT: retq194;195; AVX-LABEL: insertps_zero_from_v2i64:196; AVX: # %bb.0:197; AVX-NEXT: vmovdqa (%rdi), %xmm1198; AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1199; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]200; AVX-NEXT: vmovdqa %xmm1, (%rdi)201; AVX-NEXT: retq202 %1 = load <2 x i64>, ptr %a1203 %2 = bitcast <2 x i64> <i64 1, i64 -2> to <4 x float>204 %3 = add <2 x i64> %1, <i64 1, i64 -2>205 %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 5, i32 2, i32 2, i32 3>206 store <2 x i64> %3, ptr%a1207 ret <4 x float> %4208}209 210define <4 x float> @insertps_zero_from_v8i16(<4 x float> %a0, ptr %a1) nounwind {211; SSE-LABEL: insertps_zero_from_v8i16:212; SSE: # %bb.0:213; SSE-NEXT: movdqa (%rdi), %xmm1214; SSE-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1215; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]216; SSE-NEXT: movdqa %xmm1, (%rdi)217; SSE-NEXT: retq218;219; AVX-LABEL: insertps_zero_from_v8i16:220; AVX: # %bb.0:221; AVX-NEXT: vmovdqa (%rdi), %xmm1222; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1223; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]224; AVX-NEXT: vmovdqa %xmm1, (%rdi)225; AVX-NEXT: retq226 %1 = load <8 x i16>, ptr %a1227 %2 = bitcast <8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3> to <4 x float>228 %3 = add <8 x i16> %1, <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3>229 %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 4, i32 2, i32 2, i32 3>230 store <8 x i16> %3, ptr%a1231 ret <4 x float> %4232}233 234define <4 x float> @consecutive_load_insertps_04zz(ptr %p) {235; SSE-LABEL: consecutive_load_insertps_04zz:236; SSE: # %bb.0:237; SSE-NEXT: movsd 4(%rdi), %xmm0 # xmm0 = mem[0],zero238; SSE-NEXT: retq239;240; AVX-LABEL: consecutive_load_insertps_04zz:241; AVX: # %bb.0:242; AVX-NEXT: vmovsd 4(%rdi), %xmm0 # xmm0 = mem[0],zero243; AVX-NEXT: retq244 %p0 = getelementptr inbounds float, ptr %p, i64 1245 %p1 = getelementptr inbounds float, ptr %p, i64 2246 %s0 = load float, ptr %p0247 %s1 = load float, ptr %p1248 %v0 = insertelement <4 x float> undef, float %s0, i32 0249 %v1 = insertelement <4 x float> undef, float %s1, i32 0250 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 28)251 ret <4 x float> %res252}253 254define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) {255; SSE-LABEL: extract_zero_insertps_z0z7:256; SSE: # %bb.0:257; SSE-NEXT: xorps %xmm0, %xmm0258; SSE-NEXT: retq259;260; AVX-LABEL: extract_zero_insertps_z0z7:261; AVX: # %bb.0:262; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0263; AVX-NEXT: retq264 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 21)265 %ext = extractelement <4 x float> %res, i32 0266 ret float %ext267}268 269define float @extract_lane_insertps_5123(<4 x float> %a0, ptr%p1) {270; SSE-LABEL: extract_lane_insertps_5123:271; SSE: # %bb.0:272; SSE-NEXT: movshdup (%rdi), %xmm0 # xmm0 = mem[1,1,3,3]273; SSE-NEXT: retq274;275; AVX-LABEL: extract_lane_insertps_5123:276; AVX: # %bb.0:277; AVX-NEXT: vmovshdup (%rdi), %xmm0 # xmm0 = mem[1,1,3,3]278; AVX-NEXT: retq279 %a1 = load <4 x float>, ptr%p1280 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 64)281 %ext = extractelement <4 x float> %res, i32 0282 ret float %ext283}284 285define float @extract_lane_insertps_6123(<4 x float> %a0, ptr%p1) {286; SSE-LABEL: extract_lane_insertps_6123:287; SSE: # %bb.0:288; SSE-NEXT: movaps (%rdi), %xmm0289; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]290; SSE-NEXT: retq291;292; AVX-LABEL: extract_lane_insertps_6123:293; AVX: # %bb.0:294; AVX-NEXT: vpermilpd $1, (%rdi), %xmm0 # xmm0 = mem[1,0]295; AVX-NEXT: retq296 %a1 = load <4 x float>, ptr%p1297 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 128)298 %ext = extractelement <4 x float> %res, i32 0299 ret float %ext300}301 302; PR40340303define <4 x float> @commute_load_insertps(<4 x float>, ptr nocapture readonly) {304; SSE-LABEL: commute_load_insertps:305; SSE: # %bb.0:306; SSE-NEXT: insertps $53, 12(%rdi), %xmm0 # xmm0 = zero,xmm0[1],zero,mem[0]307; SSE-NEXT: retq308;309; AVX-LABEL: commute_load_insertps:310; AVX: # %bb.0:311; AVX-NEXT: vinsertps $53, 12(%rdi), %xmm0, %xmm0 # xmm0 = zero,xmm0[1],zero,mem[0]312; AVX-NEXT: retq313 %3 = load <4 x float>, ptr %1314 %4 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %3, <4 x float> %0, i8 85)315 ret <4 x float> %4316}317 318declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone319