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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 %s -o - | FileCheck %s --check-prefixes SSE2,SSE2-X643; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -fast-isel %s -o - | FileCheck %s --check-prefixes SSE2,SSE2-X644; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes SSE2,SSE2-GISEL5 6;7; 128 bit vectors8;9 10define <7 x i8> @test_vector_v7i8() {11; SSE2-X64-LABEL: test_vector_v7i8:12; SSE2-X64: # %bb.0:13; SSE2-X64-NEXT: movq %rdi, %rax14; SSE2-X64-NEXT: movl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ecx15; SSE2-X64-NEXT: movl %ecx, (%rdi)16; SSE2-X64-NEXT: movb $63, 6(%rdi)17; SSE2-X64-NEXT: movw $10775, 4(%rdi) # imm = 0x2A1718; SSE2-X64-NEXT: retq19;20; SSE2-GISEL-LABEL: test_vector_v7i8:21; SSE2-GISEL: # %bb.0:22; SSE2-GISEL-NEXT: movq %rdi, %rax23; SSE2-GISEL-NEXT: movb $4, (%rdi)24; SSE2-GISEL-NEXT: movb $8, 1(%rdi)25; SSE2-GISEL-NEXT: movb $15, 2(%rdi)26; SSE2-GISEL-NEXT: movb $16, 3(%rdi)27; SSE2-GISEL-NEXT: movb $23, 4(%rdi)28; SSE2-GISEL-NEXT: movb $42, 5(%rdi)29; SSE2-GISEL-NEXT: movb $63, 6(%rdi)30; SSE2-GISEL-NEXT: retq31 ret <7 x i8> <i8 4, i8 8, i8 15, i8 16, i8 23, i8 42, i8 63>32}33 34define <16 x i8> @test_vector_v16i8() {35; SSE2-LABEL: test_vector_v16i8:36; SSE2: # %bb.0:37; SSE2-NEXT: movaps {{.*#+}} xmm0 = [4,8,15,16,23,42,63,70,92,105,123,133,157,160,174,180]38; SSE2-NEXT: retq39 ret <16 x i8> <i8 4, i8 8, i8 15, i8 16, i8 23, i8 42, i8 63, i8 70, i8 92, i8 105, i8 123, i8 133, i8 157, i8 160, i8 174, i8 180>40}41 42define <8 x i16> @test_vector_v8i16() {43; SSE2-LABEL: test_vector_v8i16:44; SSE2: # %bb.0:45; SSE2-NEXT: movaps {{.*#+}} xmm0 = [4,15,23,63,92,123,157,174]46; SSE2-NEXT: retq47 ret <8 x i16> <i16 4, i16 15, i16 23, i16 63, i16 92, i16 123, i16 157, i16 174>48}49 50define <4 x float> @test_vector_v4f32() {51; SSE2-LABEL: test_vector_v4f32:52; SSE2: # %bb.0:53; SSE2-NEXT: movaps {{.*#+}} xmm0 = [u,3.6627E+5,9.86864E+5,7.0851E+4]54; SSE2-NEXT: retq55 ret <4 x float> <float undef, float 366270.0, float 986864.0, float 70851.0>56}57 58define <2 x i64> @test_vector_v4i64() {59; SSE2-LABEL: test_vector_v4i64:60; SSE2: # %bb.0:61; SSE2-NEXT: movaps {{.*#+}} xmm0 = [9406487659005566976,9903695591611287552]62; SSE2-NEXT: retq63 ret <2 x i64> <i64 9406487659005566976, i64 9903695591611287552>64}65 66