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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X863; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X644 5define i32 @knownbits_mask_extract_sext(<8 x i16> %a0) nounwind {6; X86-LABEL: knownbits_mask_extract_sext:7; X86: # %bb.0:8; X86-NEXT: vmovd %xmm0, %eax9; X86-NEXT: andl $15, %eax10; X86-NEXT: retl11;12; X64-LABEL: knownbits_mask_extract_sext:13; X64: # %bb.0:14; X64-NEXT: vmovd %xmm0, %eax15; X64-NEXT: andl $15, %eax16; X64-NEXT: retq17 %1 = and <8 x i16> %a0, <i16 15, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>18 %2 = extractelement <8 x i16> %1, i32 019 %3 = sext i16 %2 to i3220 ret i32 %321}22 23define float @knownbits_mask_extract_uitofp(<2 x i64> %a0) nounwind {24; X86-LABEL: knownbits_mask_extract_uitofp:25; X86: # %bb.0:26; X86-NEXT: pushl %eax27; X86-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero28; X86-NEXT: vcvtdq2ps %xmm0, %xmm029; X86-NEXT: vmovss %xmm0, (%esp)30; X86-NEXT: flds (%esp)31; X86-NEXT: popl %eax32; X86-NEXT: retl33;34; X64-LABEL: knownbits_mask_extract_uitofp:35; X64: # %bb.0:36; X64-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero37; X64-NEXT: vcvtdq2ps %xmm0, %xmm038; X64-NEXT: retq39 %1 = and <2 x i64> %a0, <i64 65535, i64 -1>40 %2 = extractelement <2 x i64> %1, i32 041 %3 = uitofp i64 %2 to float42 ret float %343}44 45define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nounwind {46; X86-LABEL: knownbits_insert_uitofp:47; X86: # %bb.0:48; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax49; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx50; X86-NEXT: vmovd %ecx, %xmm051; X86-NEXT: vpinsrd $2, %eax, %xmm0, %xmm052; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]53; X86-NEXT: vcvtdq2ps %xmm0, %xmm054; X86-NEXT: retl55;56; X64-LABEL: knownbits_insert_uitofp:57; X64: # %bb.0:58; X64-NEXT: movzwl %di, %eax59; X64-NEXT: movzwl %si, %ecx60; X64-NEXT: vmovd %eax, %xmm061; X64-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm062; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]63; X64-NEXT: vcvtdq2ps %xmm0, %xmm064; X64-NEXT: retq65 %1 = zext i16 %a1 to i3266 %2 = zext i16 %a2 to i3267 %3 = insertelement <4 x i32> %a0, i32 %1, i32 068 %4 = insertelement <4 x i32> %3, i32 %2, i32 269 %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>70 %6 = uitofp <4 x i32> %5 to <4 x float>71 ret <4 x float> %672}73 74define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind {75; X86-LABEL: knownbits_mask_shuffle_sext:76; X86: # %bb.0:77; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm078; X86-NEXT: vpxor %xmm1, %xmm1, %xmm179; X86-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]80; X86-NEXT: retl81;82; X64-LABEL: knownbits_mask_shuffle_sext:83; X64: # %bb.0:84; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm085; X64-NEXT: vpxor %xmm1, %xmm1, %xmm186; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]87; X64-NEXT: retq88 %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15>89 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>90 %3 = sext <4 x i16> %2 to <4 x i32>91 ret <4 x i32> %392}93 94define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind {95; X86-LABEL: knownbits_mask_shuffle_shuffle_sext:96; X86: # %bb.0:97; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm098; X86-NEXT: vpxor %xmm1, %xmm1, %xmm199; X86-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]100; X86-NEXT: retl101;102; X64-LABEL: knownbits_mask_shuffle_shuffle_sext:103; X64: # %bb.0:104; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0105; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1106; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]107; X64-NEXT: retq108 %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15>109 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>110 %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>111 %4 = sext <4 x i16> %3 to <4 x i32>112 ret <4 x i32> %4113}114 115define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounwind {116; X86-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:117; X86: # %bb.0:118; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]119; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0120; X86-NEXT: vpmovsxwd %xmm0, %xmm0121; X86-NEXT: retl122;123; X64-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:124; X64: # %bb.0:125; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]126; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0127; X64-NEXT: vpmovsxwd %xmm0, %xmm0128; X64-NEXT: retq129 %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15>130 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>131 %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>132 %4 = sext <4 x i16> %3 to <4 x i32>133 ret <4 x i32> %4134}135 136define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind {137; X86-LABEL: knownbits_mask_shuffle_uitofp:138; X86: # %bb.0:139; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]140; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0141; X86-NEXT: vcvtdq2ps %xmm0, %xmm0142; X86-NEXT: retl143;144; X64-LABEL: knownbits_mask_shuffle_uitofp:145; X64: # %bb.0:146; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]147; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0148; X64-NEXT: vcvtdq2ps %xmm0, %xmm0149; X64-NEXT: retq150 %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>151 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>152 %3 = uitofp <4 x i32> %2 to <4 x float>153 ret <4 x float> %3154}155 156define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind {157; X86-LABEL: knownbits_mask_or_shuffle_uitofp:158; X86: # %bb.0:159; X86-NEXT: vbroadcastss {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4]160; X86-NEXT: retl161;162; X64-LABEL: knownbits_mask_or_shuffle_uitofp:163; X64: # %bb.0:164; X64-NEXT: vbroadcastss {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4]165; X64-NEXT: retq166 %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>167 %2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>168 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>169 %4 = uitofp <4 x i32> %3 to <4 x float>170 ret <4 x float> %4171}172 173define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind {174; X86-LABEL: knownbits_mask_xor_shuffle_uitofp:175; X86: # %bb.0:176; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]177; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0178; X86-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0179; X86-NEXT: vcvtdq2ps %xmm0, %xmm0180; X86-NEXT: retl181;182; X64-LABEL: knownbits_mask_xor_shuffle_uitofp:183; X64: # %bb.0:184; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,2,3,3]185; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0186; X64-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0187; X64-NEXT: vcvtdq2ps %xmm0, %xmm0188; X64-NEXT: retq189 %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>190 %2 = xor <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>191 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>192 %4 = uitofp <4 x i32> %3 to <4 x float>193 ret <4 x float> %4194}195 196define <4 x i32> @knownbits_mask_shl_shuffle_lshr(<4 x i32> %a0) nounwind {197; X86-LABEL: knownbits_mask_shl_shuffle_lshr:198; X86: # %bb.0:199; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0200; X86-NEXT: retl201;202; X64-LABEL: knownbits_mask_shl_shuffle_lshr:203; X64: # %bb.0:204; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0205; X64-NEXT: retq206 %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>207 %2 = shl <4 x i32> %1, <i32 17, i32 17, i32 17, i32 17>208 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>209 %4 = lshr <4 x i32> %3, <i32 15, i32 15, i32 15, i32 15>210 ret <4 x i32> %4211}212 213define <4 x i32> @knownbits_mask_ashr_shuffle_lshr(<4 x i32> %a0) nounwind {214; X86-LABEL: knownbits_mask_ashr_shuffle_lshr:215; X86: # %bb.0:216; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0217; X86-NEXT: retl218;219; X64-LABEL: knownbits_mask_ashr_shuffle_lshr:220; X64: # %bb.0:221; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0222; X64-NEXT: retq223 %1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 -1, i32 131071>224 %2 = ashr <4 x i32> %1, <i32 15, i32 15, i32 15, i32 15>225 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>226 %4 = lshr <4 x i32> %3, <i32 30, i32 30, i32 30, i32 30>227 ret <4 x i32> %4228}229 230define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) nounwind {231; X86-LABEL: knownbits_mask_mul_shuffle_shl:232; X86: # %bb.0:233; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0234; X86-NEXT: retl235;236; X64-LABEL: knownbits_mask_mul_shuffle_shl:237; X64: # %bb.0:238; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0239; X64-NEXT: retq240 %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>241 %2 = mul <4 x i32> %a1, %1242 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>243 %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>244 ret <4 x i32> %4245}246 247define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind {248; X86-LABEL: knownbits_mask_trunc_shuffle_shl:249; X86: # %bb.0:250; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0251; X86-NEXT: retl252;253; X64-LABEL: knownbits_mask_trunc_shuffle_shl:254; X64: # %bb.0:255; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0256; X64-NEXT: retq257 %1 = and <4 x i64> %a0, <i64 -65536, i64 -7, i64 7, i64 -65536>258 %2 = trunc <4 x i64> %1 to <4 x i32>259 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>260 %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>261 ret <4 x i32> %4262}263 264define <4 x i32> @knownbits_mask_add_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {265; X86-LABEL: knownbits_mask_add_shuffle_lshr:266; X86: # %bb.0:267; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0268; X86-NEXT: retl269;270; X64-LABEL: knownbits_mask_add_shuffle_lshr:271; X64: # %bb.0:272; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0273; X64-NEXT: retq274 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767>275 %2 = and <4 x i32> %a1, <i32 32767, i32 -1, i32 -1, i32 32767>276 %3 = add <4 x i32> %1, %2277 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>278 %5 = lshr <4 x i32> %4, <i32 17, i32 17, i32 17, i32 17>279 ret <4 x i32> %5280}281 282define <4 x i32> @knownbits_mask_sub_shuffle_lshr(<4 x i32> %a0) nounwind {283; X86-LABEL: knownbits_mask_sub_shuffle_lshr:284; X86: # %bb.0:285; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0286; X86-NEXT: retl287;288; X64-LABEL: knownbits_mask_sub_shuffle_lshr:289; X64: # %bb.0:290; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0291; X64-NEXT: retq292 %1 = and <4 x i32> %a0, <i32 15, i32 -1, i32 -1, i32 15>293 %2 = sub <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %1294 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>295 %4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>296 ret <4 x i32> %4297}298 299define <4 x i32> @knownbits_mask_udiv_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {300; X86-LABEL: knownbits_mask_udiv_shuffle_lshr:301; X86: # %bb.0:302; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0303; X86-NEXT: retl304;305; X64-LABEL: knownbits_mask_udiv_shuffle_lshr:306; X64: # %bb.0:307; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0308; X64-NEXT: retq309 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767>310 %2 = udiv <4 x i32> %1, %a1311 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>312 %4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>313 ret <4 x i32> %4314}315 316define <4 x i32> @knownbits_urem_lshr(<4 x i32> %a0) nounwind {317; X86-LABEL: knownbits_urem_lshr:318; X86: # %bb.0:319; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0320; X86-NEXT: retl321;322; X64-LABEL: knownbits_urem_lshr:323; X64: # %bb.0:324; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0325; X64-NEXT: retq326 %1 = urem <4 x i32> %a0, <i32 16, i32 16, i32 16, i32 16>327 %2 = lshr <4 x i32> %1, <i32 22, i32 22, i32 22, i32 22>328 ret <4 x i32> %2329}330 331define <4 x i32> @knownbits_mask_urem_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {332; X86-LABEL: knownbits_mask_urem_shuffle_lshr:333; X86: # %bb.0:334; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0335; X86-NEXT: retl336;337; X64-LABEL: knownbits_mask_urem_shuffle_lshr:338; X64: # %bb.0:339; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0340; X64-NEXT: retq341 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767>342 %2 = and <4 x i32> %a1, <i32 32767, i32 -1, i32 -1, i32 32767>343 %3 = urem <4 x i32> %1, %2344 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>345 %5 = lshr <4 x i32> %4, <i32 22, i32 22, i32 22, i32 22>346 ret <4 x i32> %5347}348 349define <4 x i32> @knownbits_mask_srem_shuffle_lshr(<4 x i32> %a0) nounwind {350; X86-LABEL: knownbits_mask_srem_shuffle_lshr:351; X86: # %bb.0:352; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0353; X86-NEXT: retl354;355; X64-LABEL: knownbits_mask_srem_shuffle_lshr:356; X64: # %bb.0:357; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0358; X64-NEXT: retq359 %1 = and <4 x i32> %a0, <i32 -32768, i32 -1, i32 -1, i32 -32768>360 %2 = srem <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>361 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>362 %4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>363 ret <4 x i32> %4364}365 366define <4 x i32> @knownbits_mask_bswap_shuffle_shl(<4 x i32> %a0) nounwind {367; X86-LABEL: knownbits_mask_bswap_shuffle_shl:368; X86: # %bb.0:369; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0370; X86-NEXT: retl371;372; X64-LABEL: knownbits_mask_bswap_shuffle_shl:373; X64: # %bb.0:374; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0375; X64-NEXT: retq376 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767>377 %2 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %1)378 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>379 %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>380 ret <4 x i32> %4381}382declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)383 384define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind {385; X86-LABEL: knownbits_mask_concat_uitofp:386; X86: # %bb.0:387; X86-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0388; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0389; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0390; X86-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,2,5,7,5,7]391; X86-NEXT: vcvtdq2ps %ymm0, %ymm0392; X86-NEXT: retl393;394; X64-LABEL: knownbits_mask_concat_uitofp:395; X64: # %bb.0:396; X64-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0397; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0398; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0399; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,2,5,7,5,7]400; X64-NEXT: vcvtdq2ps %ymm0, %ymm0401; X64-NEXT: retq402 %1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 131071, i32 -1>403 %2 = and <4 x i32> %a1, <i32 -1, i32 131071, i32 -1, i32 131071>404 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 2, i32 0, i32 2, i32 5, i32 7, i32 5, i32 7>405 %4 = uitofp <8 x i32> %3 to <8 x float>406 ret <8 x float> %4407}408 409define <4 x float> @knownbits_lshr_bitcast_shuffle_uitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {410; X86-LABEL: knownbits_lshr_bitcast_shuffle_uitofp:411; X86: # %bb.0:412; X86-NEXT: vpsrlq $1, %xmm0, %xmm0413; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]414; X86-NEXT: vcvtdq2ps %xmm0, %xmm0415; X86-NEXT: retl416;417; X64-LABEL: knownbits_lshr_bitcast_shuffle_uitofp:418; X64: # %bb.0:419; X64-NEXT: vpsrlq $1, %xmm0, %xmm0420; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]421; X64-NEXT: vcvtdq2ps %xmm0, %xmm0422; X64-NEXT: retq423 %1 = lshr <2 x i64> %a0, <i64 1, i64 1>424 %2 = bitcast <2 x i64> %1 to <4 x i32>425 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>426 %4 = uitofp <4 x i32> %3 to <4 x float>427 ret <4 x float> %4428}429 430define <4 x float> @knownbits_smax_smin_shuffle_uitofp(<4 x i32> %a0) {431; X86-LABEL: knownbits_smax_smin_shuffle_uitofp:432; X86: # %bb.0:433; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]434; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1435; X86-NEXT: vpminsd %xmm1, %xmm0, %xmm0436; X86-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0437; X86-NEXT: vcvtdq2ps %xmm0, %xmm0438; X86-NEXT: retl439;440; X64-LABEL: knownbits_smax_smin_shuffle_uitofp:441; X64: # %bb.0:442; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]443; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1444; X64-NEXT: vpminsd %xmm1, %xmm0, %xmm0445; X64-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0446; X64-NEXT: vcvtdq2ps %xmm0, %xmm0447; X64-NEXT: retq448 %1 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a0, <4 x i32> <i32 0, i32 -65535, i32 -65535, i32 0>)449 %2 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %1, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 131071>)450 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>451 %4 = uitofp <4 x i32> %3 to <4 x float>452 ret <4 x float> %4453}454declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone455declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone456 457define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) {458; X86-LABEL: knownbits_umin_shuffle_uitofp:459; X86: # %bb.0:460; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]461; X86-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0462; X86-NEXT: vcvtdq2ps %xmm0, %xmm0463; X86-NEXT: retl464;465; X64-LABEL: knownbits_umin_shuffle_uitofp:466; X64: # %bb.0:467; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]468; X64-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0469; X64-NEXT: vcvtdq2ps %xmm0, %xmm0470; X64-NEXT: retq471 %1 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a0, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 262143>)472 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>473 %3 = uitofp <4 x i32> %2 to <4 x float>474 ret <4 x float> %3475}476declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone477 478define <4 x i32> @knownbits_umax_shuffle_ashr(<4 x i32> %a0) {479; X86-LABEL: knownbits_umax_shuffle_ashr:480; X86: # %bb.0:481; X86-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0482; X86-NEXT: retl483;484; X64-LABEL: knownbits_umax_shuffle_ashr:485; X64: # %bb.0:486; X64-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0487; X64-NEXT: retq488 %1 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a0, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 262143>)489 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 2>490 %3 = ashr <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>491 ret <4 x i32> %3492}493declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone494 495define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) {496; X86-LABEL: knownbits_mask_umax_shuffle_uitofp:497; X86: # %bb.0:498; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]499; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0500; X86-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0501; X86-NEXT: vcvtdq2ps %xmm0, %xmm0502; X86-NEXT: retl503;504; X64-LABEL: knownbits_mask_umax_shuffle_uitofp:505; X64: # %bb.0:506; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]507; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0508; X64-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0509; X64-NEXT: vcvtdq2ps %xmm0, %xmm0510; X64-NEXT: retq511 %1 = and <4 x i32> %a0, <i32 65535, i32 -1, i32 -1, i32 262143>512 %2 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %1, <4 x i32> <i32 255, i32 -1, i32 -1, i32 1023>)513 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>514 %4 = uitofp <4 x i32> %3 to <4 x float>515 ret <4 x float> %4516}517 518define <4 x i32> @knownbits_mask_bitreverse_ashr(<4 x i32> %a0) {519; X86-LABEL: knownbits_mask_bitreverse_ashr:520; X86: # %bb.0:521; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0522; X86-NEXT: retl523;524; X64-LABEL: knownbits_mask_bitreverse_ashr:525; X64: # %bb.0:526; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0527; X64-NEXT: retq528 %1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 -2, i32 -2>529 %2 = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %1)530 %3 = ashr <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>531 ret <4 x i32> %3532}533declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) nounwind readnone534 535; If we don't know that the input isn't INT_MIN we can't combine to sitofp536define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {537; X86-LABEL: knownbits_abs_uitofp:538; X86: # %bb.0:539; X86-NEXT: vpabsd %xmm0, %xmm0540; X86-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]541; X86-NEXT: vpsrld $16, %xmm0, %xmm0542; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]543; X86-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0544; X86-NEXT: vaddps %xmm0, %xmm1, %xmm0545; X86-NEXT: retl546;547; X64-LABEL: knownbits_abs_uitofp:548; X64: # %bb.0:549; X64-NEXT: vpabsd %xmm0, %xmm0550; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]551; X64-NEXT: vpsrld $16, %xmm0, %xmm0552; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]553; X64-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0554; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0555; X64-NEXT: retq556 %1 = sub <4 x i32> zeroinitializer, %a0557 %2 = icmp slt <4 x i32> %a0, zeroinitializer558 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> %a0559 %4 = uitofp <4 x i32> %3 to <4 x float>560 ret <4 x float> %4561}562 563define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {564; X86-LABEL: knownbits_or_abs_uitofp:565; X86: # %bb.0:566; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]567; X86-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0568; X86-NEXT: vpabsd %xmm0, %xmm0569; X86-NEXT: vcvtdq2ps %xmm0, %xmm0570; X86-NEXT: retl571;572; X64-LABEL: knownbits_or_abs_uitofp:573; X64: # %bb.0:574; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]575; X64-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0576; X64-NEXT: vpabsd %xmm0, %xmm0577; X64-NEXT: vcvtdq2ps %xmm0, %xmm0578; X64-NEXT: retq579 %1 = or <4 x i32> %a0, <i32 1, i32 0, i32 3, i32 0>580 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>581 %3 = sub <4 x i32> zeroinitializer, %2582 %4 = icmp slt <4 x i32> %2, zeroinitializer583 %5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> %2584 %6 = uitofp <4 x i32> %5 to <4 x float>585 ret <4 x float> %6586}587 588define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind {589; X86-LABEL: knownbits_and_select_shuffle_uitofp:590; X86: # %bb.0:591; X86-NEXT: pushl %ebp592; X86-NEXT: movl %esp, %ebp593; X86-NEXT: andl $-16, %esp594; X86-NEXT: subl $16, %esp595; X86-NEXT: vmovaps 8(%ebp), %xmm3596; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2597; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3598; X86-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0599; X86-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0600; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,2]601; X86-NEXT: vcvtdq2ps %xmm0, %xmm0602; X86-NEXT: movl %ebp, %esp603; X86-NEXT: popl %ebp604; X86-NEXT: retl605;606; X64-LABEL: knownbits_and_select_shuffle_uitofp:607; X64: # %bb.0:608; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2609; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3610; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0611; X64-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0612; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,2]613; X64-NEXT: vcvtdq2ps %xmm0, %xmm0614; X64-NEXT: retq615 %1 = and <4 x i32> %a2, <i32 65535, i32 -1, i32 255, i32 -1>616 %2 = and <4 x i32> %a3, <i32 255, i32 -1, i32 65535, i32 -1>617 %3 = icmp eq <4 x i32> %a0, %a1618 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2619 %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>620 %6 = uitofp <4 x i32> %5 to <4 x float>621 ret <4 x float> %6622}623 624define <4 x float> @knownbits_lshr_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind {625; X86-LABEL: knownbits_lshr_and_select_shuffle_uitofp:626; X86: # %bb.0:627; X86-NEXT: pushl %ebp628; X86-NEXT: movl %esp, %ebp629; X86-NEXT: andl $-16, %esp630; X86-NEXT: subl $16, %esp631; X86-NEXT: vmovaps 8(%ebp), %xmm3632; X86-NEXT: vpsrld $5, %xmm2, %xmm2633; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3634; X86-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0635; X86-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0636; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,2]637; X86-NEXT: vcvtdq2ps %xmm0, %xmm0638; X86-NEXT: movl %ebp, %esp639; X86-NEXT: popl %ebp640; X86-NEXT: retl641;642; X64-LABEL: knownbits_lshr_and_select_shuffle_uitofp:643; X64: # %bb.0:644; X64-NEXT: vpsrld $5, %xmm2, %xmm2645; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3646; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0647; X64-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0648; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,2]649; X64-NEXT: vcvtdq2ps %xmm0, %xmm0650; X64-NEXT: retq651 %1 = lshr <4 x i32> %a2, <i32 5, i32 1, i32 5, i32 1>652 %2 = and <4 x i32> %a3, <i32 255, i32 -1, i32 65535, i32 -1>653 %3 = icmp eq <4 x i32> %a0, %a1654 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2655 %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>656 %6 = uitofp <4 x i32> %5 to <4 x float>657 ret <4 x float> %6658}659 660define <2 x double> @knownbits_lshr_subvector_uitofp(<4 x i32> %x) {661; X86-LABEL: knownbits_lshr_subvector_uitofp:662; X86: # %bb.0:663; X86-NEXT: vpsrld $2, %xmm0, %xmm1664; X86-NEXT: vpsrld $1, %xmm0, %xmm0665; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]666; X86-NEXT: vcvtdq2pd %xmm0, %xmm0667; X86-NEXT: retl668;669; X64-LABEL: knownbits_lshr_subvector_uitofp:670; X64: # %bb.0:671; X64-NEXT: vpsrld $2, %xmm0, %xmm1672; X64-NEXT: vpsrld $1, %xmm0, %xmm0673; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]674; X64-NEXT: vcvtdq2pd %xmm0, %xmm0675; X64-NEXT: retq676 %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 0, i32 0>677 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>678 %3 = uitofp <2 x i32> %2 to <2 x double>679 ret <2 x double> %3680}681