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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X643 4; Verify that we can look through a ZERO_EXTEND/ANY_EXTEND when doing5; ComputeNumSignBits for SHL.6; We use the (sshlsat x, c) -> (shl x, c) fold as verification.7; That fold should happen if c is less than the number of sign bits in x8 9define void @computeNumSignBits_shl_zext_1(i8 %x, ptr %p) nounwind {10; X64-LABEL: computeNumSignBits_shl_zext_1:11; X64: # %bb.0:12; X64-NEXT: sarb $5, %dil13; X64-NEXT: movzbl %dil, %eax14; X64-NEXT: movl %eax, %ecx15; X64-NEXT: shll $11, %ecx16; X64-NEXT: movw %cx, (%rsi)17; X64-NEXT: movl %eax, %ecx18; X64-NEXT: shll $12, %ecx19; X64-NEXT: movw %cx, (%rsi)20; X64-NEXT: shll $13, %eax21; X64-NEXT: movw %ax, (%rsi)22; X64-NEXT: retq23 %ashr = ashr i8 %x, 524 %zext = zext i8 %ashr to i1625 %nsb4 = shl i16 %zext, 1026 ; Expecting (sshlsat x, c) -> (shl x, c) fold.27 %tmp1 = call i16 @llvm.sshl.sat.i16(i16 %nsb4, i16 1)28 store volatile i16 %tmp1, ptr %p29 ; Expecting (sshlsat x, c) -> (shl x, c) fold.30 %tmp2 = call i16 @llvm.sshl.sat.i16(i16 %nsb4, i16 2)31 store volatile i16 %tmp2, ptr %p32 ; Expecting (sshlsat x, c) -> (shl x, c) fold.33 %tmp3 = call i16 @llvm.sshl.sat.i16(i16 %nsb4, i16 3)34 store volatile i16 %tmp3, ptr %p35 ret void36}37 38define void @computeNumSignBits_shl_zext_2(i8 %x, ptr %p) nounwind {39; X64-LABEL: computeNumSignBits_shl_zext_2:40; X64: # %bb.0:41; X64-NEXT: sarb $5, %dil42; X64-NEXT: movzbl %dil, %eax43; X64-NEXT: movl %eax, %ecx44; X64-NEXT: shll $10, %ecx45; X64-NEXT: xorl %edx, %edx46; X64-NEXT: testw %cx, %cx47; X64-NEXT: sets %dl48; X64-NEXT: addl $32767, %edx # imm = 0x7FFF49; X64-NEXT: shll $14, %eax50; X64-NEXT: movswl %ax, %edi51; X64-NEXT: shrl $4, %edi52; X64-NEXT: cmpw %di, %cx53; X64-NEXT: cmovnel %edx, %eax54; X64-NEXT: movw %ax, (%rsi)55; X64-NEXT: retq56 %ashr = ashr i8 %x, 557 %zext = zext i8 %ashr to i1658 %nsb4 = shl i16 %zext, 1059 ; 4 sign bits. Not expecting (sshlsat x, c) -> (shl x, c) fold.60 %tmp4 = call i16 @llvm.sshl.sat.i16(i16 %nsb4, i16 4)61 store volatile i16 %tmp4, ptr %p62 ret void63}64 65define void @computeNumSignBits_shl_zext_vec_1(<2 x i8> %x, ptr %p) nounwind {66; X64-LABEL: computeNumSignBits_shl_zext_vec_1:67; X64: # %bb.0:68; X64-NEXT: psrlw $5, %xmm069; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm070; X64-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]71; X64-NEXT: pxor %xmm1, %xmm072; X64-NEXT: psubb %xmm1, %xmm073; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]74; X64-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2048,8192,u,u,u,u,u,u]75; X64-NEXT: movd %xmm0, (%rdi)76; X64-NEXT: retq77 %ashr = ashr <2 x i8> %x, <i8 5, i8 5>78 %zext = zext <2 x i8> %ashr to <2 x i16>79 %nsb4_2 = shl <2 x i16> %zext, <i16 10, i16 12>80 ; Expecting (sshlsat x, c) -> (shl x, c) fold.81 %tmp1 = call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> %nsb4_2, <2 x i16> <i16 1, i16 1>)82 store volatile <2 x i16> %tmp1, ptr %p83 ret void84}85 86define void @computeNumSignBits_shl_zext_vec_2(<2 x i8> %x, ptr %p) nounwind {87; X64-LABEL: computeNumSignBits_shl_zext_vec_2:88; X64: # %bb.0:89; X64-NEXT: psrlw $5, %xmm090; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm091; X64-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]92; X64-NEXT: pxor %xmm1, %xmm093; X64-NEXT: psubb %xmm1, %xmm094; X64-NEXT: pxor %xmm1, %xmm195; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]96; X64-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1024,4096,u,u,u,u,u,u]97; X64-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]98; X64-NEXT: pand %xmm0, %xmm299; X64-NEXT: pcmpgtw %xmm0, %xmm1100; X64-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1101; X64-NEXT: por %xmm2, %xmm1102; X64-NEXT: movdqa %xmm0, %xmm2103; X64-NEXT: psllw $2, %xmm2104; X64-NEXT: movdqa %xmm2, %xmm3105; X64-NEXT: psraw $2, %xmm3106; X64-NEXT: pcmpeqw %xmm0, %xmm3107; X64-NEXT: movdqa %xmm3, %xmm0108; X64-NEXT: pandn %xmm1, %xmm0109; X64-NEXT: pand %xmm2, %xmm3110; X64-NEXT: por %xmm0, %xmm3111; X64-NEXT: movd %xmm3, (%rdi)112; X64-NEXT: retq113 %ashr = ashr <2 x i8> %x, <i8 5, i8 5>114 %zext = zext <2 x i8> %ashr to <2 x i16>115 %nsb4_2 = shl <2 x i16> %zext, <i16 10, i16 12>116 ; Not expecting (sshlsat x, c) -> (shl x, c) fold.117 ; Because only 2 sign bits in element 1.118 %tmp1 = call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> %nsb4_2, <2 x i16> <i16 2, i16 2>)119 store volatile <2 x i16> %tmp1, ptr %p120 ret void121}122 123define void @computeNumSignBits_shl_zext_vec_3(<2 x i8> %x, ptr %p) nounwind {124; X64-LABEL: computeNumSignBits_shl_zext_vec_3:125; X64: # %bb.0:126; X64-NEXT: psrlw $5, %xmm0127; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0128; X64-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]129; X64-NEXT: pxor %xmm1, %xmm0130; X64-NEXT: psubb %xmm1, %xmm0131; X64-NEXT: pxor %xmm1, %xmm1132; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]133; X64-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16384,4096,u,u,u,u,u,u]134; X64-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]135; X64-NEXT: pand %xmm0, %xmm2136; X64-NEXT: pcmpgtw %xmm0, %xmm1137; X64-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1138; X64-NEXT: por %xmm2, %xmm1139; X64-NEXT: movdqa %xmm0, %xmm2140; X64-NEXT: paddw %xmm2, %xmm2141; X64-NEXT: movdqa %xmm2, %xmm3142; X64-NEXT: psraw $1, %xmm3143; X64-NEXT: pcmpeqw %xmm0, %xmm3144; X64-NEXT: movdqa %xmm3, %xmm0145; X64-NEXT: pandn %xmm1, %xmm0146; X64-NEXT: pand %xmm2, %xmm3147; X64-NEXT: por %xmm0, %xmm3148; X64-NEXT: movd %xmm3, (%rdi)149; X64-NEXT: retq150 %ashr = ashr <2 x i8> %x, <i8 5, i8 5>151 %zext = zext <2 x i8> %ashr to <2 x i16>152 %nsb1_2 = shl <2 x i16> %zext, <i16 14, i16 12>153 ; Not expecting (sshlsat x, c) -> (shl x, c) fold.154 ; Because all sign bits shifted out for element 0155 %tmp1 = call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> %nsb1_2, <2 x i16> <i16 1, i16 1>)156 store volatile <2 x i16> %tmp1, ptr %p157 ret void158}159