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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -limit-float-precision=6 -mtriple=i686-- | FileCheck %s --check-prefix=precision63; RUN: llc < %s -limit-float-precision=12 -mtriple=i686-- | FileCheck %s --check-prefix=precision124; RUN: llc < %s -limit-float-precision=18 -mtriple=i686-- | FileCheck %s --check-prefix=precision185 6define float @f1(float %x) nounwind noinline {7; precision6-LABEL: f1:8; precision6: # %bb.0: # %entry9; precision6-NEXT: subl $20, %esp10; precision6-NEXT: flds {{[0-9]+}}(%esp)11; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}12; precision6-NEXT: fnstcw (%esp)13; precision6-NEXT: movzwl (%esp), %eax14; precision6-NEXT: orl $3072, %eax # imm = 0xC0015; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)16; precision6-NEXT: fldcw {{[0-9]+}}(%esp)17; precision6-NEXT: fistl {{[0-9]+}}(%esp)18; precision6-NEXT: fldcw (%esp)19; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax20; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)21; precision6-NEXT: fisubl {{[0-9]+}}(%esp)22; precision6-NEXT: fld %st(0)23; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}24; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}25; precision6-NEXT: fmulp %st, %st(1)26; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}27; precision6-NEXT: fstps {{[0-9]+}}(%esp)28; precision6-NEXT: shll $23, %eax29; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax30; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)31; precision6-NEXT: flds {{[0-9]+}}(%esp)32; precision6-NEXT: addl $20, %esp33; precision6-NEXT: retl34;35; precision12-LABEL: f1:36; precision12: # %bb.0: # %entry37; precision12-NEXT: subl $20, %esp38; precision12-NEXT: flds {{[0-9]+}}(%esp)39; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}40; precision12-NEXT: fnstcw (%esp)41; precision12-NEXT: movzwl (%esp), %eax42; precision12-NEXT: orl $3072, %eax # imm = 0xC0043; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)44; precision12-NEXT: fldcw {{[0-9]+}}(%esp)45; precision12-NEXT: fistl {{[0-9]+}}(%esp)46; precision12-NEXT: fldcw (%esp)47; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax48; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)49; precision12-NEXT: fisubl {{[0-9]+}}(%esp)50; precision12-NEXT: fld %st(0)51; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}52; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}53; precision12-NEXT: fmul %st(1), %st54; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}55; precision12-NEXT: fmulp %st, %st(1)56; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}57; precision12-NEXT: fstps {{[0-9]+}}(%esp)58; precision12-NEXT: shll $23, %eax59; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax60; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)61; precision12-NEXT: flds {{[0-9]+}}(%esp)62; precision12-NEXT: addl $20, %esp63; precision12-NEXT: retl64;65; precision18-LABEL: f1:66; precision18: # %bb.0: # %entry67; precision18-NEXT: subl $20, %esp68; precision18-NEXT: flds {{[0-9]+}}(%esp)69; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}70; precision18-NEXT: fnstcw (%esp)71; precision18-NEXT: movzwl (%esp), %eax72; precision18-NEXT: orl $3072, %eax # imm = 0xC0073; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)74; precision18-NEXT: fldcw {{[0-9]+}}(%esp)75; precision18-NEXT: fistl {{[0-9]+}}(%esp)76; precision18-NEXT: fldcw (%esp)77; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax78; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)79; precision18-NEXT: fisubl {{[0-9]+}}(%esp)80; precision18-NEXT: fld %st(0)81; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}82; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}83; precision18-NEXT: fmul %st(1), %st84; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}85; precision18-NEXT: fmul %st(1), %st86; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}87; precision18-NEXT: fmul %st(1), %st88; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}89; precision18-NEXT: fmul %st(1), %st90; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}91; precision18-NEXT: fmulp %st, %st(1)92; precision18-NEXT: fld193; precision18-NEXT: faddp %st, %st(1)94; precision18-NEXT: fstps {{[0-9]+}}(%esp)95; precision18-NEXT: shll $23, %eax96; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax97; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)98; precision18-NEXT: flds {{[0-9]+}}(%esp)99; precision18-NEXT: addl $20, %esp100; precision18-NEXT: retl101entry:102 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]103 %0 = call float @llvm.exp.f32(float %x) ; <float> [#uses=1]104 ret float %0105}106 107declare float @llvm.exp.f32(float) nounwind readonly108 109define float @f2(float %x) nounwind noinline {110; precision6-LABEL: f2:111; precision6: # %bb.0: # %entry112; precision6-NEXT: subl $20, %esp113; precision6-NEXT: flds {{[0-9]+}}(%esp)114; precision6-NEXT: fnstcw (%esp)115; precision6-NEXT: movzwl (%esp), %eax116; precision6-NEXT: orl $3072, %eax # imm = 0xC00117; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)118; precision6-NEXT: fldcw {{[0-9]+}}(%esp)119; precision6-NEXT: fistl {{[0-9]+}}(%esp)120; precision6-NEXT: fldcw (%esp)121; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax122; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)123; precision6-NEXT: fisubl {{[0-9]+}}(%esp)124; precision6-NEXT: fld %st(0)125; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}126; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}127; precision6-NEXT: fmulp %st, %st(1)128; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}129; precision6-NEXT: fstps {{[0-9]+}}(%esp)130; precision6-NEXT: shll $23, %eax131; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax132; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)133; precision6-NEXT: flds {{[0-9]+}}(%esp)134; precision6-NEXT: addl $20, %esp135; precision6-NEXT: retl136;137; precision12-LABEL: f2:138; precision12: # %bb.0: # %entry139; precision12-NEXT: subl $20, %esp140; precision12-NEXT: flds {{[0-9]+}}(%esp)141; precision12-NEXT: fnstcw (%esp)142; precision12-NEXT: movzwl (%esp), %eax143; precision12-NEXT: orl $3072, %eax # imm = 0xC00144; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)145; precision12-NEXT: fldcw {{[0-9]+}}(%esp)146; precision12-NEXT: fistl {{[0-9]+}}(%esp)147; precision12-NEXT: fldcw (%esp)148; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax149; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)150; precision12-NEXT: fisubl {{[0-9]+}}(%esp)151; precision12-NEXT: fld %st(0)152; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}153; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}154; precision12-NEXT: fmul %st(1), %st155; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}156; precision12-NEXT: fmulp %st, %st(1)157; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}158; precision12-NEXT: fstps {{[0-9]+}}(%esp)159; precision12-NEXT: shll $23, %eax160; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax161; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)162; precision12-NEXT: flds {{[0-9]+}}(%esp)163; precision12-NEXT: addl $20, %esp164; precision12-NEXT: retl165;166; precision18-LABEL: f2:167; precision18: # %bb.0: # %entry168; precision18-NEXT: subl $20, %esp169; precision18-NEXT: flds {{[0-9]+}}(%esp)170; precision18-NEXT: fnstcw (%esp)171; precision18-NEXT: movzwl (%esp), %eax172; precision18-NEXT: orl $3072, %eax # imm = 0xC00173; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)174; precision18-NEXT: fldcw {{[0-9]+}}(%esp)175; precision18-NEXT: fistl {{[0-9]+}}(%esp)176; precision18-NEXT: fldcw (%esp)177; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax178; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)179; precision18-NEXT: fisubl {{[0-9]+}}(%esp)180; precision18-NEXT: fld %st(0)181; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}182; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}183; precision18-NEXT: fmul %st(1), %st184; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}185; precision18-NEXT: fmul %st(1), %st186; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}187; precision18-NEXT: fmul %st(1), %st188; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}189; precision18-NEXT: fmul %st(1), %st190; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}191; precision18-NEXT: fmulp %st, %st(1)192; precision18-NEXT: fld1193; precision18-NEXT: faddp %st, %st(1)194; precision18-NEXT: fstps {{[0-9]+}}(%esp)195; precision18-NEXT: shll $23, %eax196; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax197; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)198; precision18-NEXT: flds {{[0-9]+}}(%esp)199; precision18-NEXT: addl $20, %esp200; precision18-NEXT: retl201entry:202 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]203 %0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1]204 ret float %0205}206 207declare float @llvm.exp2.f32(float) nounwind readonly208 209define float @f3(float %x) nounwind noinline {210; precision6-LABEL: f3:211; precision6: # %bb.0: # %entry212; precision6-NEXT: subl $20, %esp213; precision6-NEXT: flds {{[0-9]+}}(%esp)214; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}215; precision6-NEXT: fnstcw (%esp)216; precision6-NEXT: movzwl (%esp), %eax217; precision6-NEXT: orl $3072, %eax # imm = 0xC00218; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)219; precision6-NEXT: fldcw {{[0-9]+}}(%esp)220; precision6-NEXT: fistl {{[0-9]+}}(%esp)221; precision6-NEXT: fldcw (%esp)222; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax223; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)224; precision6-NEXT: fisubl {{[0-9]+}}(%esp)225; precision6-NEXT: fld %st(0)226; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}227; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}228; precision6-NEXT: fmulp %st, %st(1)229; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}230; precision6-NEXT: fstps {{[0-9]+}}(%esp)231; precision6-NEXT: shll $23, %eax232; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax233; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)234; precision6-NEXT: flds {{[0-9]+}}(%esp)235; precision6-NEXT: addl $20, %esp236; precision6-NEXT: retl237;238; precision12-LABEL: f3:239; precision12: # %bb.0: # %entry240; precision12-NEXT: subl $20, %esp241; precision12-NEXT: flds {{[0-9]+}}(%esp)242; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}243; precision12-NEXT: fnstcw (%esp)244; precision12-NEXT: movzwl (%esp), %eax245; precision12-NEXT: orl $3072, %eax # imm = 0xC00246; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)247; precision12-NEXT: fldcw {{[0-9]+}}(%esp)248; precision12-NEXT: fistl {{[0-9]+}}(%esp)249; precision12-NEXT: fldcw (%esp)250; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax251; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)252; precision12-NEXT: fisubl {{[0-9]+}}(%esp)253; precision12-NEXT: fld %st(0)254; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}255; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}256; precision12-NEXT: fmul %st(1), %st257; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}258; precision12-NEXT: fmulp %st, %st(1)259; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}260; precision12-NEXT: fstps {{[0-9]+}}(%esp)261; precision12-NEXT: shll $23, %eax262; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax263; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)264; precision12-NEXT: flds {{[0-9]+}}(%esp)265; precision12-NEXT: addl $20, %esp266; precision12-NEXT: retl267;268; precision18-LABEL: f3:269; precision18: # %bb.0: # %entry270; precision18-NEXT: subl $20, %esp271; precision18-NEXT: flds {{[0-9]+}}(%esp)272; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}273; precision18-NEXT: fnstcw (%esp)274; precision18-NEXT: movzwl (%esp), %eax275; precision18-NEXT: orl $3072, %eax # imm = 0xC00276; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)277; precision18-NEXT: fldcw {{[0-9]+}}(%esp)278; precision18-NEXT: fistl {{[0-9]+}}(%esp)279; precision18-NEXT: fldcw (%esp)280; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax281; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)282; precision18-NEXT: fisubl {{[0-9]+}}(%esp)283; precision18-NEXT: fld %st(0)284; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}285; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}286; precision18-NEXT: fmul %st(1), %st287; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}288; precision18-NEXT: fmul %st(1), %st289; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}290; precision18-NEXT: fmul %st(1), %st291; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}292; precision18-NEXT: fmul %st(1), %st293; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}294; precision18-NEXT: fmulp %st, %st(1)295; precision18-NEXT: fld1296; precision18-NEXT: faddp %st, %st(1)297; precision18-NEXT: fstps {{[0-9]+}}(%esp)298; precision18-NEXT: shll $23, %eax299; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax300; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)301; precision18-NEXT: flds {{[0-9]+}}(%esp)302; precision18-NEXT: addl $20, %esp303; precision18-NEXT: retl304entry:305 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]306 %0 = call float @llvm.pow.f32(float 1.000000e+01, float %x) ; <float> [#uses=1]307 ret float %0308}309 310declare float @llvm.pow.f32(float, float) nounwind readonly311 312define float @f4(float %x) nounwind noinline {313; precision6-LABEL: f4:314; precision6: # %bb.0: # %entry315; precision6-NEXT: subl $8, %esp316; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax317; precision6-NEXT: movl %eax, %ecx318; precision6-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF319; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000320; precision6-NEXT: movl %ecx, (%esp)321; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000322; precision6-NEXT: shrl $23, %eax323; precision6-NEXT: addl $-127, %eax324; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)325; precision6-NEXT: flds (%esp)326; precision6-NEXT: fld %st(0)327; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}328; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}329; precision6-NEXT: fmulp %st, %st(1)330; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}331; precision6-NEXT: fildl {{[0-9]+}}(%esp)332; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}333; precision6-NEXT: faddp %st, %st(1)334; precision6-NEXT: addl $8, %esp335; precision6-NEXT: retl336;337; precision12-LABEL: f4:338; precision12: # %bb.0: # %entry339; precision12-NEXT: subl $8, %esp340; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax341; precision12-NEXT: movl %eax, %ecx342; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF343; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000344; precision12-NEXT: movl %ecx, (%esp)345; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000346; precision12-NEXT: shrl $23, %eax347; precision12-NEXT: addl $-127, %eax348; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)349; precision12-NEXT: flds (%esp)350; precision12-NEXT: fld %st(0)351; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}352; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}353; precision12-NEXT: fmul %st(1), %st354; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}355; precision12-NEXT: fmul %st(1), %st356; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}357; precision12-NEXT: fmulp %st, %st(1)358; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}359; precision12-NEXT: fildl {{[0-9]+}}(%esp)360; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}361; precision12-NEXT: faddp %st, %st(1)362; precision12-NEXT: addl $8, %esp363; precision12-NEXT: retl364;365; precision18-LABEL: f4:366; precision18: # %bb.0: # %entry367; precision18-NEXT: subl $8, %esp368; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax369; precision18-NEXT: movl %eax, %ecx370; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF371; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000372; precision18-NEXT: movl %ecx, (%esp)373; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000374; precision18-NEXT: shrl $23, %eax375; precision18-NEXT: addl $-127, %eax376; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)377; precision18-NEXT: flds (%esp)378; precision18-NEXT: fld %st(0)379; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}380; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}381; precision18-NEXT: fmul %st(1), %st382; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}383; precision18-NEXT: fmul %st(1), %st384; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}385; precision18-NEXT: fmul %st(1), %st386; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}387; precision18-NEXT: fmul %st(1), %st388; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}389; precision18-NEXT: fmulp %st, %st(1)390; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}391; precision18-NEXT: fildl {{[0-9]+}}(%esp)392; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}393; precision18-NEXT: faddp %st, %st(1)394; precision18-NEXT: addl $8, %esp395; precision18-NEXT: retl396entry:397 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]398 %0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1]399 ret float %0400}401 402declare float @llvm.log.f32(float) nounwind readonly403 404define float @f5(float %x) nounwind noinline {405; precision6-LABEL: f5:406; precision6: # %bb.0: # %entry407; precision6-NEXT: subl $8, %esp408; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax409; precision6-NEXT: movl %eax, %ecx410; precision6-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF411; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000412; precision6-NEXT: movl %ecx, (%esp)413; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000414; precision6-NEXT: shrl $23, %eax415; precision6-NEXT: addl $-127, %eax416; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)417; precision6-NEXT: flds (%esp)418; precision6-NEXT: fld %st(0)419; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}420; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}421; precision6-NEXT: fmulp %st, %st(1)422; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}423; precision6-NEXT: fiaddl {{[0-9]+}}(%esp)424; precision6-NEXT: addl $8, %esp425; precision6-NEXT: retl426;427; precision12-LABEL: f5:428; precision12: # %bb.0: # %entry429; precision12-NEXT: subl $8, %esp430; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax431; precision12-NEXT: movl %eax, %ecx432; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF433; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000434; precision12-NEXT: movl %ecx, (%esp)435; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000436; precision12-NEXT: shrl $23, %eax437; precision12-NEXT: addl $-127, %eax438; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)439; precision12-NEXT: flds (%esp)440; precision12-NEXT: fld %st(0)441; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}442; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}443; precision12-NEXT: fmul %st(1), %st444; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}445; precision12-NEXT: fmul %st(1), %st446; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}447; precision12-NEXT: fmulp %st, %st(1)448; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}449; precision12-NEXT: fiaddl {{[0-9]+}}(%esp)450; precision12-NEXT: addl $8, %esp451; precision12-NEXT: retl452;453; precision18-LABEL: f5:454; precision18: # %bb.0: # %entry455; precision18-NEXT: subl $8, %esp456; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax457; precision18-NEXT: movl %eax, %ecx458; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF459; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000460; precision18-NEXT: movl %ecx, (%esp)461; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000462; precision18-NEXT: shrl $23, %eax463; precision18-NEXT: addl $-127, %eax464; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)465; precision18-NEXT: flds (%esp)466; precision18-NEXT: fld %st(0)467; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}468; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}469; precision18-NEXT: fmul %st(1), %st470; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}471; precision18-NEXT: fmul %st(1), %st472; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}473; precision18-NEXT: fmul %st(1), %st474; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}475; precision18-NEXT: fmul %st(1), %st476; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}477; precision18-NEXT: fmulp %st, %st(1)478; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}479; precision18-NEXT: fiaddl {{[0-9]+}}(%esp)480; precision18-NEXT: addl $8, %esp481; precision18-NEXT: retl482entry:483 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]484 %0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1]485 ret float %0486}487 488declare float @llvm.log2.f32(float) nounwind readonly489 490define float @f6(float %x) nounwind noinline {491; precision6-LABEL: f6:492; precision6: # %bb.0: # %entry493; precision6-NEXT: subl $8, %esp494; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax495; precision6-NEXT: movl %eax, %ecx496; precision6-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF497; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000498; precision6-NEXT: movl %ecx, (%esp)499; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000500; precision6-NEXT: shrl $23, %eax501; precision6-NEXT: addl $-127, %eax502; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)503; precision6-NEXT: flds (%esp)504; precision6-NEXT: fld %st(0)505; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}506; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}507; precision6-NEXT: fmulp %st, %st(1)508; precision6-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}509; precision6-NEXT: fildl {{[0-9]+}}(%esp)510; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}511; precision6-NEXT: faddp %st, %st(1)512; precision6-NEXT: addl $8, %esp513; precision6-NEXT: retl514;515; precision12-LABEL: f6:516; precision12: # %bb.0: # %entry517; precision12-NEXT: subl $8, %esp518; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax519; precision12-NEXT: movl %eax, %ecx520; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF521; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000522; precision12-NEXT: movl %ecx, (%esp)523; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000524; precision12-NEXT: shrl $23, %eax525; precision12-NEXT: addl $-127, %eax526; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)527; precision12-NEXT: flds (%esp)528; precision12-NEXT: fld %st(0)529; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}530; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}531; precision12-NEXT: fmul %st(1), %st532; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}533; precision12-NEXT: fmulp %st, %st(1)534; precision12-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}535; precision12-NEXT: fildl {{[0-9]+}}(%esp)536; precision12-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}537; precision12-NEXT: faddp %st, %st(1)538; precision12-NEXT: addl $8, %esp539; precision12-NEXT: retl540;541; precision18-LABEL: f6:542; precision18: # %bb.0: # %entry543; precision18-NEXT: subl $8, %esp544; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax545; precision18-NEXT: movl %eax, %ecx546; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF547; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000548; precision18-NEXT: movl %ecx, (%esp)549; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000550; precision18-NEXT: shrl $23, %eax551; precision18-NEXT: addl $-127, %eax552; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)553; precision18-NEXT: flds (%esp)554; precision18-NEXT: fld %st(0)555; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}556; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}557; precision18-NEXT: fmul %st(1), %st558; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}559; precision18-NEXT: fmul %st(1), %st560; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}561; precision18-NEXT: fmul %st(1), %st562; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}563; precision18-NEXT: fmulp %st, %st(1)564; precision18-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}565; precision18-NEXT: fildl {{[0-9]+}}(%esp)566; precision18-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}567; precision18-NEXT: faddp %st, %st(1)568; precision18-NEXT: addl $8, %esp569; precision18-NEXT: retl570entry:571 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]572 %0 = call float @llvm.log10.f32(float %x) ; <float> [#uses=1]573 ret float %0574}575 576declare float @llvm.log10.f32(float) nounwind readonly577